================================================================ == Vivado HLS Report for 'apint_arith' ================================================================ * Date: Mon Mar 5 11:22:31 2018 * Version: 2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017) * Project: vivado_test * Solution: solution3 * Product family: zynq * Target device: xc7z020clg484-1 ================================================================ == Performance Estimates ================================================================ + Timing (ns): * Summary: +--------+-------+----------+------------+ | Clock | Target| Estimated| Uncertainty| +--------+-------+----------+------------+ |ap_clk | 10.00| 7.98| 1.25| +--------+-------+----------+------------+ + Latency (clock cycles): * Summary: +------+------+------+------+---------+ | Latency | Interval | Pipeline| | min | max | min | max | Type | +------+------+------+------+---------+ | 1026| 1026| 1026| 1026| none | +------+------+------+------+---------+ + Detail: * Instance: N/A * Loop: N/A ================================================================ == Utilization Estimates ================================================================ * Summary: +-----------------+---------+-------+--------+-------+ | Name | BRAM_18K| DSP48E| FF | LUT | +-----------------+---------+-------+--------+-------+ |DSP | -| -| -| -| |Expression | -| -| -| -| |FIFO | -| -| -| -| |Instance | 0| 16| 5709| 7506| |Memory | -| -| -| -| |Multiplexer | -| -| -| 2193| |Register | -| -| 1027| -| +-----------------+---------+-------+--------+-------+ |Total | 0| 16| 6736| 9699| +-----------------+---------+-------+--------+-------+ |Available | 280| 220| 106400| 53200| +-----------------+---------+-------+--------+-------+ |Utilization (%) | 0| 7| 6| 18| +-----------------+---------+-------+--------+-------+ + Detail: * Instance: +------------------------------+----------------------------+---------+-------+------+------+ | Instance | Module | BRAM_18K| DSP48E| FF | LUT | +------------------------------+----------------------------+---------+-------+------+------+ |apint_arith_AXILiteS_s_axi_U |apint_arith_AXILiteS_s_axi | 0| 0| 3130| 6180| |apint_arith_add_5cud_U2 |apint_arith_add_5cud | 0| 0| 580| 132| |apint_arith_mul_5bkb_U1 |apint_arith_mul_5bkb | 0| 16| 441| 256| |apint_arith_sdiv_dEe_U3 |apint_arith_sdiv_dEe | 0| 0| 779| 469| |apint_arith_srem_eOg_U4 |apint_arith_srem_eOg | 0| 0| 779| 469| +------------------------------+----------------------------+---------+-------+------+------+ |Total | | 0| 16| 5709| 7506| +------------------------------+----------------------------+---------+-------+------+------+ * DSP48: N/A * Memory: N/A * FIFO: N/A * Expression: N/A * Multiplexer: +-----------+------+-----------+-----+-----------+ | Name | LUT | Input Size| Bits| Total Bits| +-----------+------+-----------+-----+-----------+ |ap_NS_fsm | 2193| 1028| 1| 1028| +-----------+------+-----------+-----+-----------+ |Total | 2193| 1028| 1| 1028| +-----------+------+-----------+-----+-----------+ * Register: +-----------+------+----+------+-----------+ | Name | FF | LUT| Bits | Const Bits| +-----------+------+----+------+-----------+ |ap_CS_fsm | 1027| 0| 1027| 0| +-----------+------+----+------+-----------+ |Total | 1027| 0| 1027| 0| +-----------+------+----+------+-----------+ ================================================================ == Interface ================================================================ * Summary: +------------------------+-----+------+------------+--------------+--------------+ | RTL Ports | Dir | Bits | Protocol | Source Object| C Type | +------------------------+-----+------+------------+--------------+--------------+ |s_axi_AXILiteS_AWVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_AWREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_AWADDR | in | 9| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WDATA | in | 32| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WSTRB | in | 4| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARADDR | in | 9| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RVALID | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RREADY | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RDATA | out | 32| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RRESP | out | 2| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BVALID | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BREADY | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BRESP | out | 2| s_axi | AXILiteS | scalar | |ap_clk | in | 1| ap_ctrl_hs | apint_arith | return value | |ap_rst_n | in | 1| ap_ctrl_hs | apint_arith | return value | |interrupt | out | 1| ap_ctrl_hs | apint_arith | return value | |out1_V | out | 1024| ap_vld | out1_V | pointer | |out1_V_ap_vld | out | 1| ap_vld | out1_V | pointer | |out2_V | out | 513| ap_vld | out2_V | pointer | |out2_V_ap_vld | out | 1| ap_vld | out2_V | pointer | |out3_V | out | 1024| ap_vld | out3_V | pointer | |out3_V_ap_vld | out | 1| ap_vld | out3_V | pointer | |out4_V | out | 512| ap_vld | out4_V | pointer | |out4_V_ap_vld | out | 1| ap_vld | out4_V | pointer | +------------------------+-----+------+------------+--------------+--------------+