================================================================
== Vivado HLS Report for 'apint_arith'
================================================================
* Date:           Mon Mar  5 11:16:26 2018

* Version:        2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017)
* Project:        vivado_test
* Solution:       solution2
* Product family: zynq
* Target device:  xc7z020clg484-1


================================================================
== Performance Estimates
================================================================
+ Timing (ns): 
    * Summary: 
    +--------+-------+----------+------------+
    |  Clock | Target| Estimated| Uncertainty|
    +--------+-------+----------+------------+
    |ap_clk  |  10.00|      8.51|        1.25|
    +--------+-------+----------+------------+

+ Latency (clock cycles): 
    * Summary: 
    +-----+-----+-----+-----+---------+
    |  Latency  |  Interval | Pipeline|
    | min | max | min | max |   Type  |
    +-----+-----+-----+-----+---------+
    |   51|   51|   51|   51|   none  |
    +-----+-----+-----+-----+---------+

    + Detail: 
        * Instance: 
        N/A

        * Loop: 
        N/A



================================================================
== Utilization Estimates
================================================================
* Summary: 
+-----------------+---------+-------+--------+-------+
|       Name      | BRAM_18K| DSP48E|   FF   |  LUT  |
+-----------------+---------+-------+--------+-------+
|DSP              |        -|      -|       -|      -|
|Expression       |        -|      3|       0|     60|
|FIFO             |        -|      -|       -|      -|
|Instance         |        0|      -|    1281|    978|
|Memory           |        -|      -|       -|      -|
|Multiplexer      |        -|      -|       -|    229|
|Register         |        -|      -|     108|      -|
+-----------------+---------+-------+--------+-------+
|Total            |        0|      3|    1389|   1267|
+-----------------+---------+-------+--------+-------+
|Available        |      280|    220|  106400|  53200|
+-----------------+---------+-------+--------+-------+
|Utilization (%)  |        0|      1|       1|      2|
+-----------------+---------+-------+--------+-------+

+ Detail: 
    * Instance: 
    +------------------------------+----------------------------+---------+-------+-----+-----+
    |           Instance           |           Module           | BRAM_18K| DSP48E|  FF | LUT |
    +------------------------------+----------------------------+---------+-------+-----+-----+
    |apint_arith_AXILiteS_s_axi_U  |apint_arith_AXILiteS_s_axi  |        0|      0|  204|  328|
    |apint_arith_sdiv_bkb_U1       |apint_arith_sdiv_bkb        |        0|      0|  490|  296|
    |apint_arith_srem_cud_U2       |apint_arith_srem_cud        |        0|      0|  587|  354|
    +------------------------------+----------------------------+---------+-------+-----+-----+
    |Total                         |                            |        0|      0| 1281|  978|
    +------------------------------+----------------------------+---------+-------+-----+-----+

    * DSP48: 
    N/A

    * Memory: 
    N/A

    * FIFO: 
    N/A

    * Expression: 
    +--------------+----------+-------+---+----+------------+------------+
    | Variable Name| Operation| DSP48E| FF| LUT| Bitwidth P0| Bitwidth P1|
    +--------------+----------+-------+---+----+------------+------------+
    |out1_V        |     *    |      3|  0|  20|          32|          24|
    |out2_V        |     +    |      0|  0|  40|          33|          33|
    +--------------+----------+-------+---+----+------------+------------+
    |Total         |          |      3|  0|  60|          65|          57|
    +--------------+----------+-------+---+----+------------+------------+

    * Multiplexer: 
    +-----------+-----+-----------+-----+-----------+
    |    Name   | LUT | Input Size| Bits| Total Bits|
    +-----------+-----+-----------+-----+-----------+
    |ap_NS_fsm  |  229|         53|    1|         53|
    +-----------+-----+-----------+-----+-----------+
    |Total      |  229|         53|    1|         53|
    +-----------+-----+-----------+-----+-----------+

    * Register: 
    +--------------------+----+----+-----+-----------+
    |        Name        | FF | LUT| Bits| Const Bits|
    +--------------------+----+----+-----+-----------+
    |ap_CS_fsm           |  52|   0|   52|          0|
    |inA_V_read_reg_170  |  24|   0|   24|          0|
    |inB_V_read_reg_164  |  32|   0|   32|          0|
    +--------------------+----+----+-----+-----------+
    |Total               | 108|   0|  108|          0|
    +--------------------+----+----+-----+-----------+



================================================================
== Interface
================================================================
* Summary: 
+------------------------+-----+-----+------------+--------------+--------------+
|        RTL Ports       | Dir | Bits|  Protocol  | Source Object|    C Type    |
+------------------------+-----+-----+------------+--------------+--------------+
|s_axi_AXILiteS_AWVALID  |  in |    1|    s_axi   |   AXILiteS   |    scalar    |
|s_axi_AXILiteS_AWREADY  | out |    1|    s_axi   |   AXILiteS   |    scalar    |
|s_axi_AXILiteS_AWADDR   |  in |    6|    s_axi   |   AXILiteS   |    scalar    |
|s_axi_AXILiteS_WVALID   |  in |    1|    s_axi   |   AXILiteS   |    scalar    |
|s_axi_AXILiteS_WREADY   | out |    1|    s_axi   |   AXILiteS   |    scalar    |
|s_axi_AXILiteS_WDATA    |  in |   32|    s_axi   |   AXILiteS   |    scalar    |
|s_axi_AXILiteS_WSTRB    |  in |    4|    s_axi   |   AXILiteS   |    scalar    |
|s_axi_AXILiteS_ARVALID  |  in |    1|    s_axi   |   AXILiteS   |    scalar    |
|s_axi_AXILiteS_ARREADY  | out |    1|    s_axi   |   AXILiteS   |    scalar    |
|s_axi_AXILiteS_ARADDR   |  in |    6|    s_axi   |   AXILiteS   |    scalar    |
|s_axi_AXILiteS_RVALID   | out |    1|    s_axi   |   AXILiteS   |    scalar    |
|s_axi_AXILiteS_RREADY   |  in |    1|    s_axi   |   AXILiteS   |    scalar    |
|s_axi_AXILiteS_RDATA    | out |   32|    s_axi   |   AXILiteS   |    scalar    |
|s_axi_AXILiteS_RRESP    | out |    2|    s_axi   |   AXILiteS   |    scalar    |
|s_axi_AXILiteS_BVALID   | out |    1|    s_axi   |   AXILiteS   |    scalar    |
|s_axi_AXILiteS_BREADY   |  in |    1|    s_axi   |   AXILiteS   |    scalar    |
|s_axi_AXILiteS_BRESP    | out |    2|    s_axi   |   AXILiteS   |    scalar    |
|ap_clk                  |  in |    1| ap_ctrl_hs |  apint_arith | return value |
|ap_rst_n                |  in |    1| ap_ctrl_hs |  apint_arith | return value |
|interrupt               | out |    1| ap_ctrl_hs |  apint_arith | return value |
|out1_V                  | out |   56|   ap_vld   |    out1_V    |    pointer   |
|out1_V_ap_vld           | out |    1|   ap_vld   |    out1_V    |    pointer   |
|out2_V                  | out |   33|   ap_vld   |    out2_V    |    pointer   |
|out2_V_ap_vld           | out |    1|   ap_vld   |    out2_V    |    pointer   |
|out3_V                  | out |   48|   ap_vld   |    out3_V    |    pointer   |
|out3_V_ap_vld           | out |    1|   ap_vld   |    out3_V    |    pointer   |
|out4_V                  | out |   24|   ap_vld   |    out4_V    |    pointer   |
|out4_V_ap_vld           | out |    1|   ap_vld   |    out4_V    |    pointer   |
+------------------------+-----+-----+------------+--------------+--------------+