================================================================
== Vivado HLS Report for 'apint_arith'
================================================================
* Date:           Mon Mar  5 11:16:26 2018

* Version:        2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017)
* Project:        vivado_test
* Solution:       solution2
* Product family: zynq
* Target device:  xc7z020clg484-1


================================================================
== Performance Estimates
================================================================
+ Timing (ns): 
    * Summary: 
    +--------+-------+----------+------------+
    |  Clock | Target| Estimated| Uncertainty|
    +--------+-------+----------+------------+
    |ap_clk  |  10.00|      8.51|        1.25|
    +--------+-------+----------+------------+

+ Latency (clock cycles): 
    * Summary: 
    +-----+-----+-----+-----+---------+
    |  Latency  |  Interval | Pipeline|
    | min | max | min | max |   Type  |
    +-----+-----+-----+-----+---------+
    |   51|   51|   51|   51|   none  |
    +-----+-----+-----+-----+---------+

    + Detail: 
        * Instance: 
        N/A

        * Loop: 
        N/A

============================================================
+ Verbose Summary: Synthesis Manager
============================================================
InlineROM: 1
ExposeGlobal: 0
============================================================
+ Verbose Summary: CDFG Model
============================================================
IsTopModel: 1
ResetActiveHigh: 1
IsCombinational: 0
IsDatapathOnly: 0
HasWiredReturn: 1
HasMFsm: 0
HasVarLatency: 1
IsPipeline: 0
IsRtlPipelined: 0
IsInstanceOverlapped: 0
IsDontTouch: 0
HasImplIP: 0
IsGatedGlobalClock: 0


============================================================
+ Verbose Summary: Schedule
============================================================
* Number of FSM states : 52
* Pipeline : 0
* Dataflow Pipeline: 0

* FSM state transitions: 
1 --> 
	2  / true
2 --> 
	3  / true
3 --> 
	4  / true
4 --> 
	5  / true
5 --> 
	6  / true
6 --> 
	7  / true
7 --> 
	8  / true
8 --> 
	9  / true
9 --> 
	10  / true
10 --> 
	11  / true
11 --> 
	12  / true
12 --> 
	13  / true
13 --> 
	14  / true
14 --> 
	15  / true
15 --> 
	16  / true
16 --> 
	17  / true
17 --> 
	18  / true
18 --> 
	19  / true
19 --> 
	20  / true
20 --> 
	21  / true
21 --> 
	22  / true
22 --> 
	23  / true
23 --> 
	24  / true
24 --> 
	25  / true
25 --> 
	26  / true
26 --> 
	27  / true
27 --> 
	28  / true
28 --> 
	29  / true
29 --> 
	30  / true
30 --> 
	31  / true
31 --> 
	32  / true
32 --> 
	33  / true
33 --> 
	34  / true
34 --> 
	35  / true
35 --> 
	36  / true
36 --> 
	37  / true
37 --> 
	38  / true
38 --> 
	39  / true
39 --> 
	40  / true
40 --> 
	41  / true
41 --> 
	42  / true
42 --> 
	43  / true
43 --> 
	44  / true
44 --> 
	45  / true
45 --> 
	46  / true
46 --> 
	47  / true
47 --> 
	48  / true
48 --> 
	49  / true
49 --> 
	50  / true
50 --> 
	51  / true
51 --> 
	52  / true
52 --> 

* FSM state operations: 

 <State 1> : 5.55ns
ST_1 : Operation 53 [1/1] (1.00ns)   --->   "%inD_V_read = call i48 @_ssdm_op_Read.s_axilite.i48(i48 %inD_V)"   --->   Core 10 's_axilite' <Latency = 0> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write'>
ST_1 : Operation 54 [1/1] (1.00ns)   --->   "%inC_V_read = call i40 @_ssdm_op_Read.s_axilite.i40(i40 %inC_V)"   --->   Core 10 's_axilite' <Latency = 0> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write'>
ST_1 : Operation 55 [1/1] (1.00ns)   --->   "%inB_V_read = call i32 @_ssdm_op_Read.s_axilite.i32(i32 %inB_V)"   --->   Core 10 's_axilite' <Latency = 0> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write'>
ST_1 : Operation 56 [1/1] (1.00ns)   --->   "%inA_V_read = call i24 @_ssdm_op_Read.s_axilite.i24(i24 %inA_V)"   --->   Core 10 's_axilite' <Latency = 0> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write'>
ST_1 : Operation 57 [1/1] (0.00ns)   --->   "%tmp = sext i24 %inA_V_read to i40" [vivado_test/prec_test.cpp:8]
ST_1 : Operation 58 [44/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_1 : Operation 59 [1/1] (0.00ns)   --->   "%tmp_3 = sext i24 %inA_V_read to i48" [vivado_test/prec_test.cpp:9]
ST_1 : Operation 60 [52/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 2> : 8.51ns
ST_2 : Operation 61 [1/1] (0.00ns)   --->   "%lhs_V = sext i24 %inA_V_read to i56" [vivado_test/prec_test.cpp:6]
ST_2 : Operation 62 [1/1] (0.00ns)   --->   "%rhs_V = sext i32 %inB_V_read to i56" [vivado_test/prec_test.cpp:6]
ST_2 : Operation 63 [1/1] (8.51ns)   --->   "%r_V = mul nsw i56 %rhs_V, %lhs_V" [vivado_test/prec_test.cpp:6]   --->   Core 16 'Mul' <Latency = 0> <II = 1> <Delay = 8.51> <FuncUnit> <Opcode : 'mul'> <InPorts = 2> <OutPorts = 1>
ST_2 : Operation 64 [1/1] (0.00ns)   --->   "call void @_ssdm_op_Write.ap_auto.i56P(i56* %out1_V, i56 %r_V)" [vivado_test/prec_test.cpp:6]
ST_2 : Operation 65 [1/1] (0.00ns)   --->   "%lhs_V_1 = sext i32 %inB_V_read to i33" [vivado_test/prec_test.cpp:7]
ST_2 : Operation 66 [1/1] (0.00ns)   --->   "%rhs_V_1 = sext i24 %inA_V_read to i33" [vivado_test/prec_test.cpp:7]
ST_2 : Operation 67 [1/1] (2.55ns)   --->   "%r_V_1 = add nsw i33 %lhs_V_1, %rhs_V_1" [vivado_test/prec_test.cpp:7]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.55> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_2 : Operation 68 [1/1] (0.00ns)   --->   "call void @_ssdm_op_Write.ap_auto.i33P(i33* %out2_V, i33 %r_V_1)" [vivado_test/prec_test.cpp:7]
ST_2 : Operation 69 [43/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_2 : Operation 70 [51/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 3> : 4.55ns
ST_3 : Operation 71 [42/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_3 : Operation 72 [50/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 4> : 4.55ns
ST_4 : Operation 73 [41/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_4 : Operation 74 [49/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 5> : 4.55ns
ST_5 : Operation 75 [40/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_5 : Operation 76 [48/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 6> : 4.55ns
ST_6 : Operation 77 [39/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_6 : Operation 78 [47/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 7> : 4.55ns
ST_7 : Operation 79 [38/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_7 : Operation 80 [46/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 8> : 4.55ns
ST_8 : Operation 81 [37/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_8 : Operation 82 [45/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 9> : 4.55ns
ST_9 : Operation 83 [36/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_9 : Operation 84 [44/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 10> : 4.55ns
ST_10 : Operation 85 [35/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_10 : Operation 86 [43/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 11> : 4.55ns
ST_11 : Operation 87 [34/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_11 : Operation 88 [42/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 12> : 4.55ns
ST_12 : Operation 89 [33/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_12 : Operation 90 [41/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 13> : 4.55ns
ST_13 : Operation 91 [32/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_13 : Operation 92 [40/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 14> : 4.55ns
ST_14 : Operation 93 [31/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_14 : Operation 94 [39/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 15> : 4.55ns
ST_15 : Operation 95 [30/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_15 : Operation 96 [38/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 16> : 4.55ns
ST_16 : Operation 97 [29/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_16 : Operation 98 [37/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 17> : 4.55ns
ST_17 : Operation 99 [28/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_17 : Operation 100 [36/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 18> : 4.55ns
ST_18 : Operation 101 [27/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_18 : Operation 102 [35/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 19> : 4.55ns
ST_19 : Operation 103 [26/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_19 : Operation 104 [34/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 20> : 4.55ns
ST_20 : Operation 105 [25/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_20 : Operation 106 [33/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 21> : 4.55ns
ST_21 : Operation 107 [24/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_21 : Operation 108 [32/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 22> : 4.55ns
ST_22 : Operation 109 [23/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_22 : Operation 110 [31/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 23> : 4.55ns
ST_23 : Operation 111 [22/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_23 : Operation 112 [30/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 24> : 4.55ns
ST_24 : Operation 113 [21/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_24 : Operation 114 [29/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 25> : 4.55ns
ST_25 : Operation 115 [20/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_25 : Operation 116 [28/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 26> : 4.55ns
ST_26 : Operation 117 [19/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_26 : Operation 118 [27/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 27> : 4.55ns
ST_27 : Operation 119 [18/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_27 : Operation 120 [26/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 28> : 4.55ns
ST_28 : Operation 121 [17/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_28 : Operation 122 [25/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 29> : 4.55ns
ST_29 : Operation 123 [16/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_29 : Operation 124 [24/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 30> : 4.55ns
ST_30 : Operation 125 [15/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_30 : Operation 126 [23/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 31> : 4.55ns
ST_31 : Operation 127 [14/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_31 : Operation 128 [22/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 32> : 4.55ns
ST_32 : Operation 129 [13/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_32 : Operation 130 [21/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 33> : 4.55ns
ST_33 : Operation 131 [12/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_33 : Operation 132 [20/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 34> : 4.55ns
ST_34 : Operation 133 [11/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_34 : Operation 134 [19/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 35> : 4.55ns
ST_35 : Operation 135 [10/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_35 : Operation 136 [18/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 36> : 4.55ns
ST_36 : Operation 137 [9/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_36 : Operation 138 [17/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 37> : 4.55ns
ST_37 : Operation 139 [8/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_37 : Operation 140 [16/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 38> : 4.55ns
ST_38 : Operation 141 [7/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_38 : Operation 142 [15/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 39> : 4.55ns
ST_39 : Operation 143 [6/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_39 : Operation 144 [14/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 40> : 4.55ns
ST_40 : Operation 145 [5/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_40 : Operation 146 [13/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 41> : 4.55ns
ST_41 : Operation 147 [4/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_41 : Operation 148 [12/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 42> : 4.55ns
ST_42 : Operation 149 [3/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_42 : Operation 150 [11/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 43> : 4.55ns
ST_43 : Operation 151 [2/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_43 : Operation 152 [10/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 44> : 4.55ns
ST_44 : Operation 153 [1/44] (4.37ns)   --->   "%tmp_1 = sdiv i40 %inC_V_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_44 : Operation 154 [1/1] (0.00ns)   --->   "%tmp_2 = sext i40 %tmp_1 to i48" [vivado_test/prec_test.cpp:8]
ST_44 : Operation 155 [1/1] (0.00ns)   --->   "call void @_ssdm_op_Write.ap_auto.i48P(i48* %out3_V, i48 %tmp_2)" [vivado_test/prec_test.cpp:8]
ST_44 : Operation 156 [9/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 45> : 4.55ns
ST_45 : Operation 157 [8/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 46> : 4.55ns
ST_46 : Operation 158 [7/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 47> : 4.55ns
ST_47 : Operation 159 [6/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 48> : 4.55ns
ST_48 : Operation 160 [5/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 49> : 4.55ns
ST_49 : Operation 161 [4/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 50> : 4.55ns
ST_50 : Operation 162 [3/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 51> : 4.55ns
ST_51 : Operation 163 [2/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 52> : 4.55ns
ST_52 : Operation 164 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecBitsMap(i24 %inA_V), !map !55"
ST_52 : Operation 165 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecBitsMap(i32 %inB_V), !map !61"
ST_52 : Operation 166 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecBitsMap(i40 %inC_V), !map !65"
ST_52 : Operation 167 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecBitsMap(i48 %inD_V), !map !69"
ST_52 : Operation 168 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecBitsMap(i56* %out1_V), !map !73"
ST_52 : Operation 169 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecBitsMap(i33* %out2_V), !map !77"
ST_52 : Operation 170 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecBitsMap(i48* %out3_V), !map !81"
ST_52 : Operation 171 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecBitsMap(i24* %out4_V), !map !85"
ST_52 : Operation 172 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecTopModule([12 x i8]* @apint_arith_str) nounwind"
ST_52 : Operation 173 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(i32 0, [10 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1, [1 x i8]* @p_str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1) nounwind" [vivado_test/prec_test.cpp:5]
ST_52 : Operation 174 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(i48 %inD_V, [10 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1, [1 x i8]* @p_str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1) nounwind" [vivado_test/prec_test.cpp:5]
ST_52 : Operation 175 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(i40 %inC_V, [10 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1, [1 x i8]* @p_str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1) nounwind" [vivado_test/prec_test.cpp:5]
ST_52 : Operation 176 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(i32 %inB_V, [10 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1, [1 x i8]* @p_str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1) nounwind" [vivado_test/prec_test.cpp:5]
ST_52 : Operation 177 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(i24 %inA_V, [10 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1, [1 x i8]* @p_str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1) nounwind" [vivado_test/prec_test.cpp:5]
ST_52 : Operation 178 [1/52] (4.55ns)   --->   "%tmp_4 = srem i48 %inD_V_read, %tmp_3" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 51> <II = 24> <Delay = 4.55> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_52 : Operation 179 [1/1] (0.00ns)   --->   "%r_V_2 = trunc i48 %tmp_4 to i24" [vivado_test/prec_test.cpp:9]
ST_52 : Operation 180 [1/1] (0.00ns)   --->   "call void @_ssdm_op_Write.ap_auto.i24P(i24* %out4_V, i24 %r_V_2)" [vivado_test/prec_test.cpp:9]
ST_52 : Operation 181 [1/1] (0.00ns)   --->   "ret void" [vivado_test/prec_test.cpp:10]


============================================================
+ Verbose Summary: Binding
============================================================
STG Binding: 
---------------- STG Properties BEGIN ----------------
- Is combinational: 0
- Is one-state seq: 0
- Is datapath-only: 0
- Is pipelined: 0
- Is top level: 1
Port [ Return ] is wired: 1; IO mode=ap_ctrl_hs:ce=0
Port [ inA_V]:  wired=1; compound=0; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=0; pingpong=0; private_global=0; IO mode=ap_none:ce=0
Port [ inB_V]:  wired=1; compound=0; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=0; pingpong=0; private_global=0; IO mode=ap_none:ce=0
Port [ inC_V]:  wired=1; compound=0; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=0; pingpong=0; private_global=0; IO mode=ap_none:ce=0
Port [ inD_V]:  wired=1; compound=0; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=0; pingpong=0; private_global=0; IO mode=ap_none:ce=0
Port [ out1_V]:  wired=1; compound=0; hidden=0; nouse=0; global=0; static=0; extern=0; dir=1; type=0; pingpong=0; private_global=0; IO mode=ap_vld:ce=0
Port [ out2_V]:  wired=1; compound=0; hidden=0; nouse=0; global=0; static=0; extern=0; dir=1; type=0; pingpong=0; private_global=0; IO mode=ap_vld:ce=0
Port [ out3_V]:  wired=1; compound=0; hidden=0; nouse=0; global=0; static=0; extern=0; dir=1; type=0; pingpong=0; private_global=0; IO mode=ap_vld:ce=0
Port [ out4_V]:  wired=1; compound=0; hidden=0; nouse=0; global=0; static=0; extern=0; dir=1; type=0; pingpong=0; private_global=0; IO mode=ap_vld:ce=0
---------------- STG Properties END ------------------

---------------- Datapath Model BEGIN ----------------

<LifeTime>
<method=bitvector/>
inD_V_read   (read         ) [ 00111111111111111111111111111111111111111111111111111]
inC_V_read   (read         ) [ 00111111111111111111111111111111111111111111100000000]
inB_V_read   (read         ) [ 00100000000000000000000000000000000000000000000000000]
inA_V_read   (read         ) [ 00100000000000000000000000000000000000000000000000000]
tmp          (sext         ) [ 00111111111111111111111111111111111111111111100000000]
tmp_3        (sext         ) [ 00111111111111111111111111111111111111111111111111111]
lhs_V        (sext         ) [ 00000000000000000000000000000000000000000000000000000]
rhs_V        (sext         ) [ 00000000000000000000000000000000000000000000000000000]
r_V          (mul          ) [ 00000000000000000000000000000000000000000000000000000]
StgValue_64  (write        ) [ 00000000000000000000000000000000000000000000000000000]
lhs_V_1      (sext         ) [ 00000000000000000000000000000000000000000000000000000]
rhs_V_1      (sext         ) [ 00000000000000000000000000000000000000000000000000000]
r_V_1        (add          ) [ 00000000000000000000000000000000000000000000000000000]
StgValue_68  (write        ) [ 00000000000000000000000000000000000000000000000000000]
tmp_1        (sdiv         ) [ 00000000000000000000000000000000000000000000000000000]
tmp_2        (sext         ) [ 00000000000000000000000000000000000000000000000000000]
StgValue_155 (write        ) [ 00000000000000000000000000000000000000000000000000000]
StgValue_164 (specbitsmap  ) [ 00000000000000000000000000000000000000000000000000000]
StgValue_165 (specbitsmap  ) [ 00000000000000000000000000000000000000000000000000000]
StgValue_166 (specbitsmap  ) [ 00000000000000000000000000000000000000000000000000000]
StgValue_167 (specbitsmap  ) [ 00000000000000000000000000000000000000000000000000000]
StgValue_168 (specbitsmap  ) [ 00000000000000000000000000000000000000000000000000000]
StgValue_169 (specbitsmap  ) [ 00000000000000000000000000000000000000000000000000000]
StgValue_170 (specbitsmap  ) [ 00000000000000000000000000000000000000000000000000000]
StgValue_171 (specbitsmap  ) [ 00000000000000000000000000000000000000000000000000000]
StgValue_172 (spectopmodule) [ 00000000000000000000000000000000000000000000000000000]
StgValue_173 (specinterface) [ 00000000000000000000000000000000000000000000000000000]
StgValue_174 (specinterface) [ 00000000000000000000000000000000000000000000000000000]
StgValue_175 (specinterface) [ 00000000000000000000000000000000000000000000000000000]
StgValue_176 (specinterface) [ 00000000000000000000000000000000000000000000000000000]
StgValue_177 (specinterface) [ 00000000000000000000000000000000000000000000000000000]
tmp_4        (srem         ) [ 00000000000000000000000000000000000000000000000000000]
r_V_2        (trunc        ) [ 00000000000000000000000000000000000000000000000000000]
StgValue_180 (write        ) [ 00000000000000000000000000000000000000000000000000000]
StgValue_181 (ret          ) [ 00000000000000000000000000000000000000000000000000000]
</LifeTime>

<model>

<comp_list>
<comp id="0" class="1000" name="inA_V">
<pin_list>
<pin id="1" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="inA_V"/></StgValue>
</bind>
</comp>

<comp id="2" class="1000" name="inB_V">
<pin_list>
<pin id="3" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="inB_V"/></StgValue>
</bind>
</comp>

<comp id="4" class="1000" name="inC_V">
<pin_list>
<pin id="5" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="inC_V"/></StgValue>
</bind>
</comp>

<comp id="6" class="1000" name="inD_V">
<pin_list>
<pin id="7" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="inD_V"/></StgValue>
</bind>
</comp>

<comp id="8" class="1000" name="out1_V">
<pin_list>
<pin id="9" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="out1_V"/></StgValue>
</bind>
</comp>

<comp id="10" class="1000" name="out2_V">
<pin_list>
<pin id="11" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="out2_V"/></StgValue>
</bind>
</comp>

<comp id="12" class="1000" name="out3_V">
<pin_list>
<pin id="13" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="out3_V"/></StgValue>
</bind>
</comp>

<comp id="14" class="1000" name="out4_V">
<pin_list>
<pin id="15" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="out4_V"/></StgValue>
</bind>
</comp>

<comp id="16" class="1001" name="const_16">
<pin_list>
<pin id="17" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_Read.s_axilite.i48"/></StgValue>
</bind>
</comp>

<comp id="18" class="1001" name="const_18">
<pin_list>
<pin id="19" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_Read.s_axilite.i40"/></StgValue>
</bind>
</comp>

<comp id="20" class="1001" name="const_20">
<pin_list>
<pin id="21" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_Read.s_axilite.i32"/></StgValue>
</bind>
</comp>

<comp id="22" class="1001" name="const_22">
<pin_list>
<pin id="23" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_Read.s_axilite.i24"/></StgValue>
</bind>
</comp>

<comp id="24" class="1001" name="const_24">
<pin_list>
<pin id="25" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_Write.ap_auto.i56P"/></StgValue>
</bind>
</comp>

<comp id="26" class="1001" name="const_26">
<pin_list>
<pin id="27" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_Write.ap_auto.i33P"/></StgValue>
</bind>
</comp>

<comp id="28" class="1001" name="const_28">
<pin_list>
<pin id="29" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_Write.ap_auto.i48P"/></StgValue>
</bind>
</comp>

<comp id="30" class="1001" name="const_30">
<pin_list>
<pin id="31" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecBitsMap"/></StgValue>
</bind>
</comp>

<comp id="32" class="1001" name="const_32">
<pin_list>
<pin id="33" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecTopModule"/></StgValue>
</bind>
</comp>

<comp id="34" class="1001" name="const_34">
<pin_list>
<pin id="35" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="apint_arith_str"/></StgValue>
</bind>
</comp>

<comp id="36" class="1001" name="const_36">
<pin_list>
<pin id="37" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecInterface"/></StgValue>
</bind>
</comp>

<comp id="38" class="1001" name="const_38">
<pin_list>
<pin id="39" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="40" class="1001" name="const_40">
<pin_list>
<pin id="41" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str"/></StgValue>
</bind>
</comp>

<comp id="42" class="1001" name="const_42">
<pin_list>
<pin id="43" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str1"/></StgValue>
</bind>
</comp>

<comp id="44" class="1001" name="const_44">
<pin_list>
<pin id="45" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_Write.ap_auto.i24P"/></StgValue>
</bind>
</comp>

<comp id="46" class="1004" name="inD_V_read_read_fu_46">
<pin_list>
<pin id="47" dir="0" index="0" bw="48" slack="0"/>
<pin id="48" dir="0" index="1" bw="48" slack="0"/>
<pin id="49" dir="1" index="2" bw="48" slack="0"/>
</pin_list>
<bind>
<opcode="read(1150) " fcode="read"/>
<opset="inD_V_read/1 "/>
</bind>
</comp>

<comp id="52" class="1004" name="inC_V_read_read_fu_52">
<pin_list>
<pin id="53" dir="0" index="0" bw="40" slack="0"/>
<pin id="54" dir="0" index="1" bw="40" slack="0"/>
<pin id="55" dir="1" index="2" bw="40" slack="0"/>
</pin_list>
<bind>
<opcode="read(1150) " fcode="read"/>
<opset="inC_V_read/1 "/>
</bind>
</comp>

<comp id="58" class="1004" name="inB_V_read_read_fu_58">
<pin_list>
<pin id="59" dir="0" index="0" bw="32" slack="0"/>
<pin id="60" dir="0" index="1" bw="32" slack="0"/>
<pin id="61" dir="1" index="2" bw="32" slack="1"/>
</pin_list>
<bind>
<opcode="read(1150) " fcode="read"/>
<opset="inB_V_read/1 "/>
</bind>
</comp>

<comp id="64" class="1004" name="inA_V_read_read_fu_64">
<pin_list>
<pin id="65" dir="0" index="0" bw="24" slack="0"/>
<pin id="66" dir="0" index="1" bw="24" slack="0"/>
<pin id="67" dir="1" index="2" bw="24" slack="0"/>
</pin_list>
<bind>
<opcode="read(1150) " fcode="read"/>
<opset="inA_V_read/1 "/>
</bind>
</comp>

<comp id="70" class="1004" name="StgValue_64_write_fu_70">
<pin_list>
<pin id="71" dir="0" index="0" bw="0" slack="0"/>
<pin id="72" dir="0" index="1" bw="56" slack="0"/>
<pin id="73" dir="0" index="2" bw="56" slack="0"/>
<pin id="74" dir="1" index="3" bw="0" slack="2147483647"/>
</pin_list>
<bind>
<opcode="write(1151) " fcode="write"/>
<opset="StgValue_64/2 "/>
</bind>
</comp>

<comp id="77" class="1004" name="StgValue_68_write_fu_77">
<pin_list>
<pin id="78" dir="0" index="0" bw="0" slack="0"/>
<pin id="79" dir="0" index="1" bw="33" slack="0"/>
<pin id="80" dir="0" index="2" bw="33" slack="0"/>
<pin id="81" dir="1" index="3" bw="0" slack="2147483647"/>
</pin_list>
<bind>
<opcode="write(1151) " fcode="write"/>
<opset="StgValue_68/2 "/>
</bind>
</comp>

<comp id="84" class="1004" name="StgValue_155_write_fu_84">
<pin_list>
<pin id="85" dir="0" index="0" bw="0" slack="0"/>
<pin id="86" dir="0" index="1" bw="48" slack="0"/>
<pin id="87" dir="0" index="2" bw="40" slack="0"/>
<pin id="88" dir="1" index="3" bw="0" slack="2147483647"/>
</pin_list>
<bind>
<opcode="write(1151) " fcode="write"/>
<opset="StgValue_155/44 "/>
</bind>
</comp>

<comp id="91" class="1004" name="StgValue_180_write_fu_91">
<pin_list>
<pin id="92" dir="0" index="0" bw="0" slack="0"/>
<pin id="93" dir="0" index="1" bw="24" slack="0"/>
<pin id="94" dir="0" index="2" bw="24" slack="0"/>
<pin id="95" dir="1" index="3" bw="0" slack="2147483647"/>
</pin_list>
<bind>
<opcode="write(1151) " fcode="write"/>
<opset="StgValue_180/52 "/>
</bind>
</comp>

<comp id="98" class="1004" name="tmp_fu_98">
<pin_list>
<pin id="99" dir="0" index="0" bw="24" slack="0"/>
<pin id="100" dir="1" index="1" bw="40" slack="0"/>
</pin_list>
<bind>
<opcode="sext(35) " fcode="sext"/>
<opset="tmp/1 "/>
</bind>
</comp>

<comp id="102" class="1004" name="grp_fu_102">
<pin_list>
<pin id="103" dir="0" index="0" bw="40" slack="0"/>
<pin id="104" dir="0" index="1" bw="24" slack="0"/>
<pin id="105" dir="1" index="2" bw="40" slack="0"/>
</pin_list>
<bind>
<opcode="sdiv(15) " fcode="sdiv"/>
<opset="tmp_1/1 "/>
</bind>
</comp>

<comp id="108" class="1004" name="tmp_3_fu_108">
<pin_list>
<pin id="109" dir="0" index="0" bw="24" slack="0"/>
<pin id="110" dir="1" index="1" bw="48" slack="0"/>
</pin_list>
<bind>
<opcode="sext(35) " fcode="sext"/>
<opset="tmp_3/1 "/>
</bind>
</comp>

<comp id="112" class="1004" name="grp_fu_112">
<pin_list>
<pin id="113" dir="0" index="0" bw="48" slack="0"/>
<pin id="114" dir="0" index="1" bw="24" slack="0"/>
<pin id="115" dir="1" index="2" bw="24" slack="0"/>
</pin_list>
<bind>
<opcode="srem(18) " fcode="srem"/>
<opset="tmp_4/1 "/>
</bind>
</comp>

<comp id="118" class="1004" name="lhs_V_fu_118">
<pin_list>
<pin id="119" dir="0" index="0" bw="24" slack="1"/>
<pin id="120" dir="1" index="1" bw="56" slack="0"/>
</pin_list>
<bind>
<opcode="sext(35) " fcode="sext"/>
<opset="lhs_V/2 "/>
</bind>
</comp>

<comp id="121" class="1004" name="rhs_V_fu_121">
<pin_list>
<pin id="122" dir="0" index="0" bw="32" slack="1"/>
<pin id="123" dir="1" index="1" bw="56" slack="0"/>
</pin_list>
<bind>
<opcode="sext(35) " fcode="sext"/>
<opset="rhs_V/2 "/>
</bind>
</comp>

<comp id="124" class="1004" name="r_V_fu_124">
<pin_list>
<pin id="125" dir="0" index="0" bw="32" slack="0"/>
<pin id="126" dir="0" index="1" bw="24" slack="0"/>
<pin id="127" dir="1" index="2" bw="56" slack="0"/>
</pin_list>
<bind>
<opcode="mul(12) " fcode="mul"/>
<opset="r_V/2 "/>
</bind>
</comp>

<comp id="131" class="1004" name="lhs_V_1_fu_131">
<pin_list>
<pin id="132" dir="0" index="0" bw="32" slack="1"/>
<pin id="133" dir="1" index="1" bw="33" slack="0"/>
</pin_list>
<bind>
<opcode="sext(35) " fcode="sext"/>
<opset="lhs_V_1/2 "/>
</bind>
</comp>

<comp id="134" class="1004" name="rhs_V_1_fu_134">
<pin_list>
<pin id="135" dir="0" index="0" bw="24" slack="1"/>
<pin id="136" dir="1" index="1" bw="33" slack="0"/>
</pin_list>
<bind>
<opcode="sext(35) " fcode="sext"/>
<opset="rhs_V_1/2 "/>
</bind>
</comp>

<comp id="137" class="1004" name="r_V_1_fu_137">
<pin_list>
<pin id="138" dir="0" index="0" bw="32" slack="0"/>
<pin id="139" dir="0" index="1" bw="24" slack="0"/>
<pin id="140" dir="1" index="2" bw="33" slack="0"/>
</pin_list>
<bind>
<opcode="add(8) " fcode="add"/>
<opset="r_V_1/2 "/>
</bind>
</comp>

<comp id="144" class="1004" name="tmp_2_fu_144">
<pin_list>
<pin id="145" dir="0" index="0" bw="40" slack="0"/>
<pin id="146" dir="1" index="1" bw="48" slack="0"/>
</pin_list>
<bind>
<opcode="sext(35) " fcode="sext"/>
<opset="tmp_2/44 "/>
</bind>
</comp>

<comp id="149" class="1004" name="r_V_2_fu_149">
<pin_list>
<pin id="150" dir="0" index="0" bw="24" slack="0"/>
<pin id="151" dir="1" index="1" bw="24" slack="0"/>
</pin_list>
<bind>
<opcode="trunc(33) " fcode="trunc"/>
<opset="r_V_2/52 "/>
</bind>
</comp>

<comp id="154" class="1005" name="inD_V_read_reg_154">
<pin_list>
<pin id="155" dir="0" index="0" bw="48" slack="1"/>
<pin id="156" dir="1" index="1" bw="48" slack="1"/>
</pin_list>
<bind>
<opset="inD_V_read "/>
</bind>
</comp>

<comp id="159" class="1005" name="inC_V_read_reg_159">
<pin_list>
<pin id="160" dir="0" index="0" bw="40" slack="1"/>
<pin id="161" dir="1" index="1" bw="40" slack="1"/>
</pin_list>
<bind>
<opset="inC_V_read "/>
</bind>
</comp>

<comp id="164" class="1005" name="inB_V_read_reg_164">
<pin_list>
<pin id="165" dir="0" index="0" bw="32" slack="1"/>
<pin id="166" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="inB_V_read "/>
</bind>
</comp>

<comp id="170" class="1005" name="inA_V_read_reg_170">
<pin_list>
<pin id="171" dir="0" index="0" bw="24" slack="1"/>
<pin id="172" dir="1" index="1" bw="24" slack="1"/>
</pin_list>
<bind>
<opset="inA_V_read "/>
</bind>
</comp>

<comp id="176" class="1005" name="tmp_reg_176">
<pin_list>
<pin id="177" dir="0" index="0" bw="40" slack="1"/>
<pin id="178" dir="1" index="1" bw="40" slack="1"/>
</pin_list>
<bind>
<opset="tmp "/>
</bind>
</comp>

<comp id="181" class="1005" name="tmp_3_reg_181">
<pin_list>
<pin id="182" dir="0" index="0" bw="48" slack="1"/>
<pin id="183" dir="1" index="1" bw="48" slack="1"/>
</pin_list>
<bind>
<opset="tmp_3 "/>
</bind>
</comp>

</comp_list>

<net_list>
<net id="50"><net_src comp="16" pin="0"/><net_sink comp="46" pin=0"/></net>

<net id="51"><net_src comp="6" pin="0"/><net_sink comp="46" pin=1"/></net>

<net id="56"><net_src comp="18" pin="0"/><net_sink comp="52" pin=0"/></net>

<net id="57"><net_src comp="4" pin="0"/><net_sink comp="52" pin=1"/></net>

<net id="62"><net_src comp="20" pin="0"/><net_sink comp="58" pin=0"/></net>

<net id="63"><net_src comp="2" pin="0"/><net_sink comp="58" pin=1"/></net>

<net id="68"><net_src comp="22" pin="0"/><net_sink comp="64" pin=0"/></net>

<net id="69"><net_src comp="0" pin="0"/><net_sink comp="64" pin=1"/></net>

<net id="75"><net_src comp="24" pin="0"/><net_sink comp="70" pin=0"/></net>

<net id="76"><net_src comp="8" pin="0"/><net_sink comp="70" pin=1"/></net>

<net id="82"><net_src comp="26" pin="0"/><net_sink comp="77" pin=0"/></net>

<net id="83"><net_src comp="10" pin="0"/><net_sink comp="77" pin=1"/></net>

<net id="89"><net_src comp="28" pin="0"/><net_sink comp="84" pin=0"/></net>

<net id="90"><net_src comp="12" pin="0"/><net_sink comp="84" pin=1"/></net>

<net id="96"><net_src comp="44" pin="0"/><net_sink comp="91" pin=0"/></net>

<net id="97"><net_src comp="14" pin="0"/><net_sink comp="91" pin=1"/></net>

<net id="101"><net_src comp="64" pin="2"/><net_sink comp="98" pin=0"/></net>

<net id="106"><net_src comp="52" pin="2"/><net_sink comp="102" pin=0"/></net>

<net id="107"><net_src comp="98" pin="1"/><net_sink comp="102" pin=1"/></net>

<net id="111"><net_src comp="64" pin="2"/><net_sink comp="108" pin=0"/></net>

<net id="116"><net_src comp="46" pin="2"/><net_sink comp="112" pin=0"/></net>

<net id="117"><net_src comp="108" pin="1"/><net_sink comp="112" pin=1"/></net>

<net id="128"><net_src comp="121" pin="1"/><net_sink comp="124" pin=0"/></net>

<net id="129"><net_src comp="118" pin="1"/><net_sink comp="124" pin=1"/></net>

<net id="130"><net_src comp="124" pin="2"/><net_sink comp="70" pin=2"/></net>

<net id="141"><net_src comp="131" pin="1"/><net_sink comp="137" pin=0"/></net>

<net id="142"><net_src comp="134" pin="1"/><net_sink comp="137" pin=1"/></net>

<net id="143"><net_src comp="137" pin="2"/><net_sink comp="77" pin=2"/></net>

<net id="147"><net_src comp="102" pin="2"/><net_sink comp="144" pin=0"/></net>

<net id="148"><net_src comp="144" pin="1"/><net_sink comp="84" pin=2"/></net>

<net id="152"><net_src comp="112" pin="2"/><net_sink comp="149" pin=0"/></net>

<net id="153"><net_src comp="149" pin="1"/><net_sink comp="91" pin=2"/></net>

<net id="157"><net_src comp="46" pin="2"/><net_sink comp="154" pin=0"/></net>

<net id="158"><net_src comp="154" pin="1"/><net_sink comp="112" pin=0"/></net>

<net id="162"><net_src comp="52" pin="2"/><net_sink comp="159" pin=0"/></net>

<net id="163"><net_src comp="159" pin="1"/><net_sink comp="102" pin=0"/></net>

<net id="167"><net_src comp="58" pin="2"/><net_sink comp="164" pin=0"/></net>

<net id="168"><net_src comp="164" pin="1"/><net_sink comp="121" pin=0"/></net>

<net id="169"><net_src comp="164" pin="1"/><net_sink comp="131" pin=0"/></net>

<net id="173"><net_src comp="64" pin="2"/><net_sink comp="170" pin=0"/></net>

<net id="174"><net_src comp="170" pin="1"/><net_sink comp="118" pin=0"/></net>

<net id="175"><net_src comp="170" pin="1"/><net_sink comp="134" pin=0"/></net>

<net id="179"><net_src comp="98" pin="1"/><net_sink comp="176" pin=0"/></net>

<net id="180"><net_src comp="176" pin="1"/><net_sink comp="102" pin=1"/></net>

<net id="184"><net_src comp="108" pin="1"/><net_sink comp="181" pin=0"/></net>

<net id="185"><net_src comp="181" pin="1"/><net_sink comp="112" pin=1"/></net>

</net_list>

</model> 
---------------- Datapath Model END ------------------

* FSMD analyzer results:
  - Output states:
	Port: out1_V | {2 }
	Port: out2_V | {2 }
	Port: out3_V | {44 }
	Port: out4_V | {52 }
 - Input state : 
	Port: apint_arith : inA_V | {1 }
	Port: apint_arith : inB_V | {1 }
	Port: apint_arith : inC_V | {1 }
	Port: apint_arith : inD_V | {1 }
  - Chain level:
	State 1
		tmp_1 : 1
		tmp_4 : 1
	State 2
		r_V : 1
		StgValue_64 : 2
		r_V_1 : 1
		StgValue_68 : 2
	State 3
	State 4
	State 5
	State 6
	State 7
	State 8
	State 9
	State 10
	State 11
	State 12
	State 13
	State 14
	State 15
	State 16
	State 17
	State 18
	State 19
	State 20
	State 21
	State 22
	State 23
	State 24
	State 25
	State 26
	State 27
	State 28
	State 29
	State 30
	State 31
	State 32
	State 33
	State 34
	State 35
	State 36
	State 37
	State 38
	State 39
	State 40
	State 41
	State 42
	State 43
	State 44
		tmp_2 : 1
		StgValue_155 : 2
	State 45
	State 46
	State 47
	State 48
	State 49
	State 50
	State 51
	State 52
		r_V_2 : 1
		StgValue_180 : 2


============================================================
+ Verbose Summary: Datapath Resource usage 
============================================================

* Functional unit list:
|----------|--------------------------|---------|---------|---------|
| Operation|      Functional Unit     |  DSP48E |    FF   |   LUT   |
|----------|--------------------------|---------|---------|---------|
|   srem   |        grp_fu_112        |    0    |   587   |   354   |
|----------|--------------------------|---------|---------|---------|
|   sdiv   |        grp_fu_102        |    0    |   490   |   296   |
|----------|--------------------------|---------|---------|---------|
|    add   |       r_V_1_fu_137       |    0    |    0    |    39   |
|----------|--------------------------|---------|---------|---------|
|    mul   |        r_V_fu_124        |    3    |    0    |    20   |
|----------|--------------------------|---------|---------|---------|
|          |   inD_V_read_read_fu_46  |    0    |    0    |    0    |
|   read   |   inC_V_read_read_fu_52  |    0    |    0    |    0    |
|          |   inB_V_read_read_fu_58  |    0    |    0    |    0    |
|          |   inA_V_read_read_fu_64  |    0    |    0    |    0    |
|----------|--------------------------|---------|---------|---------|
|          |  StgValue_64_write_fu_70 |    0    |    0    |    0    |
|   write  |  StgValue_68_write_fu_77 |    0    |    0    |    0    |
|          | StgValue_155_write_fu_84 |    0    |    0    |    0    |
|          | StgValue_180_write_fu_91 |    0    |    0    |    0    |
|----------|--------------------------|---------|---------|---------|
|          |         tmp_fu_98        |    0    |    0    |    0    |
|          |       tmp_3_fu_108       |    0    |    0    |    0    |
|          |       lhs_V_fu_118       |    0    |    0    |    0    |
|   sext   |       rhs_V_fu_121       |    0    |    0    |    0    |
|          |      lhs_V_1_fu_131      |    0    |    0    |    0    |
|          |      rhs_V_1_fu_134      |    0    |    0    |    0    |
|          |       tmp_2_fu_144       |    0    |    0    |    0    |
|----------|--------------------------|---------|---------|---------|
|   trunc  |       r_V_2_fu_149       |    0    |    0    |    0    |
|----------|--------------------------|---------|---------|---------|
|   Total  |                          |    3    |   1077  |   709   |
|----------|--------------------------|---------|---------|---------|

Memories:
N/A

* Register list:
+------------------+--------+
|                  |   FF   |
+------------------+--------+
|inA_V_read_reg_170|   24   |
|inB_V_read_reg_164|   32   |
|inC_V_read_reg_159|   40   |
|inD_V_read_reg_154|   48   |
|   tmp_3_reg_181  |   48   |
|    tmp_reg_176   |   40   |
+------------------+--------+
|       Total      |   232  |
+------------------+--------+

* Multiplexer (MUX) list: 
|------------|------|------|------|--------||---------||---------|
|    Comp    |  Pin | Size |  BW  | S x BW ||  Delay  ||   LUT   |
|------------|------|------|------|--------||---------||---------|
| grp_fu_102 |  p0  |   2  |  40  |   80   ||    9    |
| grp_fu_102 |  p1  |   2  |  24  |   48   ||    9    |
| grp_fu_112 |  p0  |   2  |  48  |   96   ||    9    |
| grp_fu_112 |  p1  |   2  |  24  |   48   ||    9    |
|------------|------|------|------|--------||---------||---------|
|    Total   |      |      |      |   272  ||  7.076  ||    36   |
|------------|------|------|------|--------||---------||---------|



* Summary:
+-----------+--------+--------+--------+--------+
|           | DSP48E |  Delay |   FF   |   LUT  |
+-----------+--------+--------+--------+--------+
|  Function |    3   |    -   |  1077  |   709  |
|   Memory  |    -   |    -   |    -   |    -   |
|Multiplexer|    -   |    7   |    -   |   36   |
|  Register |    -   |    -   |   232  |    -   |
+-----------+--------+--------+--------+--------+
|   Total   |    3   |    7   |  1309  |   745  |
+-----------+--------+--------+--------+--------+