================================================================
== Vivado HLS Report for 'apint_arith'
================================================================
* Date:           Mon Mar  5 09:40:36 2018

* Version:        2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017)
* Project:        vivado_test
* Solution:       solution1
* Product family: zynq
* Target device:  xc7z020clg484-1


================================================================
== Performance Estimates
================================================================
+ Timing (ns): 
    * Summary: 
    +--------+-------+----------+------------+
    |  Clock | Target| Estimated| Uncertainty|
    +--------+-------+----------+------------+
    |ap_clk  |  10.00|      6.38|        1.25|
    +--------+-------+----------+------------+

+ Latency (clock cycles): 
    * Summary: 
    +-----+-----+-----+-----+---------+
    |  Latency  |  Interval | Pipeline|
    | min | max | min | max |   Type  |
    +-----+-----+-----+-----+---------+
    |   67|   67|   67|   67|   none  |
    +-----+-----+-----+-----+---------+

    + Detail: 
        * Instance: 
        N/A

        * Loop: 
        N/A

============================================================
+ Verbose Summary: Synthesis Manager
============================================================
InlineROM: 1
ExposeGlobal: 0
============================================================
+ Verbose Summary: CDFG Model
============================================================
IsTopModel: 1
ResetActiveHigh: 1
IsCombinational: 0
IsDatapathOnly: 0
HasWiredReturn: 1
HasMFsm: 0
HasVarLatency: 1
IsPipeline: 0
IsRtlPipelined: 0
IsInstanceOverlapped: 0
IsDontTouch: 0
HasImplIP: 0
IsGatedGlobalClock: 0


============================================================
+ Verbose Summary: Schedule
============================================================
* Number of FSM states : 68
* Pipeline : 0
* Dataflow Pipeline: 0

* FSM state transitions: 
1 --> 
	2  / true
2 --> 
	3  / true
3 --> 
	4  / true
4 --> 
	5  / true
5 --> 
	6  / true
6 --> 
	7  / true
7 --> 
	8  / true
8 --> 
	9  / true
9 --> 
	10  / true
10 --> 
	11  / true
11 --> 
	12  / true
12 --> 
	13  / true
13 --> 
	14  / true
14 --> 
	15  / true
15 --> 
	16  / true
16 --> 
	17  / true
17 --> 
	18  / true
18 --> 
	19  / true
19 --> 
	20  / true
20 --> 
	21  / true
21 --> 
	22  / true
22 --> 
	23  / true
23 --> 
	24  / true
24 --> 
	25  / true
25 --> 
	26  / true
26 --> 
	27  / true
27 --> 
	28  / true
28 --> 
	29  / true
29 --> 
	30  / true
30 --> 
	31  / true
31 --> 
	32  / true
32 --> 
	33  / true
33 --> 
	34  / true
34 --> 
	35  / true
35 --> 
	36  / true
36 --> 
	37  / true
37 --> 
	38  / true
38 --> 
	39  / true
39 --> 
	40  / true
40 --> 
	41  / true
41 --> 
	42  / true
42 --> 
	43  / true
43 --> 
	44  / true
44 --> 
	45  / true
45 --> 
	46  / true
46 --> 
	47  / true
47 --> 
	48  / true
48 --> 
	49  / true
49 --> 
	50  / true
50 --> 
	51  / true
51 --> 
	52  / true
52 --> 
	53  / true
53 --> 
	54  / true
54 --> 
	55  / true
55 --> 
	56  / true
56 --> 
	57  / true
57 --> 
	58  / true
58 --> 
	59  / true
59 --> 
	60  / true
60 --> 
	61  / true
61 --> 
	62  / true
62 --> 
	63  / true
63 --> 
	64  / true
64 --> 
	65  / true
65 --> 
	66  / true
66 --> 
	67  / true
67 --> 
	68  / true
68 --> 

* FSM state operations: 

 <State 1> : 5.07ns
ST_1 : Operation 69 [1/1] (0.00ns)   --->   "%inD_read = call i64 @_ssdm_op_Read.ap_auto.i64(i64 %inD) nounwind"
ST_1 : Operation 70 [1/1] (0.00ns)   --->   "%inA_read = call i8 @_ssdm_op_Read.ap_auto.i8(i8 %inA) nounwind"
ST_1 : Operation 71 [1/1] (0.00ns)   --->   "%tmp_5 = sext i8 %inA_read to i64" [vivado_test/prec_test.cpp:9]
ST_1 : Operation 72 [68/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 2> : 5.07ns
ST_2 : Operation 73 [67/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 3> : 5.07ns
ST_3 : Operation 74 [66/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 4> : 5.07ns
ST_4 : Operation 75 [65/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 5> : 5.07ns
ST_5 : Operation 76 [64/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 6> : 5.07ns
ST_6 : Operation 77 [63/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 7> : 5.07ns
ST_7 : Operation 78 [62/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 8> : 5.07ns
ST_8 : Operation 79 [61/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 9> : 5.07ns
ST_9 : Operation 80 [60/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 10> : 5.07ns
ST_10 : Operation 81 [59/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 11> : 5.07ns
ST_11 : Operation 82 [58/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 12> : 5.07ns
ST_12 : Operation 83 [57/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 13> : 5.07ns
ST_13 : Operation 84 [56/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 14> : 5.07ns
ST_14 : Operation 85 [55/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 15> : 5.07ns
ST_15 : Operation 86 [54/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 16> : 5.07ns
ST_16 : Operation 87 [53/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 17> : 5.07ns
ST_17 : Operation 88 [52/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 18> : 5.07ns
ST_18 : Operation 89 [51/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 19> : 5.07ns
ST_19 : Operation 90 [50/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 20> : 5.07ns
ST_20 : Operation 91 [49/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 21> : 5.07ns
ST_21 : Operation 92 [48/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 22> : 5.07ns
ST_22 : Operation 93 [47/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 23> : 5.07ns
ST_23 : Operation 94 [46/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 24> : 5.07ns
ST_24 : Operation 95 [45/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 25> : 5.07ns
ST_25 : Operation 96 [44/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 26> : 5.07ns
ST_26 : Operation 97 [43/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 27> : 5.07ns
ST_27 : Operation 98 [42/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 28> : 5.07ns
ST_28 : Operation 99 [41/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 29> : 5.07ns
ST_29 : Operation 100 [40/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 30> : 5.07ns
ST_30 : Operation 101 [39/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 31> : 5.07ns
ST_31 : Operation 102 [38/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 32> : 5.07ns
ST_32 : Operation 103 [37/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 33> : 5.07ns
ST_33 : Operation 104 [1/1] (0.00ns)   --->   "%inC_read = call i32 @_ssdm_op_Read.ap_auto.i32(i32 %inC) nounwind"
ST_33 : Operation 105 [1/1] (0.00ns)   --->   "%tmp = sext i8 %inA_read to i32" [vivado_test/prec_test.cpp:6]
ST_33 : Operation 106 [36/36] (4.13ns)   --->   "%tmp_4 = sdiv i32 %inC_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_33 : Operation 107 [36/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 34> : 5.07ns
ST_34 : Operation 108 [35/36] (4.13ns)   --->   "%tmp_4 = sdiv i32 %inC_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_34 : Operation 109 [35/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 35> : 5.07ns
ST_35 : Operation 110 [34/36] (4.13ns)   --->   "%tmp_4 = sdiv i32 %inC_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_35 : Operation 111 [34/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 36> : 5.07ns
ST_36 : Operation 112 [33/36] (4.13ns)   --->   "%tmp_4 = sdiv i32 %inC_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_36 : Operation 113 [33/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 37> : 5.07ns
ST_37 : Operation 114 [32/36] (4.13ns)   --->   "%tmp_4 = sdiv i32 %inC_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_37 : Operation 115 [32/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 38> : 5.07ns
ST_38 : Operation 116 [31/36] (4.13ns)   --->   "%tmp_4 = sdiv i32 %inC_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_38 : Operation 117 [31/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 39> : 5.07ns
ST_39 : Operation 118 [30/36] (4.13ns)   --->   "%tmp_4 = sdiv i32 %inC_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_39 : Operation 119 [30/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 40> : 5.07ns
ST_40 : Operation 120 [29/36] (4.13ns)   --->   "%tmp_4 = sdiv i32 %inC_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_40 : Operation 121 [29/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 41> : 5.07ns
ST_41 : Operation 122 [28/36] (4.13ns)   --->   "%tmp_4 = sdiv i32 %inC_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_41 : Operation 123 [28/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 42> : 5.07ns
ST_42 : Operation 124 [27/36] (4.13ns)   --->   "%tmp_4 = sdiv i32 %inC_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_42 : Operation 125 [27/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 43> : 5.07ns
ST_43 : Operation 126 [26/36] (4.13ns)   --->   "%tmp_4 = sdiv i32 %inC_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_43 : Operation 127 [26/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 44> : 5.07ns
ST_44 : Operation 128 [25/36] (4.13ns)   --->   "%tmp_4 = sdiv i32 %inC_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_44 : Operation 129 [25/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 45> : 5.07ns
ST_45 : Operation 130 [24/36] (4.13ns)   --->   "%tmp_4 = sdiv i32 %inC_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_45 : Operation 131 [24/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 46> : 5.07ns
ST_46 : Operation 132 [23/36] (4.13ns)   --->   "%tmp_4 = sdiv i32 %inC_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_46 : Operation 133 [23/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 47> : 5.07ns
ST_47 : Operation 134 [22/36] (4.13ns)   --->   "%tmp_4 = sdiv i32 %inC_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_47 : Operation 135 [22/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 48> : 5.07ns
ST_48 : Operation 136 [21/36] (4.13ns)   --->   "%tmp_4 = sdiv i32 %inC_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_48 : Operation 137 [21/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 49> : 5.07ns
ST_49 : Operation 138 [20/36] (4.13ns)   --->   "%tmp_4 = sdiv i32 %inC_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_49 : Operation 139 [20/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 50> : 5.07ns
ST_50 : Operation 140 [19/36] (4.13ns)   --->   "%tmp_4 = sdiv i32 %inC_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_50 : Operation 141 [19/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 51> : 5.07ns
ST_51 : Operation 142 [18/36] (4.13ns)   --->   "%tmp_4 = sdiv i32 %inC_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_51 : Operation 143 [18/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 52> : 5.07ns
ST_52 : Operation 144 [17/36] (4.13ns)   --->   "%tmp_4 = sdiv i32 %inC_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_52 : Operation 145 [17/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 53> : 5.07ns
ST_53 : Operation 146 [16/36] (4.13ns)   --->   "%tmp_4 = sdiv i32 %inC_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_53 : Operation 147 [16/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 54> : 5.07ns
ST_54 : Operation 148 [15/36] (4.13ns)   --->   "%tmp_4 = sdiv i32 %inC_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_54 : Operation 149 [15/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 55> : 5.07ns
ST_55 : Operation 150 [14/36] (4.13ns)   --->   "%tmp_4 = sdiv i32 %inC_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_55 : Operation 151 [14/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 56> : 5.07ns
ST_56 : Operation 152 [13/36] (4.13ns)   --->   "%tmp_4 = sdiv i32 %inC_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_56 : Operation 153 [13/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 57> : 5.07ns
ST_57 : Operation 154 [12/36] (4.13ns)   --->   "%tmp_4 = sdiv i32 %inC_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_57 : Operation 155 [12/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 58> : 5.07ns
ST_58 : Operation 156 [11/36] (4.13ns)   --->   "%tmp_4 = sdiv i32 %inC_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_58 : Operation 157 [11/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 59> : 5.07ns
ST_59 : Operation 158 [10/36] (4.13ns)   --->   "%tmp_4 = sdiv i32 %inC_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_59 : Operation 159 [10/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 60> : 5.07ns
ST_60 : Operation 160 [9/36] (4.13ns)   --->   "%tmp_4 = sdiv i32 %inC_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_60 : Operation 161 [9/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 61> : 5.07ns
ST_61 : Operation 162 [8/36] (4.13ns)   --->   "%tmp_4 = sdiv i32 %inC_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_61 : Operation 163 [8/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 62> : 5.07ns
ST_62 : Operation 164 [7/36] (4.13ns)   --->   "%tmp_4 = sdiv i32 %inC_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_62 : Operation 165 [7/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 63> : 5.07ns
ST_63 : Operation 166 [6/36] (4.13ns)   --->   "%tmp_4 = sdiv i32 %inC_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_63 : Operation 167 [6/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 64> : 5.07ns
ST_64 : Operation 168 [5/36] (4.13ns)   --->   "%tmp_4 = sdiv i32 %inC_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_64 : Operation 169 [5/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 65> : 5.07ns
ST_65 : Operation 170 [4/36] (4.13ns)   --->   "%tmp_4 = sdiv i32 %inC_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_65 : Operation 171 [4/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 66> : 5.07ns
ST_66 : Operation 172 [3/36] (4.13ns)   --->   "%tmp_4 = sdiv i32 %inC_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_66 : Operation 173 [3/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 67> : 5.07ns
ST_67 : Operation 174 [2/36] (4.13ns)   --->   "%tmp_4 = sdiv i32 %inC_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_67 : Operation 175 [2/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>

 <State 68> : 6.38ns
ST_68 : Operation 176 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecBitsMap(i8 %inA) nounwind, !map !7"
ST_68 : Operation 177 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecBitsMap(i16 %inB) nounwind, !map !13"
ST_68 : Operation 178 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecBitsMap(i32 %inC) nounwind, !map !17"
ST_68 : Operation 179 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecBitsMap(i64 %inD) nounwind, !map !21"
ST_68 : Operation 180 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecBitsMap(i32* %out1) nounwind, !map !25"
ST_68 : Operation 181 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecBitsMap(i32* %out2) nounwind, !map !31"
ST_68 : Operation 182 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecBitsMap(i32* %out3) nounwind, !map !35"
ST_68 : Operation 183 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecBitsMap(i64* %out4) nounwind, !map !39"
ST_68 : Operation 184 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecTopModule([12 x i8]* @apint_arith_str) nounwind"
ST_68 : Operation 185 [1/1] (0.00ns)   --->   "%inB_read = call i16 @_ssdm_op_Read.ap_auto.i16(i16 %inB) nounwind"
ST_68 : Operation 186 [1/1] (0.00ns)   --->   "%tmp_cast2 = sext i8 %inA_read to i17" [vivado_test/prec_test.cpp:6]
ST_68 : Operation 187 [1/1] (0.00ns)   --->   "%tmp_cast = sext i8 %inA_read to i24" [vivado_test/prec_test.cpp:6]
ST_68 : Operation 188 [1/1] (0.00ns)   --->   "%tmp_1_cast1 = sext i16 %inB_read to i17" [vivado_test/prec_test.cpp:6]
ST_68 : Operation 189 [1/1] (0.00ns)   --->   "%tmp_1_cast = sext i16 %inB_read to i24" [vivado_test/prec_test.cpp:6]
ST_68 : Operation 190 [1/1] (6.38ns)   --->   "%tmp_2 = mul i24 %tmp_1_cast, %tmp_cast" [vivado_test/prec_test.cpp:6]   --->   Core 61 'DSP48' <Latency = 0> <II = 1> <Delay = 6.38> <IPBlock> <Opcode : 'mul' 'add' 'sub' 'select'> <InPorts = 0> <OutPorts = 1> <Sync> <CReg>
ST_68 : Operation 191 [1/1] (0.00ns)   --->   "%tmp_2_cast = sext i24 %tmp_2 to i32" [vivado_test/prec_test.cpp:6]
ST_68 : Operation 192 [1/1] (0.00ns)   --->   "call void @_ssdm_op_Write.ap_auto.i32P(i32* %out1, i32 %tmp_2_cast) nounwind" [vivado_test/prec_test.cpp:6]
ST_68 : Operation 193 [1/1] (2.07ns)   --->   "%tmp_3 = add i17 %tmp_1_cast1, %tmp_cast2" [vivado_test/prec_test.cpp:7]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.07> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_68 : Operation 194 [1/1] (0.00ns)   --->   "%tmp_3_cast = sext i17 %tmp_3 to i32" [vivado_test/prec_test.cpp:7]
ST_68 : Operation 195 [1/1] (0.00ns)   --->   "call void @_ssdm_op_Write.ap_auto.i32P(i32* %out2, i32 %tmp_3_cast) nounwind" [vivado_test/prec_test.cpp:7]
ST_68 : Operation 196 [1/36] (4.13ns)   --->   "%tmp_4 = sdiv i32 %inC_read, %tmp" [vivado_test/prec_test.cpp:8]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_68 : Operation 197 [1/1] (0.00ns)   --->   "call void @_ssdm_op_Write.ap_auto.i32P(i32* %out3, i32 %tmp_4) nounwind" [vivado_test/prec_test.cpp:8]
ST_68 : Operation 198 [1/68] (5.07ns)   --->   "%tmp_6 = srem i64 %inD_read, %tmp_5" [vivado_test/prec_test.cpp:9]   --->   Core 24 'DivnS_SEQ' <Latency = 67> <II = 64> <Delay = 5.07> <FuncUnit> <Opcode : 'sdiv' 'srem' 'udiv' 'urem'> <InPorts = 2> <OutPorts = 1>
ST_68 : Operation 199 [1/1] (0.00ns)   --->   "call void @_ssdm_op_Write.ap_auto.i64P(i64* %out4, i64 %tmp_6) nounwind" [vivado_test/prec_test.cpp:9]
ST_68 : Operation 200 [1/1] (0.00ns)   --->   "ret void" [vivado_test/prec_test.cpp:10]


============================================================
+ Verbose Summary: Timing violations
============================================================
Target clock period: 10ns, clock uncertainty: 1.25ns.

 <State 1>: 5.07ns
The critical path consists of the following:
	wire read on port 'inD' [18]  (0 ns)
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 2>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 3>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 4>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 5>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 6>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 7>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 8>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 9>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 10>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 11>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 12>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 13>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 14>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 15>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 16>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 17>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 18>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 19>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 20>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 21>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 22>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 23>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 24>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 25>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 26>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 27>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 28>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 29>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 30>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 31>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 32>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 33>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 34>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 35>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 36>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 37>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 38>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 39>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 40>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 41>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 42>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 43>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 44>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 45>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 46>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 47>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 48>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 49>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 50>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 51>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 52>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 53>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 54>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 55>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 56>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 57>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 58>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 59>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 60>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 61>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 62>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 63>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 64>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 65>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 66>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 67>: 5.07ns
The critical path consists of the following:
	'srem' operation ('tmp_6', vivado_test/prec_test.cpp:9) [36]  (5.07 ns)

 <State 68>: 6.38ns
The critical path consists of the following:
	wire read on port 'inB' [20]  (0 ns)
	'mul' operation ('tmp_2', vivado_test/prec_test.cpp:6) [27]  (6.38 ns)


============================================================
+ Verbose Summary: Binding
============================================================
N/A
* FSMD analyzer results:
  - Output states:
 - Input state : 
  - Chain level:
	State 1
	State 2
	State 3
	State 4
	State 5
	State 6
	State 7
	State 8
	State 9
	State 10
	State 11
	State 12
	State 13
	State 14
	State 15
	State 16
	State 17
	State 18
	State 19
	State 20
	State 21
	State 22
	State 23
	State 24
	State 25
	State 26
	State 27
	State 28
	State 29
	State 30
	State 31
	State 32
	State 33
	State 34
	State 35
	State 36
	State 37
	State 38
	State 39
	State 40
	State 41
	State 42
	State 43
	State 44
	State 45
	State 46
	State 47
	State 48
	State 49
	State 50
	State 51
	State 52
	State 53
	State 54
	State 55
	State 56
	State 57
	State 58
	State 59
	State 60
	State 61
	State 62
	State 63
	State 64
	State 65
	State 66
	State 67
	State 68


============================================================
+ Verbose Summary: Datapath Resource usage 
============================================================
N/A