================================================================ == Vivado HLS Report for 'vector_mult' ================================================================ * Date: Mon Mar 19 10:58:26 2018 * Version: 2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017) * Project: vector_mult * Solution: solution4 * Product family: zynq * Target device: xc7z020clg484-1 ================================================================ == Performance Estimates ================================================================ + Timing (ns): * Summary: +--------+-------+----------+------------+ | Clock | Target| Estimated| Uncertainty| +--------+-------+----------+------------+ |ap_clk | 10.00| 8.75| 1.25| +--------+-------+----------+------------+ + Latency (clock cycles): * Summary: +-----+-----+-----+-----+---------+ | Latency | Interval | Pipeline| | min | max | min | max | Type | +-----+-----+-----+-----+---------+ | 36| 36| 36| 36| none | +-----+-----+-----+-----+---------+ + Detail: * Instance: N/A * Loop: +--------------------------------+-----+-----+----------+-----------+-----------+------+----------+ | | Latency | Iteration| Initiation Interval | Trip | | | Loop Name | min | max | Latency | achieved | target | Count| Pipelined| +--------------------------------+-----+-----+----------+-----------+-----------+------+----------+ |- memcpy.tempA.A | 3| 3| 3| 1| 1| 2| yes | |- memcpy.tempB.B | 3| 3| 3| 1| 1| 2| yes | |- vector_mult_loop | 3| 3| 3| 1| 1| 2| yes | |- memcpy.result.tempResult.gep | 2| 2| 2| 1| 1| 2| yes | +--------------------------------+-----+-----+----------+-----------+-----------+------+----------+ ================================================================ == Utilization Estimates ================================================================ * Summary: +-----------------+---------+-------+--------+-------+ | Name | BRAM_18K| DSP48E| FF | LUT | +-----------------+---------+-------+--------+-------+ |DSP | -| -| -| -| |Expression | -| 12| 0| 1747| |FIFO | -| -| -| -| |Instance | 8| -| 763| 1271| |Memory | -| -| -| -| |Multiplexer | -| -| -| 317| |Register | -| -| 1753| -| +-----------------+---------+-------+--------+-------+ |Total | 8| 12| 2516| 3335| +-----------------+---------+-------+--------+-------+ |Available | 280| 220| 106400| 53200| +-----------------+---------+-------+--------+-------+ |Utilization (%) | 2| 5| 2| 6| +-----------------+---------+-------+--------+-------+ + Detail: * Instance: +------------------------------+----------------------------+---------+-------+-----+-----+ | Instance | Module | BRAM_18K| DSP48E| FF | LUT | +------------------------------+----------------------------+---------+-------+-----+-----+ |vector_mult_AXILiteS_s_axi_U |vector_mult_AXILiteS_s_axi | 0| 0| 150| 232| |vector_mult_gmem_m_axi_U |vector_mult_gmem_m_axi | 8| 0| 613| 787| |vector_mult_mux_4bkb_U1 |vector_mult_mux_4bkb | 0| 0| 0| 21| |vector_mult_mux_4bkb_U2 |vector_mult_mux_4bkb | 0| 0| 0| 21| |vector_mult_mux_4bkb_U3 |vector_mult_mux_4bkb | 0| 0| 0| 21| |vector_mult_mux_4bkb_U4 |vector_mult_mux_4bkb | 0| 0| 0| 21| |vector_mult_mux_4bkb_U5 |vector_mult_mux_4bkb | 0| 0| 0| 21| |vector_mult_mux_4bkb_U6 |vector_mult_mux_4bkb | 0| 0| 0| 21| |vector_mult_mux_4bkb_U7 |vector_mult_mux_4bkb | 0| 0| 0| 21| |vector_mult_mux_4bkb_U8 |vector_mult_mux_4bkb | 0| 0| 0| 21| |vector_mult_mux_4bkb_U9 |vector_mult_mux_4bkb | 0| 0| 0| 21| |vector_mult_mux_4bkb_U10 |vector_mult_mux_4bkb | 0| 0| 0| 21| |vector_mult_mux_4bkb_U11 |vector_mult_mux_4bkb | 0| 0| 0| 21| |vector_mult_mux_4bkb_U12 |vector_mult_mux_4bkb | 0| 0| 0| 21| +------------------------------+----------------------------+---------+-------+-----+-----+ |Total | | 8| 0| 763| 1271| +------------------------------+----------------------------+---------+-------+-----+-----+ * DSP48: N/A * Memory: N/A * FIFO: N/A * Expression: +-----------------------------------+----------+-------+---+----+------------+------------+ | Variable Name | Operation| DSP48E| FF| LUT| Bitwidth P0| Bitwidth P1| +-----------------------------------+----------+-------+---+----+------------+------------+ |tempResult_0_1_fu_1092_p2 | * | 3| 0| 20| 32| 32| |tempResult_0_3_11_fu_1084_p2 | * | 3| 0| 20| 32| 32| |tempResult_1_1_fu_1096_p2 | * | 3| 0| 20| 32| 32| |tempResult_1_3_11_fu_1088_p2 | * | 3| 0| 20| 32| 32| |i_1_3_fu_1078_p2 | + | 0| 0| 13| 4| 3| |indvar_next1_3_fu_1272_p2 | + | 0| 0| 13| 4| 3| |indvar_next8_3_fu_775_p2 | + | 0| 0| 13| 3| 4| |indvar_next_3_fu_596_p2 | + | 0| 0| 13| 3| 4| |ap_block_pp0_stage0_11001 | and | 0| 0| 8| 1| 1| |ap_block_pp1_stage0_11001 | and | 0| 0| 8| 1| 1| |ap_block_pp3_stage0_11001 | and | 0| 0| 8| 1| 1| |ap_block_state10_pp0_stage0_iter1 | and | 0| 0| 8| 1| 1| |ap_block_state20_pp1_stage0_iter1 | and | 0| 0| 8| 1| 1| |ap_block_state28_io | and | 0| 0| 8| 1| 1| |ap_condition_1337 | and | 0| 0| 8| 1| 1| |cond1_fu_904_p2 | icmp | 0| 0| 8| 2| 1| |cond2_fu_1044_p2 | icmp | 0| 0| 8| 2| 1| |cond_fu_725_p2 | icmp | 0| 0| 8| 2| 1| |exitcond1_fu_580_p2 | icmp | 0| 0| 11| 4| 5| |exitcond2_fu_1208_p2 | icmp | 0| 0| 11| 4| 5| |exitcond9_fu_759_p2 | icmp | 0| 0| 11| 4| 5| |exitcond_fu_938_p2 | icmp | 0| 0| 11| 4| 5| |sel_tmp1_fu_1100_p2 | icmp | 0| 0| 9| 2| 3| |sel_tmp2_fu_648_p2 | icmp | 0| 0| 8| 2| 1| |sel_tmp3_fu_1112_p2 | icmp | 0| 0| 8| 2| 1| |sel_tmp6_fu_815_p2 | icmp | 0| 0| 9| 2| 3| |sel_tmp8_fu_827_p2 | icmp | 0| 0| 8| 2| 1| |sel_tmp_fu_636_p2 | icmp | 0| 0| 9| 2| 3| |newIndex116_t_fu_1010_p2 | or | 0| 0| 8| 2| 1| |newIndex16_t_fu_1252_p2 | or | 0| 0| 8| 2| 1| |newIndex56_t_fu_899_p2 | or | 0| 0| 8| 2| 1| |newIndex96_t_fu_720_p2 | or | 0| 0| 8| 2| 1| |tempA_0_3_10_fu_738_p3 | select | 0| 0| 32| 1| 32| |tempA_0_3_1_fu_653_p3 | select | 0| 0| 32| 1| 32| |tempA_0_3_2_fu_731_p3 | select | 0| 0| 32| 1| 32| |tempA_0_3_4_fu_641_p3 | select | 0| 0| 32| 1| 32| |tempA_0_3_5_fu_661_p3 | select | 0| 0| 32| 1| 32| |tempA_0_3_6_fu_668_p3 | select | 0| 0| 32| 1| 32| |tempA_0_3_8_fu_676_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_10_fu_752_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_1_fu_690_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_2_fu_745_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_4_fu_683_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_5_fu_698_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_6_fu_705_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_8_fu_713_p3 | select | 0| 0| 32| 1| 32| |tempB_0_3_10_fu_917_p3 | select | 0| 0| 32| 1| 32| |tempB_0_3_1_fu_832_p3 | select | 0| 0| 32| 1| 32| |tempB_0_3_2_fu_910_p3 | select | 0| 0| 32| 1| 32| |tempB_0_3_4_fu_820_p3 | select | 0| 0| 32| 1| 32| |tempB_0_3_5_fu_840_p3 | select | 0| 0| 32| 1| 32| |tempB_0_3_6_fu_847_p3 | select | 0| 0| 32| 1| 32| |tempB_0_3_8_fu_855_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_10_fu_931_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_1_fu_869_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_2_fu_924_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_4_fu_862_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_5_fu_877_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_6_fu_884_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_8_fu_892_p3 | select | 0| 0| 32| 1| 32| |tempResult_0_3_10_fu_1190_p3 | select | 0| 0| 32| 1| 32| |tempResult_0_3_1_fu_1117_p3 | select | 0| 0| 32| 1| 32| |tempResult_0_3_2_fu_1184_p3 | select | 0| 0| 32| 1| 32| |tempResult_0_3_4_fu_1105_p3 | select | 0| 0| 32| 1| 32| |tempResult_0_3_5_fu_1125_p3 | select | 0| 0| 32| 1| 32| |tempResult_0_3_6_fu_1132_p3 | select | 0| 0| 32| 1| 32| |tempResult_0_3_8_fu_1140_p3 | select | 0| 0| 32| 1| 32| |tempResult_1_3_10_fu_1202_p3 | select | 0| 0| 32| 1| 32| |tempResult_1_3_1_fu_1154_p3 | select | 0| 0| 32| 1| 32| |tempResult_1_3_2_fu_1196_p3 | select | 0| 0| 32| 1| 32| |tempResult_1_3_4_fu_1147_p3 | select | 0| 0| 32| 1| 32| |tempResult_1_3_5_fu_1162_p3 | select | 0| 0| 32| 1| 32| |tempResult_1_3_6_fu_1169_p3 | select | 0| 0| 32| 1| 32| |tempResult_1_3_8_fu_1177_p3 | select | 0| 0| 32| 1| 32| |ap_enable_pp0 | xor | 0| 0| 8| 1| 2| |ap_enable_pp1 | xor | 0| 0| 8| 1| 2| |ap_enable_pp2 | xor | 0| 0| 8| 1| 2| |ap_enable_pp3 | xor | 0| 0| 8| 1| 2| |ap_enable_reg_pp0_iter1 | xor | 0| 0| 8| 2| 1| |ap_enable_reg_pp1_iter1 | xor | 0| 0| 8| 2| 1| |ap_enable_reg_pp2_iter1 | xor | 0| 0| 8| 2| 1| |ap_enable_reg_pp3_iter1 | xor | 0| 0| 8| 2| 1| +-----------------------------------+----------+-------+---+----+------------+------------+ |Total | | 12| 0|1747| 245| 1544| +-----------------------------------+----------+-------+---+----+------------+------------+ * Multiplexer: +-----------------------------+-----+-----------+-----+-----------+ | Name | LUT | Input Size| Bits| Total Bits| +-----------------------------+-----+-----------+-----+-----------+ |ap_NS_fsm | 125| 27| 1| 27| |ap_enable_reg_pp0_iter1 | 9| 2| 1| 2| |ap_enable_reg_pp0_iter2 | 9| 2| 1| 2| |ap_enable_reg_pp1_iter1 | 9| 2| 1| 2| |ap_enable_reg_pp1_iter2 | 9| 2| 1| 2| |ap_enable_reg_pp2_iter1 | 9| 2| 1| 2| |ap_enable_reg_pp2_iter2 | 9| 2| 1| 2| |ap_enable_reg_pp3_iter1 | 15| 3| 1| 3| |ap_sig_ioackin_gmem_ARREADY | 9| 2| 1| 2| |ap_sig_ioackin_gmem_AWREADY | 9| 2| 1| 2| |ap_sig_ioackin_gmem_WREADY | 9| 2| 1| 2| |gmem_ARADDR | 15| 3| 32| 96| |gmem_blk_n_AR | 9| 2| 1| 2| |gmem_blk_n_AW | 9| 2| 1| 2| |gmem_blk_n_B | 9| 2| 1| 2| |gmem_blk_n_R | 9| 2| 1| 2| |gmem_blk_n_W | 9| 2| 1| 2| |i_reg_500 | 9| 2| 4| 8| |indvar1_reg_511 | 9| 2| 4| 8| |indvar7_reg_393 | 9| 2| 4| 8| |indvar_reg_286 | 9| 2| 4| 8| +-----------------------------+-----+-----------+-----+-----------+ |Total | 317| 69| 64| 186| +-----------------------------+-----+-----------+-----+-----------+ * Register: +-----------------------------------------+----+----+-----+-----------+ | Name | FF | LUT| Bits| Const Bits| +-----------------------------------------+----+----+-----+-----------+ |A1_reg_1311 | 28| 0| 28| 0| |B3_reg_1306 | 28| 0| 28| 0| |ap_CS_fsm | 26| 0| 26| 0| |ap_enable_reg_pp0_iter0 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter1 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter2 | 1| 0| 1| 0| |ap_enable_reg_pp1_iter0 | 1| 0| 1| 0| |ap_enable_reg_pp1_iter1 | 1| 0| 1| 0| |ap_enable_reg_pp1_iter2 | 1| 0| 1| 0| |ap_enable_reg_pp2_iter0 | 1| 0| 1| 0| |ap_enable_reg_pp2_iter1 | 1| 0| 1| 0| |ap_enable_reg_pp2_iter2 | 1| 0| 1| 0| |ap_enable_reg_pp3_iter0 | 1| 0| 1| 0| |ap_enable_reg_pp3_iter1 | 1| 0| 1| 0| |ap_reg_ioackin_gmem_ARREADY | 1| 0| 1| 0| |ap_reg_ioackin_gmem_AWREADY | 1| 0| 1| 0| |ap_reg_ioackin_gmem_WREADY | 1| 0| 1| 0| |ap_reg_pp0_iter1_exitcond1_reg_1334 | 1| 0| 1| 0| |ap_reg_pp0_iter1_newIndex106_t_reg_1338 | 2| 0| 2| 0| |ap_reg_pp1_iter1_exitcond9_reg_1416 | 1| 0| 1| 0| |ap_reg_pp1_iter1_newIndex66_t_reg_1420 | 2| 0| 2| 0| |ap_reg_pp2_iter1_cond2_reg_1538 | 1| 0| 1| 0| |ap_reg_pp2_iter1_exitcond_reg_1498 | 1| 0| 1| 0| |ap_reg_pp2_iter1_newIndex126_t_reg_1502 | 2| 0| 2| 0| |cond2_reg_1538 | 1| 0| 1| 0| |exitcond1_reg_1334 | 1| 0| 1| 0| |exitcond2_reg_1627 | 1| 0| 1| 0| |exitcond9_reg_1416 | 1| 0| 1| 0| |exitcond_reg_1498 | 1| 0| 1| 0| |gmem_addr_1_reg_1328 | 28| 0| 32| 4| |gmem_addr_reg_1322 | 28| 0| 32| 4| |i_reg_500 | 4| 0| 4| 0| |indvar1_reg_511 | 4| 0| 4| 0| |indvar7_reg_393 | 4| 0| 4| 0| |indvar_reg_286 | 4| 0| 4| 0| |newIndex106_t_reg_1338 | 2| 0| 2| 0| |newIndex126_t_reg_1502 | 2| 0| 2| 0| |newIndex66_t_reg_1420 | 2| 0| 2| 0| |result5_reg_1301 | 28| 0| 28| 0| |tempA_0_1_reg_1364 | 32| 0| 32| 0| |tempA_0_1_s_reg_262 | 32| 0| 32| 0| |tempA_0_2_s_reg_250 | 32| 0| 32| 0| |tempA_0_3_11_reg_1350 | 32| 0| 32| 0| |tempA_0_3_7_reg_274 | 32| 0| 32| 0| |tempA_0_3_reg_238 | 32| 0| 32| 0| |tempA_1_1_reg_1370 | 32| 0| 32| 0| |tempA_1_1_s_reg_214 | 32| 0| 32| 0| |tempA_1_2_s_reg_202 | 32| 0| 32| 0| |tempA_1_3_11_reg_1357 | 32| 0| 32| 0| |tempA_1_3_7_reg_226 | 32| 0| 32| 0| |tempA_1_3_reg_190 | 32| 0| 32| 0| |tempB_0_1_reg_1446 | 32| 0| 32| 0| |tempB_0_1_s_reg_369 | 32| 0| 32| 0| |tempB_0_2_s_reg_357 | 32| 0| 32| 0| |tempB_0_3_11_reg_1432 | 32| 0| 32| 0| |tempB_0_3_7_reg_381 | 32| 0| 32| 0| |tempB_0_3_reg_345 | 32| 0| 32| 0| |tempB_1_1_reg_1452 | 32| 0| 32| 0| |tempB_1_1_s_reg_321 | 32| 0| 32| 0| |tempB_1_2_s_reg_309 | 32| 0| 32| 0| |tempB_1_3_11_reg_1439 | 32| 0| 32| 0| |tempB_1_3_7_reg_333 | 32| 0| 32| 0| |tempB_1_3_reg_297 | 32| 0| 32| 0| |tempResult_0_1_reg_1575 | 32| 0| 32| 0| |tempResult_0_1_s_reg_476 | 32| 0| 32| 0| |tempResult_0_2_s_reg_464 | 32| 0| 32| 0| |tempResult_0_3_11_reg_1561 | 32| 0| 32| 0| |tempResult_0_3_7_reg_488 | 32| 0| 32| 0| |tempResult_0_3_reg_452 | 32| 0| 32| 0| |tempResult_1_1_reg_1581 | 32| 0| 32| 0| |tempResult_1_1_s_reg_428 | 32| 0| 32| 0| |tempResult_1_2_s_reg_416 | 32| 0| 32| 0| |tempResult_1_3_11_reg_1568 | 32| 0| 32| 0| |tempResult_1_3_7_reg_440 | 32| 0| 32| 0| |tempResult_1_3_reg_404 | 32| 0| 32| 0| |tmp_10_reg_1551 | 32| 0| 32| 0| |tmp_12_reg_1631 | 32| 0| 32| 0| |tmp_13_reg_1636 | 32| 0| 32| 0| |tmp_14_reg_1641 | 32| 0| 32| 0| |tmp_15_reg_1651 | 32| 0| 32| 0| |tmp_3_reg_1513 | 32| 0| 32| 0| |tmp_4_reg_1518 | 32| 0| 32| 0| |tmp_5_reg_1533 | 32| 0| 32| 0| |tmp_6_reg_1546 | 32| 0| 32| 0| |tmp_7_reg_1523 | 32| 0| 32| 0| |tmp_9_reg_1528 | 32| 0| 32| 0| |tmp_reg_1508 | 32| 0| 32| 0| +-----------------------------------------+----+----+-----+-----------+ |Total |1753| 0| 1761| 8| +-----------------------------------------+----+----+-----+-----------+ ================================================================ == Interface ================================================================ * Summary: +------------------------+-----+-----+------------+--------------+--------------+ | RTL Ports | Dir | Bits| Protocol | Source Object| C Type | +------------------------+-----+-----+------------+--------------+--------------+ |s_axi_AXILiteS_AWVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_AWREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_AWADDR | in | 6| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WDATA | in | 32| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WSTRB | in | 4| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARADDR | in | 6| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RVALID | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RREADY | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RDATA | out | 32| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RRESP | out | 2| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BVALID | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BREADY | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BRESP | out | 2| s_axi | AXILiteS | scalar | |ap_clk | in | 1| ap_ctrl_hs | vector_mult | return value | |ap_rst_n | in | 1| ap_ctrl_hs | vector_mult | return value | |interrupt | out | 1| ap_ctrl_hs | vector_mult | return value | |m_axi_gmem_AWVALID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_AWREADY | in | 1| m_axi | gmem | pointer | |m_axi_gmem_AWADDR | out | 32| m_axi | gmem | pointer | |m_axi_gmem_AWID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_AWLEN | out | 8| m_axi | gmem | pointer | |m_axi_gmem_AWSIZE | out | 3| m_axi | gmem | pointer | |m_axi_gmem_AWBURST | out | 2| m_axi | gmem | pointer | |m_axi_gmem_AWLOCK | out | 2| m_axi | gmem | pointer | |m_axi_gmem_AWCACHE | out | 4| m_axi | gmem | pointer | |m_axi_gmem_AWPROT | out | 3| m_axi | gmem | pointer | |m_axi_gmem_AWQOS | out | 4| m_axi | gmem | pointer | |m_axi_gmem_AWREGION | out | 4| m_axi | gmem | pointer | |m_axi_gmem_AWUSER | out | 1| m_axi | gmem | pointer | |m_axi_gmem_WVALID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_WREADY | in | 1| m_axi | gmem | pointer | |m_axi_gmem_WDATA | out | 128| m_axi | gmem | pointer | |m_axi_gmem_WSTRB | out | 16| m_axi | gmem | pointer | |m_axi_gmem_WLAST | out | 1| m_axi | gmem | pointer | |m_axi_gmem_WID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_WUSER | out | 1| m_axi | gmem | pointer | |m_axi_gmem_ARVALID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_ARREADY | in | 1| m_axi | gmem | pointer | |m_axi_gmem_ARADDR | out | 32| m_axi | gmem | pointer | |m_axi_gmem_ARID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_ARLEN | out | 8| m_axi | gmem | pointer | |m_axi_gmem_ARSIZE | out | 3| m_axi | gmem | pointer | |m_axi_gmem_ARBURST | out | 2| m_axi | gmem | pointer | |m_axi_gmem_ARLOCK | out | 2| m_axi | gmem | pointer | |m_axi_gmem_ARCACHE | out | 4| m_axi | gmem | pointer | |m_axi_gmem_ARPROT | out | 3| m_axi | gmem | pointer | |m_axi_gmem_ARQOS | out | 4| m_axi | gmem | pointer | |m_axi_gmem_ARREGION | out | 4| m_axi | gmem | pointer | |m_axi_gmem_ARUSER | out | 1| m_axi | gmem | pointer | |m_axi_gmem_RVALID | in | 1| m_axi | gmem | pointer | |m_axi_gmem_RREADY | out | 1| m_axi | gmem | pointer | |m_axi_gmem_RDATA | in | 128| m_axi | gmem | pointer | |m_axi_gmem_RLAST | in | 1| m_axi | gmem | pointer | |m_axi_gmem_RID | in | 1| m_axi | gmem | pointer | |m_axi_gmem_RUSER | in | 1| m_axi | gmem | pointer | |m_axi_gmem_RRESP | in | 2| m_axi | gmem | pointer | |m_axi_gmem_BVALID | in | 1| m_axi | gmem | pointer | |m_axi_gmem_BREADY | out | 1| m_axi | gmem | pointer | |m_axi_gmem_BRESP | in | 2| m_axi | gmem | pointer | |m_axi_gmem_BID | in | 1| m_axi | gmem | pointer | |m_axi_gmem_BUSER | in | 1| m_axi | gmem | pointer | +------------------------+-----+-----+------------+--------------+--------------+