================================================================ == Vivado HLS Report for 'vector_mult' ================================================================ * Date: Mon Mar 19 10:58:25 2018 * Version: 2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017) * Project: vector_mult * Solution: solution4 * Product family: zynq * Target device: xc7z020clg484-1 ================================================================ == Performance Estimates ================================================================ + Timing (ns): * Summary: +--------+-------+----------+------------+ | Clock | Target| Estimated| Uncertainty| +--------+-------+----------+------------+ |ap_clk | 10.00| 8.75| 1.25| +--------+-------+----------+------------+ + Latency (clock cycles): * Summary: +-----+-----+-----+-----+---------+ | Latency | Interval | Pipeline| | min | max | min | max | Type | +-----+-----+-----+-----+---------+ | 36| 36| 36| 36| none | +-----+-----+-----+-----+---------+ + Detail: * Instance: N/A * Loop: +--------------------------------+-----+-----+----------+-----------+-----------+------+----------+ | | Latency | Iteration| Initiation Interval | Trip | | | Loop Name | min | max | Latency | achieved | target | Count| Pipelined| +--------------------------------+-----+-----+----------+-----------+-----------+------+----------+ |- memcpy.tempA.A | 3| 3| 3| 1| 1| 2| yes | |- memcpy.tempB.B | 3| 3| 3| 1| 1| 2| yes | |- vector_mult_loop | 3| 3| 3| 1| 1| 2| yes | |- memcpy.result.tempResult.gep | 2| 2| 2| 1| 1| 2| yes | +--------------------------------+-----+-----+----------+-----------+-----------+------+----------+ ============================================================ + Verbose Summary: Synthesis Manager ============================================================ InlineROM: 1 ExposeGlobal: 0 ============================================================ + Verbose Summary: CDFG Model ============================================================ IsTopModel: 1 ResetActiveHigh: 1 IsCombinational: 0 IsDatapathOnly: 0 HasWiredReturn: 1 HasMFsm: 0 HasVarLatency: 1 IsPipeline: 0 IsRtlPipelined: 0 IsInstanceOverlapped: 0 IsDontTouch: 0 HasImplIP: 0 IsGatedGlobalClock: 0 + Individual pipeline summary: * Pipeline-0: initiation interval (II) = 1, depth = 3 * Pipeline-1: initiation interval (II) = 1, depth = 3 * Pipeline-2: initiation interval (II) = 1, depth = 3 * Pipeline-3: initiation interval (II) = 1, depth = 2 ============================================================ + Verbose Summary: Schedule ============================================================ * Number of FSM states : 33 * Pipeline : 4 Pipeline-0 : II = 1, D = 3, States = { 9 10 11 } Pipeline-1 : II = 1, D = 3, States = { 19 20 21 } Pipeline-2 : II = 1, D = 3, States = { 23 24 25 } Pipeline-3 : II = 1, D = 2, States = { 27 28 } * Dataflow Pipeline: 0 * FSM state transitions: 1 --> 2 / true 2 --> 3 / true 3 --> 4 / true 4 --> 5 / true 5 --> 6 / true 6 --> 7 / true 7 --> 8 / true 8 --> 9 / true 9 --> 12 / (exitcond1) 10 / (!exitcond1) 10 --> 11 / true 11 --> 9 / true 12 --> 13 / true 13 --> 14 / true 14 --> 15 / true 15 --> 16 / true 16 --> 17 / true 17 --> 18 / true 18 --> 19 / true 19 --> 22 / (exitcond9) 20 / (!exitcond9) 20 --> 21 / true 21 --> 19 / true 22 --> 23 / true 23 --> 26 / (exitcond) 24 / (!exitcond) 24 --> 25 / true 25 --> 23 / true 26 --> 27 / true 27 --> 29 / (exitcond2) 28 / (!exitcond2) 28 --> 27 / true 29 --> 30 / true 30 --> 31 / true 31 --> 32 / true 32 --> 33 / true 33 --> * FSM state operations: : 1.00ns ST_1 : Operation 34 [1/1] (1.00ns) ---> "%result_read = call i32 @_ssdm_op_Read.s_axilite.i32(i32 %result)" ---> Core 10 's_axilite' ST_1 : Operation 35 [1/1] (1.00ns) ---> "%B_read = call i32 @_ssdm_op_Read.s_axilite.i32(i32 %B)" ---> Core 10 's_axilite' ST_1 : Operation 36 [1/1] (1.00ns) ---> "%A_read = call i32 @_ssdm_op_Read.s_axilite.i32(i32 %A)" ---> Core 10 's_axilite' ST_1 : Operation 37 [1/1] (0.00ns) ---> "%result5 = call i28 @_ssdm_op_PartSelect.i28.i32.i32.i32(i32 %result_read, i32 4, i32 31)" ST_1 : Operation 38 [1/1] (0.00ns) ---> "%B3 = call i28 @_ssdm_op_PartSelect.i28.i32.i32.i32(i32 %B_read, i32 4, i32 31)" ST_1 : Operation 39 [1/1] (0.00ns) ---> "%A1 = call i28 @_ssdm_op_PartSelect.i28.i32.i32.i32(i32 %A_read, i32 4, i32 31)" : 8.75ns ST_2 : Operation 40 [1/1] (0.00ns) ---> "%tmp_2 = zext i28 %A1 to i64" ST_2 : Operation 41 [1/1] (0.00ns) ---> "%gmem_addr_2 = getelementptr i128* %gmem, i64 %tmp_2" ST_2 : Operation 42 [7/7] (8.75ns) ---> "%gmem_addr_2_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i128P(i128* %gmem_addr_2, i32 2)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' : 8.75ns ST_3 : Operation 43 [6/7] (8.75ns) ---> "%gmem_addr_2_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i128P(i128* %gmem_addr_2, i32 2)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' : 8.75ns ST_4 : Operation 44 [5/7] (8.75ns) ---> "%gmem_addr_2_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i128P(i128* %gmem_addr_2, i32 2)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' : 8.75ns ST_5 : Operation 45 [4/7] (8.75ns) ---> "%gmem_addr_2_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i128P(i128* %gmem_addr_2, i32 2)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' : 8.75ns ST_6 : Operation 46 [3/7] (8.75ns) ---> "%gmem_addr_2_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i128P(i128* %gmem_addr_2, i32 2)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' : 8.75ns ST_7 : Operation 47 [2/7] (8.75ns) ---> "%gmem_addr_2_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i128P(i128* %gmem_addr_2, i32 2)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' : 8.75ns ST_8 : Operation 48 [1/1] (0.00ns) ---> "%tmp_s = zext i28 %result5 to i64" ST_8 : Operation 49 [1/1] (0.00ns) ---> "%gmem_addr = getelementptr i128* %gmem, i64 %tmp_s" ST_8 : Operation 50 [1/1] (0.00ns) ---> "%tmp_1 = zext i28 %B3 to i64" ST_8 : Operation 51 [1/1] (0.00ns) ---> "%gmem_addr_1 = getelementptr i128* %gmem, i64 %tmp_1" ST_8 : Operation 52 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecBitsMap(i128* %gmem), !map !11" ST_8 : Operation 53 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecTopModule([12 x i8]* @vector_mult_str) nounwind" ST_8 : Operation 54 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32 0, [10 x i8]* @p_str2, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1, [1 x i8]* @p_str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1) nounwind" [vector_mult/vector_mult.cpp:5] ST_8 : Operation 55 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32 %result, [10 x i8]* @mode5, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @bundle6, [6 x i8]* @p_str4, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)" ST_8 : Operation 56 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32 %B, [10 x i8]* @mode3, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @bundle4, [6 x i8]* @p_str4, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)" ST_8 : Operation 57 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i128* %gmem, [6 x i8]* @p_str3, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @p_str1, [6 x i8]* @p_str4, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)" ST_8 : Operation 58 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32 %A, [10 x i8]* @mode, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @bundle, [6 x i8]* @p_str4, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)" ST_8 : Operation 59 [1/7] (8.75ns) ---> "%gmem_addr_2_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i128P(i128* %gmem_addr_2, i32 2)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' ST_8 : Operation 60 [1/1] (1.76ns) ---> "br label %burst.rd.header.0" : 2.23ns ST_9 : Operation 61 [1/1] (0.00ns) ---> "%tempA_1_3 = phi i32 [ undef, %0 ], [ %tempA_1_3_2, %burst.rd.body.0_ifconv ]" ST_9 : Operation 62 [1/1] (0.00ns) ---> "%tempA_1_2_s = phi i32 [ undef, %0 ], [ %tempA_1_3_6, %burst.rd.body.0_ifconv ]" ST_9 : Operation 63 [1/1] (0.00ns) ---> "%tempA_1_1_s = phi i32 [ undef, %0 ], [ %tempA_1_3_10, %burst.rd.body.0_ifconv ]" ST_9 : Operation 64 [1/1] (0.00ns) ---> "%tempA_1_3_7 = phi i32 [ undef, %0 ], [ %tempA_1_3_8, %burst.rd.body.0_ifconv ]" ST_9 : Operation 65 [1/1] (0.00ns) ---> "%tempA_0_3 = phi i32 [ undef, %0 ], [ %tempA_0_3_2, %burst.rd.body.0_ifconv ]" ST_9 : Operation 66 [1/1] (0.00ns) ---> "%tempA_0_2_s = phi i32 [ undef, %0 ], [ %tempA_0_3_6, %burst.rd.body.0_ifconv ]" ST_9 : Operation 67 [1/1] (0.00ns) ---> "%tempA_0_1_s = phi i32 [ undef, %0 ], [ %tempA_0_3_10, %burst.rd.body.0_ifconv ]" ST_9 : Operation 68 [1/1] (0.00ns) ---> "%tempA_0_3_7 = phi i32 [ undef, %0 ], [ %tempA_0_3_8, %burst.rd.body.0_ifconv ]" ST_9 : Operation 69 [1/1] (0.00ns) ---> "%indvar = phi i4 [ 0, %0 ], [ %indvar_next_3, %burst.rd.body.0_ifconv ]" ST_9 : Operation 70 [1/1] (1.30ns) ---> "%exitcond1 = icmp eq i4 %indvar, -8" ---> Core 25 'Cmp' ST_9 : Operation 71 [1/1] (0.00ns) ---> "br i1 %exitcond1, label %burst.rd.header5.0.preheader, label %burst.rd.body.0_ifconv" ST_9 : Operation 72 [1/1] (0.00ns) ---> "%newIndex106_t = call i2 @_ssdm_op_PartSelect.i2.i4.i32.i32(i4 %indvar, i32 1, i32 2)" ST_9 : Operation 73 [1/1] (1.73ns) ---> "%indvar_next_3 = add i4 4, %indvar" ---> Core 14 'AddSub' : 8.75ns ST_10 : Operation 74 [1/1] (8.75ns) ---> "%gmem_addr_2_read = call i128 @_ssdm_op_Read.m_axi.i128P(i128* %gmem_addr_2)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' ST_10 : Operation 75 [1/1] (0.00ns) ---> "%tempA_0_3_11 = trunc i128 %gmem_addr_2_read to i32" [vector_mult/vector_mult.cpp:6] ST_10 : Operation 76 [1/1] (0.00ns) ---> "%tempA_1_3_11 = call i32 @_ssdm_op_PartSelect.i32.i128.i9.i9(i128 %gmem_addr_2_read, i9 32, i9 63)" [vector_mult/vector_mult.cpp:6] ST_10 : Operation 77 [1/1] (0.00ns) ---> "%tempA_0_1 = call i32 @_ssdm_op_PartSelect.i32.i128.i9.i9(i128 %gmem_addr_2_read, i9 64, i9 95)" [vector_mult/vector_mult.cpp:6] ST_10 : Operation 78 [1/1] (0.00ns) ---> "%tempA_1_1 = call i32 @_ssdm_op_PartSelect.i32.i128.i9.i9(i128 %gmem_addr_2_read, i9 96, i9 127)" [vector_mult/vector_mult.cpp:6] : 3.70ns ST_11 : Operation 79 [1/1] (0.00ns) ---> "%empty = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 2, i64 2, i64 2)" ST_11 : Operation 80 [1/1] (0.00ns) ---> "%burstread_rbegin = call i32 (...)* @_ssdm_op_SpecRegionBegin([17 x i8]* @burstread_OC_region_s) nounwind" ST_11 : Operation 81 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecPipeline(i32 1, i32 1, i32 1, i32 0, [1 x i8]* @p_str6)" ST_11 : Operation 82 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecLoopName([15 x i8]* @memcpy_OC_tempA_OC_A)" ST_11 : Operation 83 [1/1] (0.95ns) ---> "%sel_tmp = icmp eq i2 %newIndex106_t, -2" ---> Core 25 'Cmp' ST_11 : Operation 84 [1/1] (0.00ns) (grouped into LUT with out node tempA_0_3_1) ---> "%tempA_0_3_4 = select i1 %sel_tmp, i32 %tempA_0_3, i32 %tempA_0_3_11" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 85 [1/1] (0.95ns) ---> "%sel_tmp2 = icmp eq i2 %newIndex106_t, 0" ---> Core 25 'Cmp' ST_11 : Operation 86 [1/1] (1.37ns) (out node of the LUT) ---> "%tempA_0_3_1 = select i1 %sel_tmp2, i32 %tempA_0_3, i32 %tempA_0_3_4" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 87 [1/1] (0.00ns) (grouped into LUT with out node tempA_0_3_6) ---> "%tempA_0_3_5 = select i1 %sel_tmp, i32 %tempA_0_3_11, i32 %tempA_0_2_s" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 88 [1/1] (1.37ns) (out node of the LUT) ---> "%tempA_0_3_6 = select i1 %sel_tmp2, i32 %tempA_0_2_s, i32 %tempA_0_3_5" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 89 [1/1] (1.37ns) ---> "%tempA_0_3_8 = select i1 %sel_tmp2, i32 %tempA_0_3_11, i32 %tempA_0_3_7" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 90 [1/1] (0.00ns) ---> "%burstread_rend_0 = call i32 (...)* @_ssdm_op_SpecRegionEnd([17 x i8]* @burstread_OC_region_s, i32 %burstread_rbegin) nounwind" ST_11 : Operation 91 [1/1] (0.00ns) (grouped into LUT with out node tempA_1_3_1) ---> "%tempA_1_3_4 = select i1 %sel_tmp, i32 %tempA_1_3, i32 %tempA_1_3_11" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 92 [1/1] (1.37ns) (out node of the LUT) ---> "%tempA_1_3_1 = select i1 %sel_tmp2, i32 %tempA_1_3, i32 %tempA_1_3_4" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 93 [1/1] (0.00ns) (grouped into LUT with out node tempA_1_3_6) ---> "%tempA_1_3_5 = select i1 %sel_tmp, i32 %tempA_1_3_11, i32 %tempA_1_2_s" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 94 [1/1] (1.37ns) (out node of the LUT) ---> "%tempA_1_3_6 = select i1 %sel_tmp2, i32 %tempA_1_2_s, i32 %tempA_1_3_5" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 95 [1/1] (1.37ns) ---> "%tempA_1_3_8 = select i1 %sel_tmp2, i32 %tempA_1_3_11, i32 %tempA_1_3_7" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 96 [1/1] (0.00ns) (grouped into LUT with out node cond) ---> "%newIndex96_t = or i2 %newIndex106_t, 1" ST_11 : Operation 97 [1/1] (0.95ns) (out node of the LUT) ---> "%cond = icmp eq i2 %newIndex96_t, 1" [vector_mult/vector_mult.cpp:6] ---> Core 25 'Cmp' ST_11 : Operation 98 [1/1] (1.37ns) (out node of the LUT) ---> "%tempA_0_3_2 = select i1 %cond, i32 %tempA_0_3_1, i32 %tempA_0_1" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 99 [1/1] (1.37ns) ---> "%tempA_0_3_10 = select i1 %cond, i32 %tempA_0_1, i32 %tempA_0_1_s" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 100 [1/1] (1.37ns) (out node of the LUT) ---> "%tempA_1_3_2 = select i1 %cond, i32 %tempA_1_3_1, i32 %tempA_1_1" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 101 [1/1] (1.37ns) ---> "%tempA_1_3_10 = select i1 %cond, i32 %tempA_1_1, i32 %tempA_1_1_s" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 102 [1/1] (0.00ns) ---> "br label %burst.rd.header.0" : 8.75ns ST_12 : Operation 103 [7/7] (8.75ns) ---> "%gmem_addr_1_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i128P(i128* %gmem_addr_1, i32 2)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' : 8.75ns ST_13 : Operation 104 [6/7] (8.75ns) ---> "%gmem_addr_1_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i128P(i128* %gmem_addr_1, i32 2)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' : 8.75ns ST_14 : Operation 105 [5/7] (8.75ns) ---> "%gmem_addr_1_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i128P(i128* %gmem_addr_1, i32 2)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' : 8.75ns ST_15 : Operation 106 [4/7] (8.75ns) ---> "%gmem_addr_1_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i128P(i128* %gmem_addr_1, i32 2)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' : 8.75ns ST_16 : Operation 107 [3/7] (8.75ns) ---> "%gmem_addr_1_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i128P(i128* %gmem_addr_1, i32 2)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' : 8.75ns ST_17 : Operation 108 [2/7] (8.75ns) ---> "%gmem_addr_1_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i128P(i128* %gmem_addr_1, i32 2)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' : 8.75ns ST_18 : Operation 109 [1/7] (8.75ns) ---> "%gmem_addr_1_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i128P(i128* %gmem_addr_1, i32 2)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' ST_18 : Operation 110 [1/1] (1.76ns) ---> "br label %burst.rd.header5.0" : 2.23ns ST_19 : Operation 111 [1/1] (0.00ns) ---> "%tempB_1_3 = phi i32 [ %tempB_1_3_2, %burst.rd.body6.0_ifconv ], [ undef, %burst.rd.header5.0.preheader ]" ST_19 : Operation 112 [1/1] (0.00ns) ---> "%tempB_1_2_s = phi i32 [ %tempB_1_3_6, %burst.rd.body6.0_ifconv ], [ undef, %burst.rd.header5.0.preheader ]" ST_19 : Operation 113 [1/1] (0.00ns) ---> "%tempB_1_1_s = phi i32 [ %tempB_1_3_10, %burst.rd.body6.0_ifconv ], [ undef, %burst.rd.header5.0.preheader ]" ST_19 : Operation 114 [1/1] (0.00ns) ---> "%tempB_1_3_7 = phi i32 [ %tempB_1_3_8, %burst.rd.body6.0_ifconv ], [ undef, %burst.rd.header5.0.preheader ]" ST_19 : Operation 115 [1/1] (0.00ns) ---> "%tempB_0_3 = phi i32 [ %tempB_0_3_2, %burst.rd.body6.0_ifconv ], [ undef, %burst.rd.header5.0.preheader ]" ST_19 : Operation 116 [1/1] (0.00ns) ---> "%tempB_0_2_s = phi i32 [ %tempB_0_3_6, %burst.rd.body6.0_ifconv ], [ undef, %burst.rd.header5.0.preheader ]" ST_19 : Operation 117 [1/1] (0.00ns) ---> "%tempB_0_1_s = phi i32 [ %tempB_0_3_10, %burst.rd.body6.0_ifconv ], [ undef, %burst.rd.header5.0.preheader ]" ST_19 : Operation 118 [1/1] (0.00ns) ---> "%tempB_0_3_7 = phi i32 [ %tempB_0_3_8, %burst.rd.body6.0_ifconv ], [ undef, %burst.rd.header5.0.preheader ]" ST_19 : Operation 119 [1/1] (0.00ns) ---> "%indvar7 = phi i4 [ %indvar_next8_3, %burst.rd.body6.0_ifconv ], [ 0, %burst.rd.header5.0.preheader ]" ST_19 : Operation 120 [1/1] (1.30ns) ---> "%exitcond9 = icmp eq i4 %indvar7, -8" ---> Core 25 'Cmp' ST_19 : Operation 121 [1/1] (0.00ns) ---> "br i1 %exitcond9, label %burst.rd.end4.0.preheader, label %burst.rd.body6.0_ifconv" ST_19 : Operation 122 [1/1] (0.00ns) ---> "%newIndex66_t = call i2 @_ssdm_op_PartSelect.i2.i4.i32.i32(i4 %indvar7, i32 1, i32 2)" ST_19 : Operation 123 [1/1] (1.73ns) ---> "%indvar_next8_3 = add i4 4, %indvar7" ---> Core 14 'AddSub' : 8.75ns ST_20 : Operation 124 [1/1] (8.75ns) ---> "%gmem_addr_1_read = call i128 @_ssdm_op_Read.m_axi.i128P(i128* %gmem_addr_1)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' ST_20 : Operation 125 [1/1] (0.00ns) ---> "%tempB_0_3_11 = trunc i128 %gmem_addr_1_read to i32" [vector_mult/vector_mult.cpp:7] ST_20 : Operation 126 [1/1] (0.00ns) ---> "%tempB_1_3_11 = call i32 @_ssdm_op_PartSelect.i32.i128.i9.i9(i128 %gmem_addr_1_read, i9 32, i9 63)" [vector_mult/vector_mult.cpp:7] ST_20 : Operation 127 [1/1] (0.00ns) ---> "%tempB_0_1 = call i32 @_ssdm_op_PartSelect.i32.i128.i9.i9(i128 %gmem_addr_1_read, i9 64, i9 95)" [vector_mult/vector_mult.cpp:7] ST_20 : Operation 128 [1/1] (0.00ns) ---> "%tempB_1_1 = call i32 @_ssdm_op_PartSelect.i32.i128.i9.i9(i128 %gmem_addr_1_read, i9 96, i9 127)" [vector_mult/vector_mult.cpp:7] : 3.70ns ST_21 : Operation 129 [1/1] (0.00ns) ---> "%empty_8 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 2, i64 2, i64 2)" ST_21 : Operation 130 [1/1] (0.00ns) ---> "%burstread_rbegin1 = call i32 (...)* @_ssdm_op_SpecRegionBegin([17 x i8]* @burstread_OC_region_s) nounwind" ST_21 : Operation 131 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecPipeline(i32 1, i32 1, i32 1, i32 0, [1 x i8]* @p_str7)" ST_21 : Operation 132 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecLoopName([15 x i8]* @memcpy_OC_tempB_OC_B)" ST_21 : Operation 133 [1/1] (0.95ns) ---> "%sel_tmp6 = icmp eq i2 %newIndex66_t, -2" ---> Core 25 'Cmp' ST_21 : Operation 134 [1/1] (0.00ns) (grouped into LUT with out node tempB_0_3_1) ---> "%tempB_0_3_4 = select i1 %sel_tmp6, i32 %tempB_0_3, i32 %tempB_0_3_11" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 135 [1/1] (0.95ns) ---> "%sel_tmp8 = icmp eq i2 %newIndex66_t, 0" ---> Core 25 'Cmp' ST_21 : Operation 136 [1/1] (1.37ns) (out node of the LUT) ---> "%tempB_0_3_1 = select i1 %sel_tmp8, i32 %tempB_0_3, i32 %tempB_0_3_4" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 137 [1/1] (0.00ns) (grouped into LUT with out node tempB_0_3_6) ---> "%tempB_0_3_5 = select i1 %sel_tmp6, i32 %tempB_0_3_11, i32 %tempB_0_2_s" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 138 [1/1] (1.37ns) (out node of the LUT) ---> "%tempB_0_3_6 = select i1 %sel_tmp8, i32 %tempB_0_2_s, i32 %tempB_0_3_5" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 139 [1/1] (1.37ns) ---> "%tempB_0_3_8 = select i1 %sel_tmp8, i32 %tempB_0_3_11, i32 %tempB_0_3_7" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 140 [1/1] (0.00ns) ---> "%burstread_rend12_0 = call i32 (...)* @_ssdm_op_SpecRegionEnd([17 x i8]* @burstread_OC_region_s, i32 %burstread_rbegin1) nounwind" ST_21 : Operation 141 [1/1] (0.00ns) (grouped into LUT with out node tempB_1_3_1) ---> "%tempB_1_3_4 = select i1 %sel_tmp6, i32 %tempB_1_3, i32 %tempB_1_3_11" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 142 [1/1] (1.37ns) (out node of the LUT) ---> "%tempB_1_3_1 = select i1 %sel_tmp8, i32 %tempB_1_3, i32 %tempB_1_3_4" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 143 [1/1] (0.00ns) (grouped into LUT with out node tempB_1_3_6) ---> "%tempB_1_3_5 = select i1 %sel_tmp6, i32 %tempB_1_3_11, i32 %tempB_1_2_s" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 144 [1/1] (1.37ns) (out node of the LUT) ---> "%tempB_1_3_6 = select i1 %sel_tmp8, i32 %tempB_1_2_s, i32 %tempB_1_3_5" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 145 [1/1] (1.37ns) ---> "%tempB_1_3_8 = select i1 %sel_tmp8, i32 %tempB_1_3_11, i32 %tempB_1_3_7" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 146 [1/1] (0.00ns) (grouped into LUT with out node cond1) ---> "%newIndex56_t = or i2 %newIndex66_t, 1" ST_21 : Operation 147 [1/1] (0.95ns) (out node of the LUT) ---> "%cond1 = icmp eq i2 %newIndex56_t, 1" [vector_mult/vector_mult.cpp:7] ---> Core 25 'Cmp' ST_21 : Operation 148 [1/1] (1.37ns) (out node of the LUT) ---> "%tempB_0_3_2 = select i1 %cond1, i32 %tempB_0_3_1, i32 %tempB_0_1" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 149 [1/1] (1.37ns) ---> "%tempB_0_3_10 = select i1 %cond1, i32 %tempB_0_1, i32 %tempB_0_1_s" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 150 [1/1] (1.37ns) (out node of the LUT) ---> "%tempB_1_3_2 = select i1 %cond1, i32 %tempB_1_3_1, i32 %tempB_1_1" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 151 [1/1] (1.37ns) ---> "%tempB_1_3_10 = select i1 %cond1, i32 %tempB_1_1, i32 %tempB_1_1_s" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 152 [1/1] (0.00ns) ---> "br label %burst.rd.header5.0" : 1.77ns ST_22 : Operation 153 [1/1] (1.76ns) ---> "br label %burst.rd.end4.0" [vector_mult/vector_mult.cpp:8] : 2.23ns ST_23 : Operation 154 [1/1] (0.00ns) ---> "%tempResult_1_3 = phi i32 [ %tempResult_1_3_2, %burst.rd.end4.1_ifconv ], [ undef, %burst.rd.end4.0.preheader ]" ST_23 : Operation 155 [1/1] (0.00ns) ---> "%tempResult_1_2_s = phi i32 [ %tempResult_1_3_6, %burst.rd.end4.1_ifconv ], [ undef, %burst.rd.end4.0.preheader ]" ST_23 : Operation 156 [1/1] (0.00ns) ---> "%tempResult_1_1_s = phi i32 [ %tempResult_1_3_10, %burst.rd.end4.1_ifconv ], [ undef, %burst.rd.end4.0.preheader ]" ST_23 : Operation 157 [1/1] (0.00ns) ---> "%tempResult_1_3_7 = phi i32 [ %tempResult_1_3_8, %burst.rd.end4.1_ifconv ], [ undef, %burst.rd.end4.0.preheader ]" ST_23 : Operation 158 [1/1] (0.00ns) ---> "%tempResult_0_3 = phi i32 [ %tempResult_0_3_2, %burst.rd.end4.1_ifconv ], [ undef, %burst.rd.end4.0.preheader ]" ST_23 : Operation 159 [1/1] (0.00ns) ---> "%tempResult_0_2_s = phi i32 [ %tempResult_0_3_6, %burst.rd.end4.1_ifconv ], [ undef, %burst.rd.end4.0.preheader ]" ST_23 : Operation 160 [1/1] (0.00ns) ---> "%tempResult_0_1_s = phi i32 [ %tempResult_0_3_10, %burst.rd.end4.1_ifconv ], [ undef, %burst.rd.end4.0.preheader ]" ST_23 : Operation 161 [1/1] (0.00ns) ---> "%tempResult_0_3_7 = phi i32 [ %tempResult_0_3_8, %burst.rd.end4.1_ifconv ], [ undef, %burst.rd.end4.0.preheader ]" ST_23 : Operation 162 [1/1] (0.00ns) ---> "%i = phi i4 [ %i_1_3, %burst.rd.end4.1_ifconv ], [ 0, %burst.rd.end4.0.preheader ]" [vector_mult/vector_mult.cpp:8] ST_23 : Operation 163 [1/1] (1.30ns) ---> "%exitcond = icmp eq i4 %i, -8" [vector_mult/vector_mult.cpp:8] ---> Core 25 'Cmp' ST_23 : Operation 164 [1/1] (0.00ns) ---> "br i1 %exitcond, label %burst.wr.header.0.preheader, label %burst.rd.end4.1_ifconv" [vector_mult/vector_mult.cpp:8] ST_23 : Operation 165 [1/1] (0.00ns) ---> "%newIndex126_t = call i2 @_ssdm_op_PartSelect.i2.i4.i32.i32(i4 %i, i32 1, i32 2)" [vector_mult/vector_mult.cpp:8] ST_23 : Operation 166 [1/1] (1.95ns) ---> "%tmp = call i32 @_ssdm_op_Mux.ap_auto.4i32.i2(i32 %tempA_0_3_7, i32 %tempA_0_1_s, i32 %tempA_0_2_s, i32 %tempA_0_3, i2 %newIndex126_t)" [vector_mult/vector_mult.cpp:6] ---> Core 31 'MuxnS' ST_23 : Operation 167 [1/1] (1.95ns) ---> "%tmp_3 = call i32 @_ssdm_op_Mux.ap_auto.4i32.i2(i32 %tempB_0_3_7, i32 %tempB_0_1_s, i32 %tempB_0_2_s, i32 %tempB_0_3, i2 %newIndex126_t)" [vector_mult/vector_mult.cpp:7] ---> Core 31 'MuxnS' ST_23 : Operation 168 [1/1] (1.95ns) ---> "%tmp_4 = call i32 @_ssdm_op_Mux.ap_auto.4i32.i2(i32 %tempA_1_3_7, i32 %tempA_1_1_s, i32 %tempA_1_2_s, i32 %tempA_1_3, i2 %newIndex126_t)" [vector_mult/vector_mult.cpp:6] ---> Core 31 'MuxnS' ST_23 : Operation 169 [1/1] (1.95ns) ---> "%tmp_7 = call i32 @_ssdm_op_Mux.ap_auto.4i32.i2(i32 %tempB_1_3_7, i32 %tempB_1_1_s, i32 %tempB_1_2_s, i32 %tempB_1_3, i2 %newIndex126_t)" [vector_mult/vector_mult.cpp:7] ---> Core 31 'MuxnS' ST_23 : Operation 170 [1/1] (0.00ns) ---> "%newIndex116_t = or i2 %newIndex126_t, 1" [vector_mult/vector_mult.cpp:8] ST_23 : Operation 171 [1/1] (1.95ns) ---> "%tmp_9 = call i32 @_ssdm_op_Mux.ap_auto.4i32.i2(i32 %tempA_0_3_7, i32 %tempA_0_1_s, i32 %tempA_0_2_s, i32 %tempA_0_3, i2 %newIndex116_t)" [vector_mult/vector_mult.cpp:6] ---> Core 31 'MuxnS' ST_23 : Operation 172 [1/1] (1.95ns) ---> "%tmp_5 = call i32 @_ssdm_op_Mux.ap_auto.4i32.i2(i32 %tempB_0_3_7, i32 %tempB_0_1_s, i32 %tempB_0_2_s, i32 %tempB_0_3, i2 %newIndex116_t)" [vector_mult/vector_mult.cpp:7] ---> Core 31 'MuxnS' ST_23 : Operation 173 [1/1] (0.95ns) ---> "%cond2 = icmp eq i2 %newIndex116_t, 1" [vector_mult/vector_mult.cpp:9] ---> Core 25 'Cmp' ST_23 : Operation 174 [1/1] (1.95ns) ---> "%tmp_6 = call i32 @_ssdm_op_Mux.ap_auto.4i32.i2(i32 %tempA_1_3_7, i32 %tempA_1_1_s, i32 %tempA_1_2_s, i32 %tempA_1_3, i2 %newIndex116_t)" [vector_mult/vector_mult.cpp:6] ---> Core 31 'MuxnS' ST_23 : Operation 175 [1/1] (1.95ns) ---> "%tmp_10 = call i32 @_ssdm_op_Mux.ap_auto.4i32.i2(i32 %tempB_1_3_7, i32 %tempB_1_1_s, i32 %tempB_1_2_s, i32 %tempB_1_3, i2 %newIndex116_t)" [vector_mult/vector_mult.cpp:7] ---> Core 31 'MuxnS' ST_23 : Operation 176 [1/1] (1.73ns) ---> "%i_1_3 = add i4 %i, 4" [vector_mult/vector_mult.cpp:8] ---> Core 14 'AddSub' : 8.51ns ST_24 : Operation 177 [1/1] (8.51ns) ---> "%tempResult_0_3_11 = mul nsw i32 %tmp_3, %tmp" [vector_mult/vector_mult.cpp:9] ---> Core 16 'Mul' ST_24 : Operation 178 [1/1] (8.51ns) ---> "%tempResult_1_3_11 = mul nsw i32 %tmp_7, %tmp_4" [vector_mult/vector_mult.cpp:9] ---> Core 16 'Mul' ST_24 : Operation 179 [1/1] (8.51ns) ---> "%tempResult_0_1 = mul nsw i32 %tmp_5, %tmp_9" [vector_mult/vector_mult.cpp:9] ---> Core 16 'Mul' ST_24 : Operation 180 [1/1] (8.51ns) ---> "%tempResult_1_1 = mul nsw i32 %tmp_10, %tmp_6" [vector_mult/vector_mult.cpp:9] ---> Core 16 'Mul' : 3.70ns ST_25 : Operation 181 [1/1] (0.00ns) ---> "%empty_9 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 2, i64 2, i64 2) nounwind" ST_25 : Operation 182 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecLoopName([17 x i8]* @p_str5) nounwind" [vector_mult/vector_mult.cpp:10] ST_25 : Operation 183 [1/1] (0.00ns) ---> "%tmp_8 = call i32 (...)* @_ssdm_op_SpecRegionBegin([17 x i8]* @p_str5) nounwind" [vector_mult/vector_mult.cpp:10] ST_25 : Operation 184 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind" [vector_mult/vector_mult.cpp:10] ST_25 : Operation 185 [1/1] (0.95ns) ---> "%sel_tmp1 = icmp eq i2 %newIndex126_t, -2" [vector_mult/vector_mult.cpp:8] ---> Core 25 'Cmp' ST_25 : Operation 186 [1/1] (0.00ns) (grouped into LUT with out node tempResult_0_3_1) ---> "%tempResult_0_3_4 = select i1 %sel_tmp1, i32 %tempResult_0_3, i32 %tempResult_0_3_11" [vector_mult/vector_mult.cpp:8] ---> Core 26 'Sel' ST_25 : Operation 187 [1/1] (0.95ns) ---> "%sel_tmp3 = icmp eq i2 %newIndex126_t, 0" [vector_mult/vector_mult.cpp:8] ---> Core 25 'Cmp' ST_25 : Operation 188 [1/1] (1.37ns) (out node of the LUT) ---> "%tempResult_0_3_1 = select i1 %sel_tmp3, i32 %tempResult_0_3, i32 %tempResult_0_3_4" [vector_mult/vector_mult.cpp:8] ---> Core 26 'Sel' ST_25 : Operation 189 [1/1] (0.00ns) (grouped into LUT with out node tempResult_0_3_6) ---> "%tempResult_0_3_5 = select i1 %sel_tmp1, i32 %tempResult_0_3_11, i32 %tempResult_0_2_s" [vector_mult/vector_mult.cpp:8] ---> Core 26 'Sel' ST_25 : Operation 190 [1/1] (1.37ns) (out node of the LUT) ---> "%tempResult_0_3_6 = select i1 %sel_tmp3, i32 %tempResult_0_2_s, i32 %tempResult_0_3_5" [vector_mult/vector_mult.cpp:8] ---> Core 26 'Sel' ST_25 : Operation 191 [1/1] (1.37ns) ---> "%tempResult_0_3_8 = select i1 %sel_tmp3, i32 %tempResult_0_3_11, i32 %tempResult_0_3_7" [vector_mult/vector_mult.cpp:8] ---> Core 26 'Sel' ST_25 : Operation 192 [1/1] (0.00ns) ---> "%empty_10 = call i32 (...)* @_ssdm_op_SpecRegionEnd([17 x i8]* @p_str5, i32 %tmp_8) nounwind" [vector_mult/vector_mult.cpp:9] ST_25 : Operation 193 [1/1] (0.00ns) (grouped into LUT with out node tempResult_1_3_1) ---> "%tempResult_1_3_4 = select i1 %sel_tmp1, i32 %tempResult_1_3, i32 %tempResult_1_3_11" [vector_mult/vector_mult.cpp:8] ---> Core 26 'Sel' ST_25 : Operation 194 [1/1] (1.37ns) (out node of the LUT) ---> "%tempResult_1_3_1 = select i1 %sel_tmp3, i32 %tempResult_1_3, i32 %tempResult_1_3_4" [vector_mult/vector_mult.cpp:8] ---> Core 26 'Sel' ST_25 : Operation 195 [1/1] (0.00ns) (grouped into LUT with out node tempResult_1_3_6) ---> "%tempResult_1_3_5 = select i1 %sel_tmp1, i32 %tempResult_1_3_11, i32 %tempResult_1_2_s" [vector_mult/vector_mult.cpp:8] ---> Core 26 'Sel' ST_25 : Operation 196 [1/1] (1.37ns) (out node of the LUT) ---> "%tempResult_1_3_6 = select i1 %sel_tmp3, i32 %tempResult_1_2_s, i32 %tempResult_1_3_5" [vector_mult/vector_mult.cpp:8] ---> Core 26 'Sel' ST_25 : Operation 197 [1/1] (1.37ns) ---> "%tempResult_1_3_8 = select i1 %sel_tmp3, i32 %tempResult_1_3_11, i32 %tempResult_1_3_7" [vector_mult/vector_mult.cpp:8] ---> Core 26 'Sel' ST_25 : Operation 198 [1/1] (1.37ns) (out node of the LUT) ---> "%tempResult_0_3_2 = select i1 %cond2, i32 %tempResult_0_3_1, i32 %tempResult_0_1" [vector_mult/vector_mult.cpp:9] ---> Core 26 'Sel' ST_25 : Operation 199 [1/1] (1.37ns) ---> "%tempResult_0_3_10 = select i1 %cond2, i32 %tempResult_0_1, i32 %tempResult_0_1_s" [vector_mult/vector_mult.cpp:9] ---> Core 26 'Sel' ST_25 : Operation 200 [1/1] (1.37ns) (out node of the LUT) ---> "%tempResult_1_3_2 = select i1 %cond2, i32 %tempResult_1_3_1, i32 %tempResult_1_1" [vector_mult/vector_mult.cpp:9] ---> Core 26 'Sel' ST_25 : Operation 201 [1/1] (1.37ns) ---> "%tempResult_1_3_10 = select i1 %cond2, i32 %tempResult_1_1, i32 %tempResult_1_1_s" [vector_mult/vector_mult.cpp:9] ---> Core 26 'Sel' ST_25 : Operation 202 [1/1] (0.00ns) ---> "br label %burst.rd.end4.0" [vector_mult/vector_mult.cpp:8] : 8.75ns ST_26 : Operation 203 [1/1] (8.75ns) ---> "%gmem_addr_wr_req = call i1 @_ssdm_op_WriteReq.m_axi.i128P(i128* %gmem_addr, i32 2)" [vector_mult/vector_mult.cpp:10] ---> Core 9 'm_axi' ST_26 : Operation 204 [1/1] (1.76ns) ---> "br label %burst.wr.header.0" : 2.23ns ST_27 : Operation 205 [1/1] (0.00ns) ---> "%indvar1 = phi i4 [ %indvar_next1_3, %burst.wr.body.0 ], [ 0, %burst.wr.header.0.preheader ]" ST_27 : Operation 206 [1/1] (1.30ns) ---> "%exitcond2 = icmp eq i4 %indvar1, -8" ---> Core 25 'Cmp' ST_27 : Operation 207 [1/1] (0.00ns) ---> "br i1 %exitcond2, label %memcpy.tail, label %burst.wr.body.0" ST_27 : Operation 208 [1/1] (0.00ns) ---> "%newIndex26_t = call i2 @_ssdm_op_PartSelect.i2.i4.i32.i32(i4 %indvar1, i32 1, i32 2)" ST_27 : Operation 209 [1/1] (1.95ns) ---> "%tmp_12 = call i32 @_ssdm_op_Mux.ap_auto.4i32.i2(i32 %tempResult_0_3_7, i32 %tempResult_0_1_s, i32 %tempResult_0_2_s, i32 %tempResult_0_3, i2 %newIndex26_t)" [vector_mult/vector_mult.cpp:8] ---> Core 31 'MuxnS' ST_27 : Operation 210 [1/1] (1.95ns) ---> "%tmp_13 = call i32 @_ssdm_op_Mux.ap_auto.4i32.i2(i32 %tempResult_1_3_7, i32 %tempResult_1_1_s, i32 %tempResult_1_2_s, i32 %tempResult_1_3, i2 %newIndex26_t)" [vector_mult/vector_mult.cpp:8] ---> Core 31 'MuxnS' ST_27 : Operation 211 [1/1] (0.00ns) ---> "%newIndex16_t = or i2 %newIndex26_t, 1" ST_27 : Operation 212 [1/1] (1.95ns) ---> "%tmp_14 = call i32 @_ssdm_op_Mux.ap_auto.4i32.i2(i32 %tempResult_0_3_7, i32 %tempResult_0_1_s, i32 %tempResult_0_2_s, i32 %tempResult_0_3, i2 %newIndex16_t)" [vector_mult/vector_mult.cpp:8] ---> Core 31 'MuxnS' ST_27 : Operation 213 [1/1] (1.73ns) ---> "%indvar_next1_3 = add i4 %indvar1, 4" ---> Core 14 'AddSub' ST_27 : Operation 214 [1/1] (1.95ns) ---> "%tmp_15 = call i32 @_ssdm_op_Mux.ap_auto.4i32.i2(i32 %tempResult_1_3_7, i32 %tempResult_1_1_s, i32 %tempResult_1_2_s, i32 %tempResult_1_3, i2 %newIndex16_t)" [vector_mult/vector_mult.cpp:8] ---> Core 31 'MuxnS' : 8.75ns ST_28 : Operation 215 [1/1] (0.00ns) ---> "%empty_11 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 2, i64 2, i64 2) nounwind" ST_28 : Operation 216 [1/1] (0.00ns) ---> "%burstwrite_rbegin = call i32 (...)* @_ssdm_op_SpecRegionBegin([18 x i8]* @burstwrite_OC_region) nounwind" ST_28 : Operation 217 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecPipeline(i32 1, i32 1, i32 1, i32 0, [1 x i8]* @p_str9)" ST_28 : Operation 218 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecLoopName([29 x i8]* @memcpy_OC_result_OC_s)" ST_28 : Operation 219 [1/1] (0.00ns) ---> "%burstwrite_rend_0 = call i32 (...)* @_ssdm_op_SpecRegionEnd([18 x i8]* @burstwrite_OC_region, i32 %burstwrite_rbegin) nounwind" ST_28 : Operation 220 [1/1] (0.00ns) ---> "%tmp_11 = call i128 @_ssdm_op_BitConcatenate.i128.i32.i32.i32.i32(i32 %tmp_15, i32 %tmp_14, i32 %tmp_13, i32 %tmp_12)" [vector_mult/vector_mult.cpp:10] ST_28 : Operation 221 [1/1] (8.75ns) ---> "call void @_ssdm_op_Write.m_axi.i128P(i128* %gmem_addr, i128 %tmp_11, i16 -1)" [vector_mult/vector_mult.cpp:10] ---> Core 9 'm_axi' ST_28 : Operation 222 [1/1] (0.00ns) ---> "br label %burst.wr.header.0" : 8.75ns ST_29 : Operation 223 [5/5] (8.75ns) ---> "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i128P(i128* %gmem_addr)" [vector_mult/vector_mult.cpp:10] ---> Core 9 'm_axi' : 8.75ns ST_30 : Operation 224 [4/5] (8.75ns) ---> "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i128P(i128* %gmem_addr)" [vector_mult/vector_mult.cpp:10] ---> Core 9 'm_axi' : 8.75ns ST_31 : Operation 225 [3/5] (8.75ns) ---> "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i128P(i128* %gmem_addr)" [vector_mult/vector_mult.cpp:10] ---> Core 9 'm_axi' : 8.75ns ST_32 : Operation 226 [2/5] (8.75ns) ---> "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i128P(i128* %gmem_addr)" [vector_mult/vector_mult.cpp:10] ---> Core 9 'm_axi' : 8.75ns ST_33 : Operation 227 [1/5] (8.75ns) ---> "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i128P(i128* %gmem_addr)" [vector_mult/vector_mult.cpp:10] ---> Core 9 'm_axi' ST_33 : Operation 228 [1/1] (0.00ns) ---> "ret void" [vector_mult/vector_mult.cpp:11] ============================================================ + Verbose Summary: Timing violations ============================================================ Target clock period: 10ns, clock uncertainty: 1.25ns. : 1ns The critical path consists of the following: s_axi read on port 'result' [5] (1 ns) : 8.75ns The critical path consists of the following: 'getelementptr' operation ('gmem_addr_2') [16] (0 ns) bus request on port 'gmem' (vector_mult/vector_mult.cpp:6) [24] (8.75 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:6) [24] (8.75 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:6) [24] (8.75 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:6) [24] (8.75 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:6) [24] (8.75 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:6) [24] (8.75 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:6) [24] (8.75 ns) : 2.23ns The critical path consists of the following: 'icmp' operation ('exitcond1') [36] (1.3 ns) blocking operation 0.931 ns on control path) : 8.75ns The critical path consists of the following: bus read on port 'gmem' (vector_mult/vector_mult.cpp:6) [43] (8.75 ns) : 3.7ns The critical path consists of the following: 'icmp' operation ('sel_tmp') [46] (0.959 ns) 'select' operation ('tempA[0][3]', vector_mult/vector_mult.cpp:6) [47] (0 ns) 'select' operation ('tempA[0][3]', vector_mult/vector_mult.cpp:6) [49] (1.37 ns) 'select' operation ('tempA[0][3]', vector_mult/vector_mult.cpp:6) [63] (1.37 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:7) [71] (8.75 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:7) [71] (8.75 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:7) [71] (8.75 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:7) [71] (8.75 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:7) [71] (8.75 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:7) [71] (8.75 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:7) [71] (8.75 ns) : 2.23ns The critical path consists of the following: 'icmp' operation ('exitcond9') [83] (1.3 ns) blocking operation 0.931 ns on control path) : 8.75ns The critical path consists of the following: bus read on port 'gmem' (vector_mult/vector_mult.cpp:7) [90] (8.75 ns) : 3.7ns The critical path consists of the following: 'icmp' operation ('sel_tmp6') [93] (0.959 ns) 'select' operation ('tempB[0][3]', vector_mult/vector_mult.cpp:7) [94] (0 ns) 'select' operation ('tempB[0][3]', vector_mult/vector_mult.cpp:7) [96] (1.37 ns) 'select' operation ('tempB[0][3]', vector_mult/vector_mult.cpp:7) [110] (1.37 ns) : 1.77ns The critical path consists of the following: multiplexor before 'phi' operation ('tempResult[1][3]') with incoming values : ('tempResult[1][3]', vector_mult/vector_mult.cpp:9) [120] (1.77 ns) : 2.23ns The critical path consists of the following: 'icmp' operation ('exitcond', vector_mult/vector_mult.cpp:8) [129] (1.3 ns) blocking operation 0.931 ns on control path) : 8.51ns The critical path consists of the following: 'mul' operation ('tempResult[0][3]', vector_mult/vector_mult.cpp:9) [139] (8.51 ns) : 3.7ns The critical path consists of the following: 'icmp' operation ('sel_tmp1', vector_mult/vector_mult.cpp:8) [140] (0.959 ns) 'select' operation ('tempResult[0][3]', vector_mult/vector_mult.cpp:8) [141] (0 ns) 'select' operation ('tempResult[0][3]', vector_mult/vector_mult.cpp:8) [143] (1.37 ns) 'select' operation ('tempResult[0][3]', vector_mult/vector_mult.cpp:9) [161] (1.37 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:10) [171] (8.75 ns) : 2.23ns The critical path consists of the following: 'icmp' operation ('exitcond2') [175] (1.3 ns) blocking operation 0.931 ns on control path) : 8.75ns The critical path consists of the following: bus write on port 'gmem' (vector_mult/vector_mult.cpp:10) [191] (8.75 ns) : 8.75ns The critical path consists of the following: bus access on port 'gmem' (vector_mult/vector_mult.cpp:10) [194] (8.75 ns) : 8.75ns The critical path consists of the following: bus access on port 'gmem' (vector_mult/vector_mult.cpp:10) [194] (8.75 ns) : 8.75ns The critical path consists of the following: bus access on port 'gmem' (vector_mult/vector_mult.cpp:10) [194] (8.75 ns) : 8.75ns The critical path consists of the following: bus access on port 'gmem' (vector_mult/vector_mult.cpp:10) [194] (8.75 ns) : 8.75ns The critical path consists of the following: bus access on port 'gmem' (vector_mult/vector_mult.cpp:10) [194] (8.75 ns) ============================================================ + Verbose Summary: Binding ============================================================ N/A * FSMD analyzer results: - Output states: - Input state : - Chain level: State 1 State 2 State 3 State 4 State 5 State 6 State 7 State 8 State 9 State 10 State 11 State 12 State 13 State 14 State 15 State 16 State 17 State 18 State 19 State 20 State 21 State 22 State 23 State 24 State 25 State 26 State 27 State 28 State 29 State 30 State 31 State 32 State 33 ============================================================ + Verbose Summary: Datapath Resource usage ============================================================ N/A