================================================================ == Vivado HLS Report for 'vector_mult' ================================================================ * Date: Mon Mar 19 10:54:34 2018 * Version: 2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017) * Project: vector_mult * Solution: solution3 * Product family: zynq * Target device: xc7z020clg484-1 ================================================================ == Performance Estimates ================================================================ + Timing (ns): * Summary: +--------+-------+----------+------------+ | Clock | Target| Estimated| Uncertainty| +--------+-------+----------+------------+ |ap_clk | 10.00| 8.75| 1.25| +--------+-------+----------+------------+ + Latency (clock cycles): * Summary: +-----+-----+-----+-----+---------+ | Latency | Interval | Pipeline| | min | max | min | max | Type | +-----+-----+-----+-----+---------+ | 54| 54| 54| 54| none | +-----+-----+-----+-----+---------+ + Detail: * Instance: N/A * Loop: +--------------------------------+-----+-----+----------+-----------+-----------+------+----------+ | | Latency | Iteration| Initiation Interval | Trip | | | Loop Name | min | max | Latency | achieved | target | Count| Pipelined| +--------------------------------+-----+-----+----------+-----------+-----------+------+----------+ |- memcpy.tempA.A | 9| 9| 3| 1| 1| 8| yes | |- memcpy.tempB.B | 9| 9| 3| 1| 1| 8| yes | |- vector_mult_loop | 3| 3| 3| 1| 1| 2| yes | |- memcpy.result.tempResult.gep | 8| 8| 2| 1| 1| 8| yes | +--------------------------------+-----+-----+----------+-----------+-----------+------+----------+ ================================================================ == Utilization Estimates ================================================================ * Summary: +-----------------+---------+-------+--------+-------+ | Name | BRAM_18K| DSP48E| FF | LUT | +-----------------+---------+-------+--------+-------+ |DSP | -| -| -| -| |Expression | -| 12| 0| 2251| |FIFO | -| -| -| -| |Instance | 2| -| 662| 1022| |Memory | -| -| -| -| |Multiplexer | -| -| -| 317| |Register | -| -| 1479| -| +-----------------+---------+-------+--------+-------+ |Total | 2| 12| 2141| 3590| +-----------------+---------+-------+--------+-------+ |Available | 280| 220| 106400| 53200| +-----------------+---------+-------+--------+-------+ |Utilization (%) | ~0 | 5| 2| 6| +-----------------+---------+-------+--------+-------+ + Detail: * Instance: +------------------------------+----------------------------+---------+-------+-----+-----+ | Instance | Module | BRAM_18K| DSP48E| FF | LUT | +------------------------------+----------------------------+---------+-------+-----+-----+ |vector_mult_AXILiteS_s_axi_U |vector_mult_AXILiteS_s_axi | 0| 0| 150| 232| |vector_mult_gmem_m_axi_U |vector_mult_gmem_m_axi | 2| 0| 512| 580| |vector_mult_mux_4bkb_U1 |vector_mult_mux_4bkb | 0| 0| 0| 21| |vector_mult_mux_4bkb_U2 |vector_mult_mux_4bkb | 0| 0| 0| 21| |vector_mult_mux_4bkb_U3 |vector_mult_mux_4bkb | 0| 0| 0| 21| |vector_mult_mux_4bkb_U4 |vector_mult_mux_4bkb | 0| 0| 0| 21| |vector_mult_mux_4bkb_U5 |vector_mult_mux_4bkb | 0| 0| 0| 21| |vector_mult_mux_4bkb_U6 |vector_mult_mux_4bkb | 0| 0| 0| 21| |vector_mult_mux_4bkb_U7 |vector_mult_mux_4bkb | 0| 0| 0| 21| |vector_mult_mux_4bkb_U8 |vector_mult_mux_4bkb | 0| 0| 0| 21| |vector_mult_mux_4bkb_U9 |vector_mult_mux_4bkb | 0| 0| 0| 21| |vector_mult_mux_4bkb_U10 |vector_mult_mux_4bkb | 0| 0| 0| 21| +------------------------------+----------------------------+---------+-------+-----+-----+ |Total | | 2| 0| 662| 1022| +------------------------------+----------------------------+---------+-------+-----+-----+ * DSP48: N/A * Memory: N/A * FIFO: N/A * Expression: +-----------------------------------+----------+-------+---+----+------------+------------+ | Variable Name | Operation| DSP48E| FF| LUT| Bitwidth P0| Bitwidth P1| +-----------------------------------+----------+-------+---+----+------------+------------+ |tempResult_0_1_fu_1148_p2 | * | 3| 0| 20| 32| 32| |tempResult_0_3_11_fu_1140_p2 | * | 3| 0| 20| 32| 32| |tempResult_1_1_fu_1152_p2 | * | 3| 0| 20| 32| 32| |tempResult_1_3_11_fu_1144_p2 | * | 3| 0| 20| 32| 32| |i_1_3_fu_1134_p2 | + | 0| 0| 13| 4| 3| |indvar_next1_fu_1270_p2 | + | 0| 0| 13| 4| 1| |indvar_next8_fu_787_p2 | + | 0| 0| 13| 4| 1| |indvar_next_fu_574_p2 | + | 0| 0| 13| 4| 1| |ap_block_pp0_stage0_11001 | and | 0| 0| 8| 1| 1| |ap_block_pp1_stage0_11001 | and | 0| 0| 8| 1| 1| |ap_block_pp3_stage0_11001 | and | 0| 0| 8| 1| 1| |ap_block_state10_pp0_stage0_iter1 | and | 0| 0| 8| 1| 1| |ap_block_state20_pp1_stage0_iter1 | and | 0| 0| 8| 1| 1| |ap_block_state28_io | and | 0| 0| 8| 1| 1| |ap_condition_1367 | and | 0| 0| 8| 1| 1| |cond_fu_1100_p2 | icmp | 0| 0| 8| 2| 1| |exitcond1_fu_568_p2 | icmp | 0| 0| 11| 4| 5| |exitcond2_fu_1264_p2 | icmp | 0| 0| 11| 4| 5| |exitcond9_fu_781_p2 | icmp | 0| 0| 11| 4| 5| |exitcond_fu_994_p2 | icmp | 0| 0| 11| 4| 5| |sel_tmp1_fu_819_p2 | icmp | 0| 0| 8| 2| 1| |sel_tmp2_fu_606_p2 | icmp | 0| 0| 8| 2| 1| |sel_tmp3_fu_832_p2 | icmp | 0| 0| 8| 2| 1| |sel_tmp4_fu_619_p2 | icmp | 0| 0| 8| 2| 1| |sel_tmp5_fu_1156_p2 | icmp | 0| 0| 9| 2| 3| |sel_tmp6_fu_1168_p2 | icmp | 0| 0| 8| 2| 1| |sel_tmp8_fu_807_p2 | icmp | 0| 0| 9| 2| 3| |sel_tmp_fu_594_p2 | icmp | 0| 0| 9| 2| 3| |newIndex68_t_fu_1066_p2 | or | 0| 0| 8| 2| 1| |or_cond1_fu_717_p2 | or | 0| 0| 8| 1| 1| |or_cond2_fu_723_p2 | or | 0| 0| 8| 1| 1| |or_cond7_fu_925_p2 | or | 0| 0| 8| 1| 1| |or_cond8_fu_930_p2 | or | 0| 0| 8| 1| 1| |or_cond9_fu_936_p2 | or | 0| 0| 8| 1| 1| |or_cond_fu_712_p2 | or | 0| 0| 8| 1| 1| |newSel1_fu_743_p3 | select | 0| 0| 32| 1| 32| |newSel3_fu_759_p3 | select | 0| 0| 32| 1| 32| |newSel6_fu_949_p3 | select | 0| 0| 32| 1| 32| |newSel7_fu_956_p3 | select | 0| 0| 32| 1| 32| |newSel9_fu_972_p3 | select | 0| 0| 32| 1| 32| |newSel_fu_736_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_11_fu_670_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_14_fu_677_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_15_fu_691_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_16_fu_698_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_17_fu_705_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_18_fu_729_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_19_fu_751_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_1_fu_684_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_20_fu_766_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_21_fu_774_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_2_fu_624_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_3_fu_611_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_4_fu_632_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_5_fu_639_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_6_fu_647_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_8_fu_655_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_9_fu_662_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_fu_599_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_11_fu_883_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_14_fu_890_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_15_fu_904_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_16_fu_911_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_17_fu_918_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_18_fu_942_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_19_fu_964_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_1_fu_897_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_20_fu_979_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_21_fu_987_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_2_fu_837_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_3_fu_824_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_4_fu_845_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_5_fu_852_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_6_fu_860_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_8_fu_868_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_9_fu_875_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_fu_812_p3 | select | 0| 0| 32| 1| 32| |tempResult_0_3_10_fu_1246_p3 | select | 0| 0| 32| 1| 32| |tempResult_0_3_1_fu_1173_p3 | select | 0| 0| 32| 1| 32| |tempResult_0_3_2_fu_1240_p3 | select | 0| 0| 32| 1| 32| |tempResult_0_3_4_fu_1161_p3 | select | 0| 0| 32| 1| 32| |tempResult_0_3_5_fu_1181_p3 | select | 0| 0| 32| 1| 32| |tempResult_0_3_6_fu_1188_p3 | select | 0| 0| 32| 1| 32| |tempResult_0_3_8_fu_1196_p3 | select | 0| 0| 32| 1| 32| |tempResult_1_3_10_fu_1258_p3 | select | 0| 0| 32| 1| 32| |tempResult_1_3_1_fu_1210_p3 | select | 0| 0| 32| 1| 32| |tempResult_1_3_2_fu_1252_p3 | select | 0| 0| 32| 1| 32| |tempResult_1_3_4_fu_1203_p3 | select | 0| 0| 32| 1| 32| |tempResult_1_3_5_fu_1218_p3 | select | 0| 0| 32| 1| 32| |tempResult_1_3_6_fu_1225_p3 | select | 0| 0| 32| 1| 32| |tempResult_1_3_8_fu_1233_p3 | select | 0| 0| 32| 1| 32| |tempResult_load_phi_fu_1318_p3 | select | 0| 0| 32| 1| 32| |ap_enable_pp0 | xor | 0| 0| 8| 1| 2| |ap_enable_pp1 | xor | 0| 0| 8| 1| 2| |ap_enable_pp2 | xor | 0| 0| 8| 1| 2| |ap_enable_pp3 | xor | 0| 0| 8| 1| 2| |ap_enable_reg_pp0_iter1 | xor | 0| 0| 8| 2| 1| |ap_enable_reg_pp1_iter1 | xor | 0| 0| 8| 2| 1| |ap_enable_reg_pp2_iter1 | xor | 0| 0| 8| 2| 1| |ap_enable_reg_pp3_iter1 | xor | 0| 0| 8| 2| 1| +-----------------------------------+----------+-------+---+----+------------+------------+ |Total | | 12| 0|2251| 262| 2019| +-----------------------------------+----------+-------+---+----+------------+------------+ * Multiplexer: +-----------------------------+-----+-----------+-----+-----------+ | Name | LUT | Input Size| Bits| Total Bits| +-----------------------------+-----+-----------+-----+-----------+ |ap_NS_fsm | 125| 27| 1| 27| |ap_enable_reg_pp0_iter1 | 9| 2| 1| 2| |ap_enable_reg_pp0_iter2 | 9| 2| 1| 2| |ap_enable_reg_pp1_iter1 | 9| 2| 1| 2| |ap_enable_reg_pp1_iter2 | 9| 2| 1| 2| |ap_enable_reg_pp2_iter1 | 9| 2| 1| 2| |ap_enable_reg_pp2_iter2 | 9| 2| 1| 2| |ap_enable_reg_pp3_iter1 | 15| 3| 1| 3| |ap_sig_ioackin_gmem_ARREADY | 9| 2| 1| 2| |ap_sig_ioackin_gmem_AWREADY | 9| 2| 1| 2| |ap_sig_ioackin_gmem_WREADY | 9| 2| 1| 2| |gmem_ARADDR | 15| 3| 32| 96| |gmem_blk_n_AR | 9| 2| 1| 2| |gmem_blk_n_AW | 9| 2| 1| 2| |gmem_blk_n_B | 9| 2| 1| 2| |gmem_blk_n_R | 9| 2| 1| 2| |gmem_blk_n_W | 9| 2| 1| 2| |i_reg_488 | 9| 2| 4| 8| |indvar1_reg_499 | 9| 2| 4| 8| |indvar7_reg_381 | 9| 2| 4| 8| |indvar_reg_274 | 9| 2| 4| 8| +-----------------------------+-----+-----------+-----+-----------+ |Total | 317| 69| 64| 186| +-----------------------------+-----+-----------+-----+-----------+ * Register: +----------------------------------------+----+----+-----+-----------+ | Name | FF | LUT| Bits| Const Bits| +----------------------------------------+----+----+-----+-----------+ |A1_reg_1336 | 30| 0| 30| 0| |B3_reg_1331 | 30| 0| 30| 0| |ap_CS_fsm | 26| 0| 26| 0| |ap_enable_reg_pp0_iter0 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter1 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter2 | 1| 0| 1| 0| |ap_enable_reg_pp1_iter0 | 1| 0| 1| 0| |ap_enable_reg_pp1_iter1 | 1| 0| 1| 0| |ap_enable_reg_pp1_iter2 | 1| 0| 1| 0| |ap_enable_reg_pp2_iter0 | 1| 0| 1| 0| |ap_enable_reg_pp2_iter1 | 1| 0| 1| 0| |ap_enable_reg_pp2_iter2 | 1| 0| 1| 0| |ap_enable_reg_pp3_iter0 | 1| 0| 1| 0| |ap_enable_reg_pp3_iter1 | 1| 0| 1| 0| |ap_reg_ioackin_gmem_ARREADY | 1| 0| 1| 0| |ap_reg_ioackin_gmem_AWREADY | 1| 0| 1| 0| |ap_reg_ioackin_gmem_WREADY | 1| 0| 1| 0| |ap_reg_pp0_iter1_exitcond1_reg_1359 | 1| 0| 1| 0| |ap_reg_pp0_iter1_newIndex84_t_reg_1378 | 2| 0| 2| 0| |ap_reg_pp0_iter1_tmp_reg_1368 | 1| 0| 1| 0| |ap_reg_pp1_iter1_exitcond9_reg_1437 | 1| 0| 1| 0| |ap_reg_pp1_iter1_newIndex58_t_reg_1456 | 2| 0| 2| 0| |ap_reg_pp1_iter1_tmp_14_reg_1446 | 1| 0| 1| 0| |ap_reg_pp2_iter1_cond_reg_1555 | 1| 0| 1| 0| |ap_reg_pp2_iter1_exitcond_reg_1515 | 1| 0| 1| 0| |ap_reg_pp2_iter1_newIndex78_t_reg_1519 | 2| 0| 2| 0| |cond_reg_1555 | 1| 0| 1| 0| |exitcond1_reg_1359 | 1| 0| 1| 0| |exitcond2_reg_1644 | 1| 0| 1| 0| |exitcond9_reg_1437 | 1| 0| 1| 0| |exitcond_reg_1515 | 1| 0| 1| 0| |gmem_addr_1_reg_1353 | 30| 0| 32| 2| |gmem_addr_reg_1347 | 30| 0| 32| 2| |i_reg_488 | 4| 0| 4| 0| |indvar1_reg_499 | 4| 0| 4| 0| |indvar7_reg_381 | 4| 0| 4| 0| |indvar_reg_274 | 4| 0| 4| 0| |newIndex58_t_reg_1456 | 2| 0| 2| 0| |newIndex78_t_reg_1519 | 2| 0| 2| 0| |newIndex84_t_reg_1378 | 2| 0| 2| 0| |result5_reg_1326 | 30| 0| 30| 0| |tempA_0_2_s_reg_238 | 32| 0| 32| 0| |tempA_0_3_s_reg_226 | 32| 0| 32| 0| |tempA_1_2_s_reg_190 | 32| 0| 32| 0| |tempA_1_3_10_reg_214 | 32| 0| 32| 0| |tempA_1_3_12_reg_250 | 32| 0| 32| 0| |tempA_1_3_13_reg_262 | 32| 0| 32| 0| |tempA_1_3_23_reg_1385 | 32| 0| 32| 0| |tempA_1_3_7_reg_202 | 32| 0| 32| 0| |tempA_1_3_s_reg_178 | 32| 0| 32| 0| |tempB_0_2_s_reg_345 | 32| 0| 32| 0| |tempB_0_3_s_reg_333 | 32| 0| 32| 0| |tempB_1_2_s_reg_297 | 32| 0| 32| 0| |tempB_1_3_10_reg_321 | 32| 0| 32| 0| |tempB_1_3_12_reg_357 | 32| 0| 32| 0| |tempB_1_3_13_reg_369 | 32| 0| 32| 0| |tempB_1_3_23_reg_1463 | 32| 0| 32| 0| |tempB_1_3_7_reg_309 | 32| 0| 32| 0| |tempB_1_3_s_reg_285 | 32| 0| 32| 0| |tempResult_0_1_reg_1592 | 32| 0| 32| 0| |tempResult_0_1_s_reg_464 | 32| 0| 32| 0| |tempResult_0_2_s_reg_452 | 32| 0| 32| 0| |tempResult_0_3_11_reg_1578 | 32| 0| 32| 0| |tempResult_0_3_7_reg_476 | 32| 0| 32| 0| |tempResult_0_3_reg_440 | 32| 0| 32| 0| |tempResult_1_1_reg_1598 | 32| 0| 32| 0| |tempResult_1_1_s_reg_416 | 32| 0| 32| 0| |tempResult_1_2_s_reg_404 | 32| 0| 32| 0| |tempResult_1_3_11_reg_1585 | 32| 0| 32| 0| |tempResult_1_3_7_reg_428 | 32| 0| 32| 0| |tempResult_1_3_reg_392 | 32| 0| 32| 0| |tempResult_load_phi_reg_1653 | 32| 0| 32| 0| |tmp_10_reg_1568 | 32| 0| 32| 0| |tmp_14_reg_1446 | 1| 0| 1| 0| |tmp_3_reg_1525 | 32| 0| 32| 0| |tmp_4_reg_1530 | 32| 0| 32| 0| |tmp_6_reg_1535 | 32| 0| 32| 0| |tmp_7_reg_1540 | 32| 0| 32| 0| |tmp_8_reg_1545 | 32| 0| 32| 0| |tmp_9_reg_1550 | 32| 0| 32| 0| |tmp_reg_1368 | 1| 0| 1| 0| |tmp_s_reg_1563 | 32| 0| 32| 0| +----------------------------------------+----+----+-----+-----------+ |Total |1479| 0| 1483| 4| +----------------------------------------+----+----+-----+-----------+ ================================================================ == Interface ================================================================ * Summary: +------------------------+-----+-----+------------+--------------+--------------+ | RTL Ports | Dir | Bits| Protocol | Source Object| C Type | +------------------------+-----+-----+------------+--------------+--------------+ |s_axi_AXILiteS_AWVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_AWREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_AWADDR | in | 6| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WDATA | in | 32| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WSTRB | in | 4| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARADDR | in | 6| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RVALID | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RREADY | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RDATA | out | 32| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RRESP | out | 2| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BVALID | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BREADY | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BRESP | out | 2| s_axi | AXILiteS | scalar | |ap_clk | in | 1| ap_ctrl_hs | vector_mult | return value | |ap_rst_n | in | 1| ap_ctrl_hs | vector_mult | return value | |interrupt | out | 1| ap_ctrl_hs | vector_mult | return value | |m_axi_gmem_AWVALID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_AWREADY | in | 1| m_axi | gmem | pointer | |m_axi_gmem_AWADDR | out | 32| m_axi | gmem | pointer | |m_axi_gmem_AWID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_AWLEN | out | 8| m_axi | gmem | pointer | |m_axi_gmem_AWSIZE | out | 3| m_axi | gmem | pointer | |m_axi_gmem_AWBURST | out | 2| m_axi | gmem | pointer | |m_axi_gmem_AWLOCK | out | 2| m_axi | gmem | pointer | |m_axi_gmem_AWCACHE | out | 4| m_axi | gmem | pointer | |m_axi_gmem_AWPROT | out | 3| m_axi | gmem | pointer | |m_axi_gmem_AWQOS | out | 4| m_axi | gmem | pointer | |m_axi_gmem_AWREGION | out | 4| m_axi | gmem | pointer | |m_axi_gmem_AWUSER | out | 1| m_axi | gmem | pointer | |m_axi_gmem_WVALID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_WREADY | in | 1| m_axi | gmem | pointer | |m_axi_gmem_WDATA | out | 32| m_axi | gmem | pointer | |m_axi_gmem_WSTRB | out | 4| m_axi | gmem | pointer | |m_axi_gmem_WLAST | out | 1| m_axi | gmem | pointer | |m_axi_gmem_WID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_WUSER | out | 1| m_axi | gmem | pointer | |m_axi_gmem_ARVALID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_ARREADY | in | 1| m_axi | gmem | pointer | |m_axi_gmem_ARADDR | out | 32| m_axi | gmem | pointer | |m_axi_gmem_ARID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_ARLEN | out | 8| m_axi | gmem | pointer | |m_axi_gmem_ARSIZE | out | 3| m_axi | gmem | pointer | |m_axi_gmem_ARBURST | out | 2| m_axi | gmem | pointer | |m_axi_gmem_ARLOCK | out | 2| m_axi | gmem | pointer | |m_axi_gmem_ARCACHE | out | 4| m_axi | gmem | pointer | |m_axi_gmem_ARPROT | out | 3| m_axi | gmem | pointer | |m_axi_gmem_ARQOS | out | 4| m_axi | gmem | pointer | |m_axi_gmem_ARREGION | out | 4| m_axi | gmem | pointer | |m_axi_gmem_ARUSER | out | 1| m_axi | gmem | pointer | |m_axi_gmem_RVALID | in | 1| m_axi | gmem | pointer | |m_axi_gmem_RREADY | out | 1| m_axi | gmem | pointer | |m_axi_gmem_RDATA | in | 32| m_axi | gmem | pointer | |m_axi_gmem_RLAST | in | 1| m_axi | gmem | pointer | |m_axi_gmem_RID | in | 1| m_axi | gmem | pointer | |m_axi_gmem_RUSER | in | 1| m_axi | gmem | pointer | |m_axi_gmem_RRESP | in | 2| m_axi | gmem | pointer | |m_axi_gmem_BVALID | in | 1| m_axi | gmem | pointer | |m_axi_gmem_BREADY | out | 1| m_axi | gmem | pointer | |m_axi_gmem_BRESP | in | 2| m_axi | gmem | pointer | |m_axi_gmem_BID | in | 1| m_axi | gmem | pointer | |m_axi_gmem_BUSER | in | 1| m_axi | gmem | pointer | +------------------------+-----+-----+------------+--------------+--------------+