================================================================ == Vivado HLS Report for 'vector_mult' ================================================================ * Date: Mon Mar 19 10:54:33 2018 * Version: 2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017) * Project: vector_mult * Solution: solution3 * Product family: zynq * Target device: xc7z020clg484-1 ================================================================ == Performance Estimates ================================================================ + Timing (ns): * Summary: +--------+-------+----------+------------+ | Clock | Target| Estimated| Uncertainty| +--------+-------+----------+------------+ |ap_clk | 10.00| 8.75| 1.25| +--------+-------+----------+------------+ + Latency (clock cycles): * Summary: +-----+-----+-----+-----+---------+ | Latency | Interval | Pipeline| | min | max | min | max | Type | +-----+-----+-----+-----+---------+ | 54| 54| 54| 54| none | +-----+-----+-----+-----+---------+ + Detail: * Instance: N/A * Loop: +--------------------------------+-----+-----+----------+-----------+-----------+------+----------+ | | Latency | Iteration| Initiation Interval | Trip | | | Loop Name | min | max | Latency | achieved | target | Count| Pipelined| +--------------------------------+-----+-----+----------+-----------+-----------+------+----------+ |- memcpy.tempA.A | 9| 9| 3| 1| 1| 8| yes | |- memcpy.tempB.B | 9| 9| 3| 1| 1| 8| yes | |- vector_mult_loop | 3| 3| 3| 1| 1| 2| yes | |- memcpy.result.tempResult.gep | 8| 8| 2| 1| 1| 8| yes | +--------------------------------+-----+-----+----------+-----------+-----------+------+----------+ ============================================================ + Verbose Summary: Synthesis Manager ============================================================ InlineROM: 1 ExposeGlobal: 0 ============================================================ + Verbose Summary: CDFG Model ============================================================ IsTopModel: 1 ResetActiveHigh: 1 IsCombinational: 0 IsDatapathOnly: 0 HasWiredReturn: 1 HasMFsm: 0 HasVarLatency: 1 IsPipeline: 0 IsRtlPipelined: 0 IsInstanceOverlapped: 0 IsDontTouch: 0 HasImplIP: 0 IsGatedGlobalClock: 0 + Individual pipeline summary: * Pipeline-0: initiation interval (II) = 1, depth = 3 * Pipeline-1: initiation interval (II) = 1, depth = 3 * Pipeline-2: initiation interval (II) = 1, depth = 3 * Pipeline-3: initiation interval (II) = 1, depth = 2 ============================================================ + Verbose Summary: Schedule ============================================================ * Number of FSM states : 33 * Pipeline : 4 Pipeline-0 : II = 1, D = 3, States = { 9 10 11 } Pipeline-1 : II = 1, D = 3, States = { 19 20 21 } Pipeline-2 : II = 1, D = 3, States = { 23 24 25 } Pipeline-3 : II = 1, D = 2, States = { 27 28 } * Dataflow Pipeline: 0 * FSM state transitions: 1 --> 2 / true 2 --> 3 / true 3 --> 4 / true 4 --> 5 / true 5 --> 6 / true 6 --> 7 / true 7 --> 8 / true 8 --> 9 / true 9 --> 12 / (exitcond1) 10 / (!exitcond1) 10 --> 11 / true 11 --> 9 / true 12 --> 13 / true 13 --> 14 / true 14 --> 15 / true 15 --> 16 / true 16 --> 17 / true 17 --> 18 / true 18 --> 19 / true 19 --> 22 / (exitcond9) 20 / (!exitcond9) 20 --> 21 / true 21 --> 19 / true 22 --> 23 / true 23 --> 26 / (exitcond) 24 / (!exitcond) 24 --> 25 / true 25 --> 23 / true 26 --> 27 / true 27 --> 29 / (exitcond2) 28 / (!exitcond2) 28 --> 27 / true 29 --> 30 / true 30 --> 31 / true 31 --> 32 / true 32 --> 33 / true 33 --> * FSM state operations: : 1.00ns ST_1 : Operation 34 [1/1] (1.00ns) ---> "%result_read = call i32 @_ssdm_op_Read.s_axilite.i32(i32 %result)" ---> Core 10 's_axilite' ST_1 : Operation 35 [1/1] (1.00ns) ---> "%B_read = call i32 @_ssdm_op_Read.s_axilite.i32(i32 %B)" ---> Core 10 's_axilite' ST_1 : Operation 36 [1/1] (1.00ns) ---> "%A_read = call i32 @_ssdm_op_Read.s_axilite.i32(i32 %A)" ---> Core 10 's_axilite' ST_1 : Operation 37 [1/1] (0.00ns) ---> "%result5 = call i30 @_ssdm_op_PartSelect.i30.i32.i32.i32(i32 %result_read, i32 2, i32 31)" ST_1 : Operation 38 [1/1] (0.00ns) ---> "%B3 = call i30 @_ssdm_op_PartSelect.i30.i32.i32.i32(i32 %B_read, i32 2, i32 31)" ST_1 : Operation 39 [1/1] (0.00ns) ---> "%A1 = call i30 @_ssdm_op_PartSelect.i30.i32.i32.i32(i32 %A_read, i32 2, i32 31)" : 8.75ns ST_2 : Operation 40 [1/1] (0.00ns) ---> "%tmp_13 = zext i30 %A1 to i64" ST_2 : Operation 41 [1/1] (0.00ns) ---> "%gmem_addr_2 = getelementptr i32* %gmem, i64 %tmp_13" ST_2 : Operation 42 [7/7] (8.75ns) ---> "%gmem_addr_2_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 8)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' : 8.75ns ST_3 : Operation 43 [6/7] (8.75ns) ---> "%gmem_addr_2_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 8)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' : 8.75ns ST_4 : Operation 44 [5/7] (8.75ns) ---> "%gmem_addr_2_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 8)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' : 8.75ns ST_5 : Operation 45 [4/7] (8.75ns) ---> "%gmem_addr_2_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 8)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' : 8.75ns ST_6 : Operation 46 [3/7] (8.75ns) ---> "%gmem_addr_2_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 8)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' : 8.75ns ST_7 : Operation 47 [2/7] (8.75ns) ---> "%gmem_addr_2_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 8)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' : 8.75ns ST_8 : Operation 48 [1/1] (0.00ns) ---> "%tmp_1 = zext i30 %result5 to i64" ST_8 : Operation 49 [1/1] (0.00ns) ---> "%gmem_addr = getelementptr i32* %gmem, i64 %tmp_1" ST_8 : Operation 50 [1/1] (0.00ns) ---> "%tmp_5 = zext i30 %B3 to i64" ST_8 : Operation 51 [1/1] (0.00ns) ---> "%gmem_addr_1 = getelementptr i32* %gmem, i64 %tmp_5" ST_8 : Operation 52 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecBitsMap(i32* %gmem), !map !11" ST_8 : Operation 53 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecTopModule([12 x i8]* @vector_mult_str) nounwind" ST_8 : Operation 54 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32 0, [10 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1, [1 x i8]* @p_str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1) nounwind" [vector_mult/vector_mult.cpp:5] ST_8 : Operation 55 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32 %result, [10 x i8]* @mode5, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @bundle6, [6 x i8]* @p_str3, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)" ST_8 : Operation 56 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32 %B, [10 x i8]* @mode3, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @bundle4, [6 x i8]* @p_str3, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)" ST_8 : Operation 57 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32* %gmem, [6 x i8]* @p_str2, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @p_str1, [6 x i8]* @p_str3, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)" ST_8 : Operation 58 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32 %A, [10 x i8]* @mode, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @bundle, [6 x i8]* @p_str3, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)" ST_8 : Operation 59 [1/7] (8.75ns) ---> "%gmem_addr_2_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 8)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' ST_8 : Operation 60 [1/1] (1.76ns) ---> "br label %burst.rd.header" : 2.23ns ST_9 : Operation 61 [1/1] (0.00ns) ---> "%tempA_1_3_s = phi i32 [ undef, %0 ], [ %tempA_1_3_1, %burst.rd.body_ifconv ]" ST_9 : Operation 62 [1/1] (0.00ns) ---> "%tempA_1_2_s = phi i32 [ undef, %0 ], [ %tempA_1_3_15, %burst.rd.body_ifconv ]" ST_9 : Operation 63 [1/1] (0.00ns) ---> "%tempA_1_3_7 = phi i32 [ undef, %0 ], [ %tempA_1_3_16, %burst.rd.body_ifconv ]" ST_9 : Operation 64 [1/1] (0.00ns) ---> "%tempA_1_3_10 = phi i32 [ undef, %0 ], [ %tempA_1_3_17, %burst.rd.body_ifconv ]" ST_9 : Operation 65 [1/1] (0.00ns) ---> "%tempA_0_3_s = phi i32 [ undef, %0 ], [ %tempA_1_3_18, %burst.rd.body_ifconv ]" ST_9 : Operation 66 [1/1] (0.00ns) ---> "%tempA_0_2_s = phi i32 [ undef, %0 ], [ %tempA_1_3_19, %burst.rd.body_ifconv ]" ST_9 : Operation 67 [1/1] (0.00ns) ---> "%tempA_1_3_12 = phi i32 [ undef, %0 ], [ %tempA_1_3_20, %burst.rd.body_ifconv ]" ST_9 : Operation 68 [1/1] (0.00ns) ---> "%tempA_1_3_13 = phi i32 [ undef, %0 ], [ %tempA_1_3_21, %burst.rd.body_ifconv ]" ST_9 : Operation 69 [1/1] (0.00ns) ---> "%indvar = phi i4 [ 0, %0 ], [ %indvar_next, %burst.rd.body_ifconv ]" ST_9 : Operation 70 [1/1] (1.30ns) ---> "%exitcond1 = icmp eq i4 %indvar, -8" ---> Core 25 'Cmp' ST_9 : Operation 71 [1/1] (1.73ns) ---> "%indvar_next = add i4 %indvar, 1" ---> Core 14 'AddSub' ST_9 : Operation 72 [1/1] (0.00ns) ---> "br i1 %exitcond1, label %burst.rd.header5.preheader, label %burst.rd.body_ifconv" ST_9 : Operation 73 [1/1] (0.00ns) ---> "%tmp = trunc i4 %indvar to i1" ST_9 : Operation 74 [1/1] (0.00ns) ---> "%newIndex84_t = call i2 @_ssdm_op_PartSelect.i2.i4.i32.i32(i4 %indvar, i32 1, i32 2)" : 8.75ns ST_10 : Operation 75 [1/1] (8.75ns) ---> "%tempA_1_3_23 = call i32 @_ssdm_op_Read.m_axi.i32P(i32* %gmem_addr_2)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' : 4.63ns ST_11 : Operation 76 [1/1] (0.00ns) ---> "%empty = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 8, i64 8, i64 8) nounwind" ST_11 : Operation 77 [1/1] (0.00ns) ---> "%burstread_rbegin = call i32 (...)* @_ssdm_op_SpecRegionBegin([17 x i8]* @burstread_OC_region_s) nounwind" ST_11 : Operation 78 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecPipeline(i32 1, i32 1, i32 1, i32 0, [1 x i8]* @p_str6)" ST_11 : Operation 79 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecLoopName([15 x i8]* @memcpy_OC_tempA_OC_A)" ST_11 : Operation 80 [1/1] (0.95ns) ---> "%sel_tmp = icmp eq i2 %newIndex84_t, -2" ---> Core 25 'Cmp' ST_11 : Operation 81 [1/1] (0.00ns) (grouped into LUT with out node tempA_1_3_3) ---> "%tempA_1_3 = select i1 %sel_tmp, i32 %tempA_1_3_s, i32 %tempA_1_3_23" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 82 [1/1] (0.95ns) ---> "%sel_tmp2 = icmp eq i2 %newIndex84_t, 1" ---> Core 25 'Cmp' ST_11 : Operation 83 [1/1] (1.37ns) (out node of the LUT) ---> "%tempA_1_3_3 = select i1 %sel_tmp2, i32 %tempA_1_3_s, i32 %tempA_1_3" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 84 [1/1] (0.95ns) ---> "%sel_tmp4 = icmp eq i2 %newIndex84_t, 0" ---> Core 25 'Cmp' ST_11 : Operation 85 [1/1] (0.00ns) (grouped into LUT with out node tempA_1_3_1) ---> "%tempA_1_3_2 = select i1 %sel_tmp4, i32 %tempA_1_3_s, i32 %tempA_1_3_3" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 86 [1/1] (0.00ns) (grouped into LUT with out node tempA_1_3_5) ---> "%tempA_1_3_4 = select i1 %sel_tmp, i32 %tempA_1_3_23, i32 %tempA_1_2_s" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 87 [1/1] (1.37ns) (out node of the LUT) ---> "%tempA_1_3_5 = select i1 %sel_tmp2, i32 %tempA_1_2_s, i32 %tempA_1_3_4" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 88 [1/1] (0.00ns) (grouped into LUT with out node tempA_1_3_15) ---> "%tempA_1_3_6 = select i1 %sel_tmp4, i32 %tempA_1_2_s, i32 %tempA_1_3_5" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 89 [1/1] (0.00ns) (grouped into LUT with out node tempA_1_3_9) ---> "%tempA_1_3_8 = select i1 %sel_tmp2, i32 %tempA_1_3_23, i32 %tempA_1_3_7" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 90 [1/1] (1.37ns) (out node of the LUT) ---> "%tempA_1_3_9 = select i1 %sel_tmp4, i32 %tempA_1_3_7, i32 %tempA_1_3_8" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 91 [1/1] (0.00ns) (grouped into LUT with out node tempA_1_3_17) ---> "%tempA_1_3_11 = select i1 %sel_tmp4, i32 %tempA_1_3_23, i32 %tempA_1_3_10" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 92 [1/1] (0.00ns) (grouped into LUT with out node tempA_1_3_21) ---> "%tempA_1_3_14 = select i1 %sel_tmp4, i32 %tempA_1_3_23, i32 %tempA_1_3_13" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 93 [1/1] (1.37ns) (out node of the LUT) ---> "%tempA_1_3_1 = select i1 %tmp, i32 %tempA_1_3_2, i32 %tempA_1_3_s" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 94 [1/1] (1.37ns) (out node of the LUT) ---> "%tempA_1_3_15 = select i1 %tmp, i32 %tempA_1_3_6, i32 %tempA_1_2_s" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 95 [1/1] (1.37ns) (out node of the LUT) ---> "%tempA_1_3_16 = select i1 %tmp, i32 %tempA_1_3_9, i32 %tempA_1_3_7" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 96 [1/1] (1.37ns) (out node of the LUT) ---> "%tempA_1_3_17 = select i1 %tmp, i32 %tempA_1_3_11, i32 %tempA_1_3_10" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 97 [1/1] (0.93ns) ---> "%or_cond = or i1 %tmp, %sel_tmp4" ---> Core 27 'LogicGate' ST_11 : Operation 98 [1/1] (0.00ns) (grouped into LUT with out node or_cond2) ---> "%or_cond1 = or i1 %sel_tmp2, %sel_tmp" ---> Core 27 'LogicGate' ST_11 : Operation 99 [1/1] (0.93ns) (out node of the LUT) ---> "%or_cond2 = or i1 %or_cond, %or_cond1" ---> Core 27 'LogicGate' ST_11 : Operation 100 [1/1] (1.37ns) ---> "%tempA_1_3_18 = select i1 %or_cond2, i32 %tempA_0_3_s, i32 %tempA_1_3_23" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 101 [1/1] (0.00ns) (grouped into LUT with out node newSel1) ---> "%newSel = select i1 %sel_tmp2, i32 %tempA_0_2_s, i32 %tempA_1_3_23" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 102 [1/1] (1.37ns) (out node of the LUT) ---> "%newSel1 = select i1 %or_cond, i32 %tempA_0_2_s, i32 %newSel" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 103 [1/1] (1.37ns) (out node of the LUT) ---> "%tempA_1_3_19 = select i1 %or_cond2, i32 %newSel1, i32 %tempA_0_2_s" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 104 [1/1] (0.00ns) (grouped into LUT with out node tempA_1_3_20) ---> "%newSel3 = select i1 %sel_tmp2, i32 %tempA_1_3_23, i32 %tempA_1_3_12" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 105 [1/1] (1.37ns) (out node of the LUT) ---> "%tempA_1_3_20 = select i1 %or_cond, i32 %tempA_1_3_12, i32 %newSel3" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 106 [1/1] (1.37ns) (out node of the LUT) ---> "%tempA_1_3_21 = select i1 %tmp, i32 %tempA_1_3_13, i32 %tempA_1_3_14" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 107 [1/1] (0.00ns) ---> "%burstread_rend = call i32 (...)* @_ssdm_op_SpecRegionEnd([17 x i8]* @burstread_OC_region_s, i32 %burstread_rbegin) nounwind" ST_11 : Operation 108 [1/1] (0.00ns) ---> "br label %burst.rd.header" : 8.75ns ST_12 : Operation 109 [7/7] (8.75ns) ---> "%gmem_addr_1_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 8)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' : 8.75ns ST_13 : Operation 110 [6/7] (8.75ns) ---> "%gmem_addr_1_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 8)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' : 8.75ns ST_14 : Operation 111 [5/7] (8.75ns) ---> "%gmem_addr_1_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 8)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' : 8.75ns ST_15 : Operation 112 [4/7] (8.75ns) ---> "%gmem_addr_1_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 8)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' : 8.75ns ST_16 : Operation 113 [3/7] (8.75ns) ---> "%gmem_addr_1_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 8)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' : 8.75ns ST_17 : Operation 114 [2/7] (8.75ns) ---> "%gmem_addr_1_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 8)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' : 8.75ns ST_18 : Operation 115 [1/7] (8.75ns) ---> "%gmem_addr_1_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 8)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' ST_18 : Operation 116 [1/1] (1.76ns) ---> "br label %burst.rd.header5" : 2.23ns ST_19 : Operation 117 [1/1] (0.00ns) ---> "%tempB_1_3_s = phi i32 [ %tempB_1_3_1, %burst.rd.body6_ifconv ], [ undef, %burst.rd.header5.preheader ]" ST_19 : Operation 118 [1/1] (0.00ns) ---> "%tempB_1_2_s = phi i32 [ %tempB_1_3_15, %burst.rd.body6_ifconv ], [ undef, %burst.rd.header5.preheader ]" ST_19 : Operation 119 [1/1] (0.00ns) ---> "%tempB_1_3_7 = phi i32 [ %tempB_1_3_16, %burst.rd.body6_ifconv ], [ undef, %burst.rd.header5.preheader ]" ST_19 : Operation 120 [1/1] (0.00ns) ---> "%tempB_1_3_10 = phi i32 [ %tempB_1_3_17, %burst.rd.body6_ifconv ], [ undef, %burst.rd.header5.preheader ]" ST_19 : Operation 121 [1/1] (0.00ns) ---> "%tempB_0_3_s = phi i32 [ %tempB_1_3_18, %burst.rd.body6_ifconv ], [ undef, %burst.rd.header5.preheader ]" ST_19 : Operation 122 [1/1] (0.00ns) ---> "%tempB_0_2_s = phi i32 [ %tempB_1_3_19, %burst.rd.body6_ifconv ], [ undef, %burst.rd.header5.preheader ]" ST_19 : Operation 123 [1/1] (0.00ns) ---> "%tempB_1_3_12 = phi i32 [ %tempB_1_3_20, %burst.rd.body6_ifconv ], [ undef, %burst.rd.header5.preheader ]" ST_19 : Operation 124 [1/1] (0.00ns) ---> "%tempB_1_3_13 = phi i32 [ %tempB_1_3_21, %burst.rd.body6_ifconv ], [ undef, %burst.rd.header5.preheader ]" ST_19 : Operation 125 [1/1] (0.00ns) ---> "%indvar7 = phi i4 [ %indvar_next8, %burst.rd.body6_ifconv ], [ 0, %burst.rd.header5.preheader ]" ST_19 : Operation 126 [1/1] (1.30ns) ---> "%exitcond9 = icmp eq i4 %indvar7, -8" ---> Core 25 'Cmp' ST_19 : Operation 127 [1/1] (1.73ns) ---> "%indvar_next8 = add i4 %indvar7, 1" ---> Core 14 'AddSub' ST_19 : Operation 128 [1/1] (0.00ns) ---> "br i1 %exitcond9, label %burst.rd.end4.0.preheader, label %burst.rd.body6_ifconv" ST_19 : Operation 129 [1/1] (0.00ns) ---> "%tmp_14 = trunc i4 %indvar7 to i1" ST_19 : Operation 130 [1/1] (0.00ns) ---> "%newIndex58_t = call i2 @_ssdm_op_PartSelect.i2.i4.i32.i32(i4 %indvar7, i32 1, i32 2)" : 8.75ns ST_20 : Operation 131 [1/1] (8.75ns) ---> "%tempB_1_3_23 = call i32 @_ssdm_op_Read.m_axi.i32P(i32* %gmem_addr_1)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' : 4.63ns ST_21 : Operation 132 [1/1] (0.00ns) ---> "%empty_6 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 8, i64 8, i64 8) nounwind" ST_21 : Operation 133 [1/1] (0.00ns) ---> "%burstread_rbegin1 = call i32 (...)* @_ssdm_op_SpecRegionBegin([17 x i8]* @burstread_OC_region_s) nounwind" ST_21 : Operation 134 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecPipeline(i32 1, i32 1, i32 1, i32 0, [1 x i8]* @p_str7)" ST_21 : Operation 135 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecLoopName([15 x i8]* @memcpy_OC_tempB_OC_B)" ST_21 : Operation 136 [1/1] (0.95ns) ---> "%sel_tmp8 = icmp eq i2 %newIndex58_t, -2" ---> Core 25 'Cmp' ST_21 : Operation 137 [1/1] (0.00ns) (grouped into LUT with out node tempB_1_3_3) ---> "%tempB_1_3 = select i1 %sel_tmp8, i32 %tempB_1_3_s, i32 %tempB_1_3_23" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 138 [1/1] (0.95ns) ---> "%sel_tmp1 = icmp eq i2 %newIndex58_t, 1" ---> Core 25 'Cmp' ST_21 : Operation 139 [1/1] (1.37ns) (out node of the LUT) ---> "%tempB_1_3_3 = select i1 %sel_tmp1, i32 %tempB_1_3_s, i32 %tempB_1_3" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 140 [1/1] (0.95ns) ---> "%sel_tmp3 = icmp eq i2 %newIndex58_t, 0" ---> Core 25 'Cmp' ST_21 : Operation 141 [1/1] (0.00ns) (grouped into LUT with out node tempB_1_3_1) ---> "%tempB_1_3_2 = select i1 %sel_tmp3, i32 %tempB_1_3_s, i32 %tempB_1_3_3" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 142 [1/1] (0.00ns) (grouped into LUT with out node tempB_1_3_5) ---> "%tempB_1_3_4 = select i1 %sel_tmp8, i32 %tempB_1_3_23, i32 %tempB_1_2_s" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 143 [1/1] (1.37ns) (out node of the LUT) ---> "%tempB_1_3_5 = select i1 %sel_tmp1, i32 %tempB_1_2_s, i32 %tempB_1_3_4" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 144 [1/1] (0.00ns) (grouped into LUT with out node tempB_1_3_15) ---> "%tempB_1_3_6 = select i1 %sel_tmp3, i32 %tempB_1_2_s, i32 %tempB_1_3_5" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 145 [1/1] (0.00ns) (grouped into LUT with out node tempB_1_3_9) ---> "%tempB_1_3_8 = select i1 %sel_tmp1, i32 %tempB_1_3_23, i32 %tempB_1_3_7" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 146 [1/1] (1.37ns) (out node of the LUT) ---> "%tempB_1_3_9 = select i1 %sel_tmp3, i32 %tempB_1_3_7, i32 %tempB_1_3_8" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 147 [1/1] (0.00ns) (grouped into LUT with out node tempB_1_3_17) ---> "%tempB_1_3_11 = select i1 %sel_tmp3, i32 %tempB_1_3_23, i32 %tempB_1_3_10" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 148 [1/1] (0.00ns) (grouped into LUT with out node tempB_1_3_21) ---> "%tempB_1_3_14 = select i1 %sel_tmp3, i32 %tempB_1_3_23, i32 %tempB_1_3_13" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 149 [1/1] (1.37ns) (out node of the LUT) ---> "%tempB_1_3_1 = select i1 %tmp_14, i32 %tempB_1_3_2, i32 %tempB_1_3_s" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 150 [1/1] (1.37ns) (out node of the LUT) ---> "%tempB_1_3_15 = select i1 %tmp_14, i32 %tempB_1_3_6, i32 %tempB_1_2_s" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 151 [1/1] (1.37ns) (out node of the LUT) ---> "%tempB_1_3_16 = select i1 %tmp_14, i32 %tempB_1_3_9, i32 %tempB_1_3_7" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 152 [1/1] (1.37ns) (out node of the LUT) ---> "%tempB_1_3_17 = select i1 %tmp_14, i32 %tempB_1_3_11, i32 %tempB_1_3_10" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 153 [1/1] (0.93ns) ---> "%or_cond7 = or i1 %tmp_14, %sel_tmp3" ---> Core 27 'LogicGate' ST_21 : Operation 154 [1/1] (0.00ns) (grouped into LUT with out node or_cond9) ---> "%or_cond8 = or i1 %sel_tmp1, %sel_tmp8" ---> Core 27 'LogicGate' ST_21 : Operation 155 [1/1] (0.93ns) (out node of the LUT) ---> "%or_cond9 = or i1 %or_cond7, %or_cond8" ---> Core 27 'LogicGate' ST_21 : Operation 156 [1/1] (1.37ns) ---> "%tempB_1_3_18 = select i1 %or_cond9, i32 %tempB_0_3_s, i32 %tempB_1_3_23" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 157 [1/1] (0.00ns) (grouped into LUT with out node newSel7) ---> "%newSel6 = select i1 %sel_tmp1, i32 %tempB_0_2_s, i32 %tempB_1_3_23" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 158 [1/1] (1.37ns) (out node of the LUT) ---> "%newSel7 = select i1 %or_cond7, i32 %tempB_0_2_s, i32 %newSel6" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 159 [1/1] (1.37ns) (out node of the LUT) ---> "%tempB_1_3_19 = select i1 %or_cond9, i32 %newSel7, i32 %tempB_0_2_s" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 160 [1/1] (0.00ns) (grouped into LUT with out node tempB_1_3_20) ---> "%newSel9 = select i1 %sel_tmp1, i32 %tempB_1_3_23, i32 %tempB_1_3_12" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 161 [1/1] (1.37ns) (out node of the LUT) ---> "%tempB_1_3_20 = select i1 %or_cond7, i32 %tempB_1_3_12, i32 %newSel9" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 162 [1/1] (1.37ns) (out node of the LUT) ---> "%tempB_1_3_21 = select i1 %tmp_14, i32 %tempB_1_3_13, i32 %tempB_1_3_14" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 163 [1/1] (0.00ns) ---> "%burstread_rend12 = call i32 (...)* @_ssdm_op_SpecRegionEnd([17 x i8]* @burstread_OC_region_s, i32 %burstread_rbegin1) nounwind" ST_21 : Operation 164 [1/1] (0.00ns) ---> "br label %burst.rd.header5" : 1.77ns ST_22 : Operation 165 [1/1] (1.76ns) ---> "br label %burst.rd.end4.0" [vector_mult/vector_mult.cpp:8] : 2.23ns ST_23 : Operation 166 [1/1] (0.00ns) ---> "%tempResult_1_3 = phi i32 [ %tempResult_1_3_2, %burst.rd.end4.1_ifconv ], [ undef, %burst.rd.end4.0.preheader ]" ST_23 : Operation 167 [1/1] (0.00ns) ---> "%tempResult_1_2_s = phi i32 [ %tempResult_1_3_6, %burst.rd.end4.1_ifconv ], [ undef, %burst.rd.end4.0.preheader ]" ST_23 : Operation 168 [1/1] (0.00ns) ---> "%tempResult_1_1_s = phi i32 [ %tempResult_1_3_10, %burst.rd.end4.1_ifconv ], [ undef, %burst.rd.end4.0.preheader ]" ST_23 : Operation 169 [1/1] (0.00ns) ---> "%tempResult_1_3_7 = phi i32 [ %tempResult_1_3_8, %burst.rd.end4.1_ifconv ], [ undef, %burst.rd.end4.0.preheader ]" ST_23 : Operation 170 [1/1] (0.00ns) ---> "%tempResult_0_3 = phi i32 [ %tempResult_0_3_2, %burst.rd.end4.1_ifconv ], [ undef, %burst.rd.end4.0.preheader ]" ST_23 : Operation 171 [1/1] (0.00ns) ---> "%tempResult_0_2_s = phi i32 [ %tempResult_0_3_6, %burst.rd.end4.1_ifconv ], [ undef, %burst.rd.end4.0.preheader ]" ST_23 : Operation 172 [1/1] (0.00ns) ---> "%tempResult_0_1_s = phi i32 [ %tempResult_0_3_10, %burst.rd.end4.1_ifconv ], [ undef, %burst.rd.end4.0.preheader ]" ST_23 : Operation 173 [1/1] (0.00ns) ---> "%tempResult_0_3_7 = phi i32 [ %tempResult_0_3_8, %burst.rd.end4.1_ifconv ], [ undef, %burst.rd.end4.0.preheader ]" ST_23 : Operation 174 [1/1] (0.00ns) ---> "%i = phi i4 [ %i_1_3, %burst.rd.end4.1_ifconv ], [ 0, %burst.rd.end4.0.preheader ]" [vector_mult/vector_mult.cpp:8] ST_23 : Operation 175 [1/1] (1.30ns) ---> "%exitcond = icmp eq i4 %i, -8" [vector_mult/vector_mult.cpp:8] ---> Core 25 'Cmp' ST_23 : Operation 176 [1/1] (0.00ns) ---> "br i1 %exitcond, label %burst.wr.header.preheader, label %burst.rd.end4.1_ifconv" [vector_mult/vector_mult.cpp:8] ST_23 : Operation 177 [1/1] (0.00ns) ---> "%newIndex78_t = call i2 @_ssdm_op_PartSelect.i2.i4.i32.i32(i4 %i, i32 1, i32 2)" [vector_mult/vector_mult.cpp:8] ST_23 : Operation 178 [1/1] (1.95ns) ---> "%tmp_3 = call i32 @_ssdm_op_Mux.ap_auto.4i32.i2(i32 %tempA_1_3_13, i32 %tempA_1_3_12, i32 %tempA_0_2_s, i32 %tempA_0_3_s, i2 %newIndex78_t) nounwind" [vector_mult/vector_mult.cpp:6] ---> Core 31 'MuxnS' ST_23 : Operation 179 [1/1] (1.95ns) ---> "%tmp_4 = call i32 @_ssdm_op_Mux.ap_auto.4i32.i2(i32 %tempB_1_3_13, i32 %tempB_1_3_12, i32 %tempB_0_2_s, i32 %tempB_0_3_s, i2 %newIndex78_t) nounwind" [vector_mult/vector_mult.cpp:7] ---> Core 31 'MuxnS' ST_23 : Operation 180 [1/1] (1.95ns) ---> "%tmp_6 = call i32 @_ssdm_op_Mux.ap_auto.4i32.i2(i32 %tempA_1_3_10, i32 %tempA_1_3_7, i32 %tempA_1_2_s, i32 %tempA_1_3_s, i2 %newIndex78_t) nounwind" [vector_mult/vector_mult.cpp:6] ---> Core 31 'MuxnS' ST_23 : Operation 181 [1/1] (1.95ns) ---> "%tmp_7 = call i32 @_ssdm_op_Mux.ap_auto.4i32.i2(i32 %tempB_1_3_10, i32 %tempB_1_3_7, i32 %tempB_1_2_s, i32 %tempB_1_3_s, i2 %newIndex78_t) nounwind" [vector_mult/vector_mult.cpp:7] ---> Core 31 'MuxnS' ST_23 : Operation 182 [1/1] (0.00ns) ---> "%newIndex68_t = or i2 %newIndex78_t, 1" [vector_mult/vector_mult.cpp:8] ST_23 : Operation 183 [1/1] (1.95ns) ---> "%tmp_8 = call i32 @_ssdm_op_Mux.ap_auto.4i32.i2(i32 %tempA_1_3_13, i32 %tempA_1_3_12, i32 %tempA_0_2_s, i32 %tempA_0_3_s, i2 %newIndex68_t) nounwind" [vector_mult/vector_mult.cpp:6] ---> Core 31 'MuxnS' ST_23 : Operation 184 [1/1] (1.95ns) ---> "%tmp_9 = call i32 @_ssdm_op_Mux.ap_auto.4i32.i2(i32 %tempB_1_3_13, i32 %tempB_1_3_12, i32 %tempB_0_2_s, i32 %tempB_0_3_s, i2 %newIndex68_t) nounwind" [vector_mult/vector_mult.cpp:7] ---> Core 31 'MuxnS' ST_23 : Operation 185 [1/1] (0.95ns) ---> "%cond = icmp eq i2 %newIndex68_t, 1" [vector_mult/vector_mult.cpp:9] ---> Core 25 'Cmp' ST_23 : Operation 186 [1/1] (1.95ns) ---> "%tmp_s = call i32 @_ssdm_op_Mux.ap_auto.4i32.i2(i32 %tempA_1_3_10, i32 %tempA_1_3_7, i32 %tempA_1_2_s, i32 %tempA_1_3_s, i2 %newIndex68_t) nounwind" [vector_mult/vector_mult.cpp:6] ---> Core 31 'MuxnS' ST_23 : Operation 187 [1/1] (1.95ns) ---> "%tmp_10 = call i32 @_ssdm_op_Mux.ap_auto.4i32.i2(i32 %tempB_1_3_10, i32 %tempB_1_3_7, i32 %tempB_1_2_s, i32 %tempB_1_3_s, i2 %newIndex68_t) nounwind" [vector_mult/vector_mult.cpp:7] ---> Core 31 'MuxnS' ST_23 : Operation 188 [1/1] (1.73ns) ---> "%i_1_3 = add i4 %i, 4" [vector_mult/vector_mult.cpp:8] ---> Core 14 'AddSub' : 8.51ns ST_24 : Operation 189 [1/1] (8.51ns) ---> "%tempResult_0_3_11 = mul nsw i32 %tmp_4, %tmp_3" [vector_mult/vector_mult.cpp:9] ---> Core 16 'Mul' ST_24 : Operation 190 [1/1] (8.51ns) ---> "%tempResult_1_3_11 = mul nsw i32 %tmp_7, %tmp_6" [vector_mult/vector_mult.cpp:9] ---> Core 16 'Mul' ST_24 : Operation 191 [1/1] (8.51ns) ---> "%tempResult_0_1 = mul nsw i32 %tmp_9, %tmp_8" [vector_mult/vector_mult.cpp:9] ---> Core 16 'Mul' ST_24 : Operation 192 [1/1] (8.51ns) ---> "%tempResult_1_1 = mul nsw i32 %tmp_10, %tmp_s" [vector_mult/vector_mult.cpp:9] ---> Core 16 'Mul' : 3.70ns ST_25 : Operation 193 [1/1] (0.00ns) ---> "%empty_7 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 2, i64 2, i64 2) nounwind" ST_25 : Operation 194 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecLoopName([17 x i8]* @p_str5) nounwind" [vector_mult/vector_mult.cpp:10] ST_25 : Operation 195 [1/1] (0.00ns) ---> "%tmp_2 = call i32 (...)* @_ssdm_op_SpecRegionBegin([17 x i8]* @p_str5) nounwind" [vector_mult/vector_mult.cpp:10] ST_25 : Operation 196 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind" [vector_mult/vector_mult.cpp:10] ST_25 : Operation 197 [1/1] (0.95ns) ---> "%sel_tmp5 = icmp eq i2 %newIndex78_t, -2" [vector_mult/vector_mult.cpp:8] ---> Core 25 'Cmp' ST_25 : Operation 198 [1/1] (0.00ns) (grouped into LUT with out node tempResult_0_3_1) ---> "%tempResult_0_3_4 = select i1 %sel_tmp5, i32 %tempResult_0_3, i32 %tempResult_0_3_11" [vector_mult/vector_mult.cpp:8] ---> Core 26 'Sel' ST_25 : Operation 199 [1/1] (0.95ns) ---> "%sel_tmp6 = icmp eq i2 %newIndex78_t, 0" [vector_mult/vector_mult.cpp:8] ---> Core 25 'Cmp' ST_25 : Operation 200 [1/1] (1.37ns) (out node of the LUT) ---> "%tempResult_0_3_1 = select i1 %sel_tmp6, i32 %tempResult_0_3, i32 %tempResult_0_3_4" [vector_mult/vector_mult.cpp:8] ---> Core 26 'Sel' ST_25 : Operation 201 [1/1] (0.00ns) (grouped into LUT with out node tempResult_0_3_6) ---> "%tempResult_0_3_5 = select i1 %sel_tmp5, i32 %tempResult_0_3_11, i32 %tempResult_0_2_s" [vector_mult/vector_mult.cpp:8] ---> Core 26 'Sel' ST_25 : Operation 202 [1/1] (1.37ns) (out node of the LUT) ---> "%tempResult_0_3_6 = select i1 %sel_tmp6, i32 %tempResult_0_2_s, i32 %tempResult_0_3_5" [vector_mult/vector_mult.cpp:8] ---> Core 26 'Sel' ST_25 : Operation 203 [1/1] (1.37ns) ---> "%tempResult_0_3_8 = select i1 %sel_tmp6, i32 %tempResult_0_3_11, i32 %tempResult_0_3_7" [vector_mult/vector_mult.cpp:8] ---> Core 26 'Sel' ST_25 : Operation 204 [1/1] (0.00ns) ---> "%empty_8 = call i32 (...)* @_ssdm_op_SpecRegionEnd([17 x i8]* @p_str5, i32 %tmp_2) nounwind" [vector_mult/vector_mult.cpp:9] ST_25 : Operation 205 [1/1] (0.00ns) (grouped into LUT with out node tempResult_1_3_1) ---> "%tempResult_1_3_4 = select i1 %sel_tmp5, i32 %tempResult_1_3, i32 %tempResult_1_3_11" [vector_mult/vector_mult.cpp:8] ---> Core 26 'Sel' ST_25 : Operation 206 [1/1] (1.37ns) (out node of the LUT) ---> "%tempResult_1_3_1 = select i1 %sel_tmp6, i32 %tempResult_1_3, i32 %tempResult_1_3_4" [vector_mult/vector_mult.cpp:8] ---> Core 26 'Sel' ST_25 : Operation 207 [1/1] (0.00ns) (grouped into LUT with out node tempResult_1_3_6) ---> "%tempResult_1_3_5 = select i1 %sel_tmp5, i32 %tempResult_1_3_11, i32 %tempResult_1_2_s" [vector_mult/vector_mult.cpp:8] ---> Core 26 'Sel' ST_25 : Operation 208 [1/1] (1.37ns) (out node of the LUT) ---> "%tempResult_1_3_6 = select i1 %sel_tmp6, i32 %tempResult_1_2_s, i32 %tempResult_1_3_5" [vector_mult/vector_mult.cpp:8] ---> Core 26 'Sel' ST_25 : Operation 209 [1/1] (1.37ns) ---> "%tempResult_1_3_8 = select i1 %sel_tmp6, i32 %tempResult_1_3_11, i32 %tempResult_1_3_7" [vector_mult/vector_mult.cpp:8] ---> Core 26 'Sel' ST_25 : Operation 210 [1/1] (1.37ns) (out node of the LUT) ---> "%tempResult_0_3_2 = select i1 %cond, i32 %tempResult_0_3_1, i32 %tempResult_0_1" [vector_mult/vector_mult.cpp:9] ---> Core 26 'Sel' ST_25 : Operation 211 [1/1] (1.37ns) ---> "%tempResult_0_3_10 = select i1 %cond, i32 %tempResult_0_1, i32 %tempResult_0_1_s" [vector_mult/vector_mult.cpp:9] ---> Core 26 'Sel' ST_25 : Operation 212 [1/1] (1.37ns) (out node of the LUT) ---> "%tempResult_1_3_2 = select i1 %cond, i32 %tempResult_1_3_1, i32 %tempResult_1_1" [vector_mult/vector_mult.cpp:9] ---> Core 26 'Sel' ST_25 : Operation 213 [1/1] (1.37ns) ---> "%tempResult_1_3_10 = select i1 %cond, i32 %tempResult_1_1, i32 %tempResult_1_1_s" [vector_mult/vector_mult.cpp:9] ---> Core 26 'Sel' ST_25 : Operation 214 [1/1] (0.00ns) ---> "br label %burst.rd.end4.0" [vector_mult/vector_mult.cpp:8] : 8.75ns ST_26 : Operation 215 [1/1] (8.75ns) ---> "%gmem_addr_wr_req = call i1 @_ssdm_op_WriteReq.m_axi.i32P(i32* %gmem_addr, i32 8)" [vector_mult/vector_mult.cpp:10] ---> Core 9 'm_axi' ST_26 : Operation 216 [1/1] (1.76ns) ---> "br label %burst.wr.header" : 3.33ns ST_27 : Operation 217 [1/1] (0.00ns) ---> "%indvar1 = phi i4 [ %indvar_next1, %burst.wr.body_ifconv ], [ 0, %burst.wr.header.preheader ]" ST_27 : Operation 218 [1/1] (1.30ns) ---> "%exitcond2 = icmp eq i4 %indvar1, -8" ---> Core 25 'Cmp' ST_27 : Operation 219 [1/1] (1.73ns) ---> "%indvar_next1 = add i4 %indvar1, 1" ---> Core 14 'AddSub' ST_27 : Operation 220 [1/1] (0.00ns) ---> "br i1 %exitcond2, label %memcpy.tail, label %burst.wr.body_ifconv" ST_27 : Operation 221 [1/1] (0.00ns) ---> "%tmp_15 = trunc i4 %indvar1 to i1" ST_27 : Operation 222 [1/1] (0.00ns) ---> "%newIndex30_t = call i2 @_ssdm_op_PartSelect.i2.i4.i32.i32(i4 %indvar1, i32 1, i32 2)" ST_27 : Operation 223 [1/1] (1.95ns) ---> "%tmp_11 = call i32 @_ssdm_op_Mux.ap_auto.4i32.i2(i32 %tempResult_1_3_7, i32 %tempResult_1_1_s, i32 %tempResult_1_2_s, i32 %tempResult_1_3, i2 %newIndex30_t) nounwind" [vector_mult/vector_mult.cpp:8] ---> Core 31 'MuxnS' ST_27 : Operation 224 [1/1] (1.95ns) ---> "%tmp_12 = call i32 @_ssdm_op_Mux.ap_auto.4i32.i2(i32 %tempResult_0_3_7, i32 %tempResult_0_1_s, i32 %tempResult_0_2_s, i32 %tempResult_0_3, i2 %newIndex30_t) nounwind" [vector_mult/vector_mult.cpp:8] ---> Core 31 'MuxnS' ST_27 : Operation 225 [1/1] (1.37ns) ---> "%tempResult_load_phi = select i1 %tmp_15, i32 %tmp_11, i32 %tmp_12" [vector_mult/vector_mult.cpp:10] ---> Core 26 'Sel' : 8.75ns ST_28 : Operation 226 [1/1] (0.00ns) ---> "%empty_9 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 8, i64 8, i64 8) nounwind" ST_28 : Operation 227 [1/1] (0.00ns) ---> "%burstwrite_rbegin = call i32 (...)* @_ssdm_op_SpecRegionBegin([18 x i8]* @burstwrite_OC_region) nounwind" ST_28 : Operation 228 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecPipeline(i32 1, i32 1, i32 1, i32 0, [1 x i8]* @p_str8)" ST_28 : Operation 229 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecLoopName([29 x i8]* @memcpy_OC_result_OC_s)" ST_28 : Operation 230 [1/1] (8.75ns) ---> "call void @_ssdm_op_Write.m_axi.i32P(i32* %gmem_addr, i32 %tempResult_load_phi, i4 -1)" [vector_mult/vector_mult.cpp:10] ---> Core 9 'm_axi' ST_28 : Operation 231 [1/1] (0.00ns) ---> "%burstwrite_rend = call i32 (...)* @_ssdm_op_SpecRegionEnd([18 x i8]* @burstwrite_OC_region, i32 %burstwrite_rbegin) nounwind" ST_28 : Operation 232 [1/1] (0.00ns) ---> "br label %burst.wr.header" : 8.75ns ST_29 : Operation 233 [5/5] (8.75ns) ---> "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %gmem_addr)" [vector_mult/vector_mult.cpp:10] ---> Core 9 'm_axi' : 8.75ns ST_30 : Operation 234 [4/5] (8.75ns) ---> "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %gmem_addr)" [vector_mult/vector_mult.cpp:10] ---> Core 9 'm_axi' : 8.75ns ST_31 : Operation 235 [3/5] (8.75ns) ---> "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %gmem_addr)" [vector_mult/vector_mult.cpp:10] ---> Core 9 'm_axi' : 8.75ns ST_32 : Operation 236 [2/5] (8.75ns) ---> "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %gmem_addr)" [vector_mult/vector_mult.cpp:10] ---> Core 9 'm_axi' : 8.75ns ST_33 : Operation 237 [1/5] (8.75ns) ---> "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %gmem_addr)" [vector_mult/vector_mult.cpp:10] ---> Core 9 'm_axi' ST_33 : Operation 238 [1/1] (0.00ns) ---> "ret void" [vector_mult/vector_mult.cpp:11] ============================================================ + Verbose Summary: Timing violations ============================================================ Target clock period: 10ns, clock uncertainty: 1.25ns. : 1ns The critical path consists of the following: s_axi read on port 'result' [5] (1 ns) : 8.75ns The critical path consists of the following: 'getelementptr' operation ('gmem_addr_2') [16] (0 ns) bus request on port 'gmem' (vector_mult/vector_mult.cpp:6) [24] (8.75 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:6) [24] (8.75 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:6) [24] (8.75 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:6) [24] (8.75 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:6) [24] (8.75 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:6) [24] (8.75 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:6) [24] (8.75 ns) : 2.23ns The critical path consists of the following: 'icmp' operation ('exitcond1') [36] (1.3 ns) blocking operation 0.931 ns on control path) : 8.75ns The critical path consists of the following: bus read on port 'gmem' (vector_mult/vector_mult.cpp:6) [44] (8.75 ns) : 4.63ns The critical path consists of the following: 'icmp' operation ('sel_tmp4') [51] (0.959 ns) 'or' operation ('or_cond') [64] (0.931 ns) 'select' operation ('newSel1', vector_mult/vector_mult.cpp:6) [69] (1.37 ns) 'select' operation ('tempA[1][3]', vector_mult/vector_mult.cpp:6) [70] (1.37 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:7) [77] (8.75 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:7) [77] (8.75 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:7) [77] (8.75 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:7) [77] (8.75 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:7) [77] (8.75 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:7) [77] (8.75 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:7) [77] (8.75 ns) : 2.23ns The critical path consists of the following: 'icmp' operation ('exitcond9') [89] (1.3 ns) blocking operation 0.931 ns on control path) : 8.75ns The critical path consists of the following: bus read on port 'gmem' (vector_mult/vector_mult.cpp:7) [97] (8.75 ns) : 4.63ns The critical path consists of the following: 'icmp' operation ('sel_tmp3') [104] (0.959 ns) 'or' operation ('or_cond7') [117] (0.931 ns) 'select' operation ('newSel7', vector_mult/vector_mult.cpp:7) [122] (1.37 ns) 'select' operation ('tempB[1][3]', vector_mult/vector_mult.cpp:7) [123] (1.37 ns) : 1.77ns The critical path consists of the following: multiplexor before 'phi' operation ('tempResult[1][3]') with incoming values : ('tempResult[1][3]', vector_mult/vector_mult.cpp:9) [132] (1.77 ns) : 2.23ns The critical path consists of the following: 'icmp' operation ('exitcond', vector_mult/vector_mult.cpp:8) [141] (1.3 ns) blocking operation 0.931 ns on control path) : 8.51ns The critical path consists of the following: 'mul' operation ('tempResult[0][3]', vector_mult/vector_mult.cpp:9) [151] (8.51 ns) : 3.7ns The critical path consists of the following: 'icmp' operation ('sel_tmp5', vector_mult/vector_mult.cpp:8) [152] (0.959 ns) 'select' operation ('tempResult[0][3]', vector_mult/vector_mult.cpp:8) [153] (0 ns) 'select' operation ('tempResult[0][3]', vector_mult/vector_mult.cpp:8) [155] (1.37 ns) 'select' operation ('tempResult[0][3]', vector_mult/vector_mult.cpp:9) [173] (1.37 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:10) [183] (8.75 ns) : 3.33ns The critical path consists of the following: 'phi' operation ('indvar1') with incoming values : ('indvar_next1') [186] (0 ns) 'mux' operation ('tmp_11', vector_mult/vector_mult.cpp:8) [197] (1.96 ns) 'select' operation ('tempResult_load_phi', vector_mult/vector_mult.cpp:10) [199] (1.37 ns) : 8.75ns The critical path consists of the following: bus write on port 'gmem' (vector_mult/vector_mult.cpp:10) [200] (8.75 ns) : 8.75ns The critical path consists of the following: bus access on port 'gmem' (vector_mult/vector_mult.cpp:10) [204] (8.75 ns) : 8.75ns The critical path consists of the following: bus access on port 'gmem' (vector_mult/vector_mult.cpp:10) [204] (8.75 ns) : 8.75ns The critical path consists of the following: bus access on port 'gmem' (vector_mult/vector_mult.cpp:10) [204] (8.75 ns) : 8.75ns The critical path consists of the following: bus access on port 'gmem' (vector_mult/vector_mult.cpp:10) [204] (8.75 ns) : 8.75ns The critical path consists of the following: bus access on port 'gmem' (vector_mult/vector_mult.cpp:10) [204] (8.75 ns) ============================================================ + Verbose Summary: Binding ============================================================ N/A * FSMD analyzer results: - Output states: - Input state : - Chain level: State 1 State 2 State 3 State 4 State 5 State 6 State 7 State 8 State 9 State 10 State 11 State 12 State 13 State 14 State 15 State 16 State 17 State 18 State 19 State 20 State 21 State 22 State 23 State 24 State 25 State 26 State 27 State 28 State 29 State 30 State 31 State 32 State 33 ============================================================ + Verbose Summary: Datapath Resource usage ============================================================ N/A