================================================================ == Vivado HLS Report for 'vector_mult' ================================================================ * Date: Mon Mar 19 10:54:34 2018 * Version: 2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017) * Project: vector_mult * Solution: solution3 * Product family: zynq * Target device: xc7z020clg484-1 ================================================================ == Performance Estimates ================================================================ + Timing (ns): * Summary: +--------+-------+----------+------------+ | Clock | Target| Estimated| Uncertainty| +--------+-------+----------+------------+ |ap_clk | 10.00| 8.75| 1.25| +--------+-------+----------+------------+ + Latency (clock cycles): * Summary: +-----+-----+-----+-----+---------+ | Latency | Interval | Pipeline| | min | max | min | max | Type | +-----+-----+-----+-----+---------+ | 54| 54| 54| 54| none | +-----+-----+-----+-----+---------+ + Detail: * Instance: N/A * Loop: +--------------------------------+-----+-----+----------+-----------+-----------+------+----------+ | | Latency | Iteration| Initiation Interval | Trip | | | Loop Name | min | max | Latency | achieved | target | Count| Pipelined| +--------------------------------+-----+-----+----------+-----------+-----------+------+----------+ |- memcpy.tempA.A | 9| 9| 3| 1| 1| 8| yes | |- memcpy.tempB.B | 9| 9| 3| 1| 1| 8| yes | |- vector_mult_loop | 3| 3| 3| 1| 1| 2| yes | |- memcpy.result.tempResult.gep | 8| 8| 2| 1| 1| 8| yes | +--------------------------------+-----+-----+----------+-----------+-----------+------+----------+ ================================================================ == Utilization Estimates ================================================================ * Summary: +-----------------+---------+-------+--------+-------+ | Name | BRAM_18K| DSP48E| FF | LUT | +-----------------+---------+-------+--------+-------+ |DSP | -| -| -| -| |Expression | -| 12| 0| 2251| |FIFO | -| -| -| -| |Instance | 2| -| 662| 1022| |Memory | -| -| -| -| |Multiplexer | -| -| -| 317| |Register | -| -| 1479| -| +-----------------+---------+-------+--------+-------+ |Total | 2| 12| 2141| 3590| +-----------------+---------+-------+--------+-------+ |Available | 280| 220| 106400| 53200| +-----------------+---------+-------+--------+-------+ |Utilization (%) | ~0 | 5| 2| 6| +-----------------+---------+-------+--------+-------+ + Detail: * Instance: +------------------------------+----------------------------+---------+-------+-----+-----+ | Instance | Module | BRAM_18K| DSP48E| FF | LUT | +------------------------------+----------------------------+---------+-------+-----+-----+ |vector_mult_AXILiteS_s_axi_U |vector_mult_AXILiteS_s_axi | 0| 0| 150| 232| |vector_mult_gmem_m_axi_U |vector_mult_gmem_m_axi | 2| 0| 512| 580| |vector_mult_mux_4bkb_U1 |vector_mult_mux_4bkb | 0| 0| 0| 21| |vector_mult_mux_4bkb_U2 |vector_mult_mux_4bkb | 0| 0| 0| 21| |vector_mult_mux_4bkb_U3 |vector_mult_mux_4bkb | 0| 0| 0| 21| |vector_mult_mux_4bkb_U4 |vector_mult_mux_4bkb | 0| 0| 0| 21| |vector_mult_mux_4bkb_U5 |vector_mult_mux_4bkb | 0| 0| 0| 21| |vector_mult_mux_4bkb_U6 |vector_mult_mux_4bkb | 0| 0| 0| 21| |vector_mult_mux_4bkb_U7 |vector_mult_mux_4bkb | 0| 0| 0| 21| |vector_mult_mux_4bkb_U8 |vector_mult_mux_4bkb | 0| 0| 0| 21| |vector_mult_mux_4bkb_U9 |vector_mult_mux_4bkb | 0| 0| 0| 21| |vector_mult_mux_4bkb_U10 |vector_mult_mux_4bkb | 0| 0| 0| 21| +------------------------------+----------------------------+---------+-------+-----+-----+ |Total | | 2| 0| 662| 1022| +------------------------------+----------------------------+---------+-------+-----+-----+ * DSP48: N/A * Memory: N/A * FIFO: N/A * Expression: +-----------------------------------+----------+-------+---+----+------------+------------+ | Variable Name | Operation| DSP48E| FF| LUT| Bitwidth P0| Bitwidth P1| +-----------------------------------+----------+-------+---+----+------------+------------+ |tempResult_0_1_fu_1148_p2 | * | 3| 0| 20| 32| 32| |tempResult_0_3_11_fu_1140_p2 | * | 3| 0| 20| 32| 32| |tempResult_1_1_fu_1152_p2 | * | 3| 0| 20| 32| 32| |tempResult_1_3_11_fu_1144_p2 | * | 3| 0| 20| 32| 32| |i_1_3_fu_1134_p2 | + | 0| 0| 13| 4| 3| |indvar_next1_fu_1270_p2 | + | 0| 0| 13| 4| 1| |indvar_next8_fu_787_p2 | + | 0| 0| 13| 4| 1| |indvar_next_fu_574_p2 | + | 0| 0| 13| 4| 1| |ap_block_pp0_stage0_11001 | and | 0| 0| 8| 1| 1| |ap_block_pp1_stage0_11001 | and | 0| 0| 8| 1| 1| |ap_block_pp3_stage0_11001 | and | 0| 0| 8| 1| 1| |ap_block_state10_pp0_stage0_iter1 | and | 0| 0| 8| 1| 1| |ap_block_state20_pp1_stage0_iter1 | and | 0| 0| 8| 1| 1| |ap_block_state28_io | and | 0| 0| 8| 1| 1| |ap_condition_1367 | and | 0| 0| 8| 1| 1| |cond_fu_1100_p2 | icmp | 0| 0| 8| 2| 1| |exitcond1_fu_568_p2 | icmp | 0| 0| 11| 4| 5| |exitcond2_fu_1264_p2 | icmp | 0| 0| 11| 4| 5| |exitcond9_fu_781_p2 | icmp | 0| 0| 11| 4| 5| |exitcond_fu_994_p2 | icmp | 0| 0| 11| 4| 5| |sel_tmp1_fu_819_p2 | icmp | 0| 0| 8| 2| 1| |sel_tmp2_fu_606_p2 | icmp | 0| 0| 8| 2| 1| |sel_tmp3_fu_832_p2 | icmp | 0| 0| 8| 2| 1| |sel_tmp4_fu_619_p2 | icmp | 0| 0| 8| 2| 1| |sel_tmp5_fu_1156_p2 | icmp | 0| 0| 9| 2| 3| |sel_tmp6_fu_1168_p2 | icmp | 0| 0| 8| 2| 1| |sel_tmp8_fu_807_p2 | icmp | 0| 0| 9| 2| 3| |sel_tmp_fu_594_p2 | icmp | 0| 0| 9| 2| 3| |newIndex68_t_fu_1066_p2 | or | 0| 0| 8| 2| 1| |or_cond1_fu_717_p2 | or | 0| 0| 8| 1| 1| |or_cond2_fu_723_p2 | or | 0| 0| 8| 1| 1| |or_cond7_fu_925_p2 | or | 0| 0| 8| 1| 1| |or_cond8_fu_930_p2 | or | 0| 0| 8| 1| 1| |or_cond9_fu_936_p2 | or | 0| 0| 8| 1| 1| |or_cond_fu_712_p2 | or | 0| 0| 8| 1| 1| |newSel1_fu_743_p3 | select | 0| 0| 32| 1| 32| |newSel3_fu_759_p3 | select | 0| 0| 32| 1| 32| |newSel6_fu_949_p3 | select | 0| 0| 32| 1| 32| |newSel7_fu_956_p3 | select | 0| 0| 32| 1| 32| |newSel9_fu_972_p3 | select | 0| 0| 32| 1| 32| |newSel_fu_736_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_11_fu_670_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_14_fu_677_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_15_fu_691_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_16_fu_698_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_17_fu_705_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_18_fu_729_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_19_fu_751_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_1_fu_684_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_20_fu_766_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_21_fu_774_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_2_fu_624_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_3_fu_611_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_4_fu_632_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_5_fu_639_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_6_fu_647_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_8_fu_655_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_9_fu_662_p3 | select | 0| 0| 32| 1| 32| |tempA_1_3_fu_599_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_11_fu_883_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_14_fu_890_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_15_fu_904_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_16_fu_911_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_17_fu_918_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_18_fu_942_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_19_fu_964_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_1_fu_897_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_20_fu_979_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_21_fu_987_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_2_fu_837_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_3_fu_824_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_4_fu_845_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_5_fu_852_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_6_fu_860_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_8_fu_868_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_9_fu_875_p3 | select | 0| 0| 32| 1| 32| |tempB_1_3_fu_812_p3 | select | 0| 0| 32| 1| 32| |tempResult_0_3_10_fu_1246_p3 | select | 0| 0| 32| 1| 32| |tempResult_0_3_1_fu_1173_p3 | select | 0| 0| 32| 1| 32| |tempResult_0_3_2_fu_1240_p3 | select | 0| 0| 32| 1| 32| |tempResult_0_3_4_fu_1161_p3 | select | 0| 0| 32| 1| 32| |tempResult_0_3_5_fu_1181_p3 | select | 0| 0| 32| 1| 32| |tempResult_0_3_6_fu_1188_p3 | select | 0| 0| 32| 1| 32| |tempResult_0_3_8_fu_1196_p3 | select | 0| 0| 32| 1| 32| |tempResult_1_3_10_fu_1258_p3 | select | 0| 0| 32| 1| 32| |tempResult_1_3_1_fu_1210_p3 | select | 0| 0| 32| 1| 32| |tempResult_1_3_2_fu_1252_p3 | select | 0| 0| 32| 1| 32| |tempResult_1_3_4_fu_1203_p3 | select | 0| 0| 32| 1| 32| |tempResult_1_3_5_fu_1218_p3 | select | 0| 0| 32| 1| 32| |tempResult_1_3_6_fu_1225_p3 | select | 0| 0| 32| 1| 32| |tempResult_1_3_8_fu_1233_p3 | select | 0| 0| 32| 1| 32| |tempResult_load_phi_fu_1318_p3 | select | 0| 0| 32| 1| 32| |ap_enable_pp0 | xor | 0| 0| 8| 1| 2| |ap_enable_pp1 | xor | 0| 0| 8| 1| 2| |ap_enable_pp2 | xor | 0| 0| 8| 1| 2| |ap_enable_pp3 | xor | 0| 0| 8| 1| 2| |ap_enable_reg_pp0_iter1 | xor | 0| 0| 8| 2| 1| |ap_enable_reg_pp1_iter1 | xor | 0| 0| 8| 2| 1| |ap_enable_reg_pp2_iter1 | xor | 0| 0| 8| 2| 1| |ap_enable_reg_pp3_iter1 | xor | 0| 0| 8| 2| 1| +-----------------------------------+----------+-------+---+----+------------+------------+ |Total | | 12| 0|2251| 262| 2019| +-----------------------------------+----------+-------+---+----+------------+------------+ * Multiplexer: +-----------------------------+-----+-----------+-----+-----------+ | Name | LUT | Input Size| Bits| Total Bits| +-----------------------------+-----+-----------+-----+-----------+ |ap_NS_fsm | 125| 27| 1| 27| |ap_enable_reg_pp0_iter1 | 9| 2| 1| 2| |ap_enable_reg_pp0_iter2 | 9| 2| 1| 2| |ap_enable_reg_pp1_iter1 | 9| 2| 1| 2| |ap_enable_reg_pp1_iter2 | 9| 2| 1| 2| |ap_enable_reg_pp2_iter1 | 9| 2| 1| 2| |ap_enable_reg_pp2_iter2 | 9| 2| 1| 2| |ap_enable_reg_pp3_iter1 | 15| 3| 1| 3| |ap_sig_ioackin_gmem_ARREADY | 9| 2| 1| 2| |ap_sig_ioackin_gmem_AWREADY | 9| 2| 1| 2| |ap_sig_ioackin_gmem_WREADY | 9| 2| 1| 2| |gmem_ARADDR | 15| 3| 32| 96| |gmem_blk_n_AR | 9| 2| 1| 2| |gmem_blk_n_AW | 9| 2| 1| 2| |gmem_blk_n_B | 9| 2| 1| 2| |gmem_blk_n_R | 9| 2| 1| 2| |gmem_blk_n_W | 9| 2| 1| 2| |i_reg_488 | 9| 2| 4| 8| |indvar1_reg_499 | 9| 2| 4| 8| |indvar7_reg_381 | 9| 2| 4| 8| |indvar_reg_274 | 9| 2| 4| 8| +-----------------------------+-----+-----------+-----+-----------+ |Total | 317| 69| 64| 186| +-----------------------------+-----+-----------+-----+-----------+ * Register: +----------------------------------------+----+----+-----+-----------+ | Name | FF | LUT| Bits| Const Bits| +----------------------------------------+----+----+-----+-----------+ |A1_reg_1336 | 30| 0| 30| 0| |B3_reg_1331 | 30| 0| 30| 0| |ap_CS_fsm | 26| 0| 26| 0| |ap_enable_reg_pp0_iter0 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter1 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter2 | 1| 0| 1| 0| |ap_enable_reg_pp1_iter0 | 1| 0| 1| 0| |ap_enable_reg_pp1_iter1 | 1| 0| 1| 0| |ap_enable_reg_pp1_iter2 | 1| 0| 1| 0| |ap_enable_reg_pp2_iter0 | 1| 0| 1| 0| |ap_enable_reg_pp2_iter1 | 1| 0| 1| 0| |ap_enable_reg_pp2_iter2 | 1| 0| 1| 0| |ap_enable_reg_pp3_iter0 | 1| 0| 1| 0| |ap_enable_reg_pp3_iter1 | 1| 0| 1| 0| |ap_reg_ioackin_gmem_ARREADY | 1| 0| 1| 0| |ap_reg_ioackin_gmem_AWREADY | 1| 0| 1| 0| |ap_reg_ioackin_gmem_WREADY | 1| 0| 1| 0| |ap_reg_pp0_iter1_exitcond1_reg_1359 | 1| 0| 1| 0| |ap_reg_pp0_iter1_newIndex84_t_reg_1378 | 2| 0| 2| 0| |ap_reg_pp0_iter1_tmp_reg_1368 | 1| 0| 1| 0| |ap_reg_pp1_iter1_exitcond9_reg_1437 | 1| 0| 1| 0| |ap_reg_pp1_iter1_newIndex58_t_reg_1456 | 2| 0| 2| 0| |ap_reg_pp1_iter1_tmp_14_reg_1446 | 1| 0| 1| 0| |ap_reg_pp2_iter1_cond_reg_1555 | 1| 0| 1| 0| |ap_reg_pp2_iter1_exitcond_reg_1515 | 1| 0| 1| 0| |ap_reg_pp2_iter1_newIndex78_t_reg_1519 | 2| 0| 2| 0| |cond_reg_1555 | 1| 0| 1| 0| |exitcond1_reg_1359 | 1| 0| 1| 0| |exitcond2_reg_1644 | 1| 0| 1| 0| |exitcond9_reg_1437 | 1| 0| 1| 0| |exitcond_reg_1515 | 1| 0| 1| 0| |gmem_addr_1_reg_1353 | 30| 0| 32| 2| |gmem_addr_reg_1347 | 30| 0| 32| 2| |i_reg_488 | 4| 0| 4| 0| |indvar1_reg_499 | 4| 0| 4| 0| |indvar7_reg_381 | 4| 0| 4| 0| |indvar_reg_274 | 4| 0| 4| 0| |newIndex58_t_reg_1456 | 2| 0| 2| 0| |newIndex78_t_reg_1519 | 2| 0| 2| 0| |newIndex84_t_reg_1378 | 2| 0| 2| 0| |result5_reg_1326 | 30| 0| 30| 0| |tempA_0_2_s_reg_238 | 32| 0| 32| 0| |tempA_0_3_s_reg_226 | 32| 0| 32| 0| |tempA_1_2_s_reg_190 | 32| 0| 32| 0| |tempA_1_3_10_reg_214 | 32| 0| 32| 0| |tempA_1_3_12_reg_250 | 32| 0| 32| 0| |tempA_1_3_13_reg_262 | 32| 0| 32| 0| |tempA_1_3_23_reg_1385 | 32| 0| 32| 0| |tempA_1_3_7_reg_202 | 32| 0| 32| 0| |tempA_1_3_s_reg_178 | 32| 0| 32| 0| |tempB_0_2_s_reg_345 | 32| 0| 32| 0| |tempB_0_3_s_reg_333 | 32| 0| 32| 0| |tempB_1_2_s_reg_297 | 32| 0| 32| 0| |tempB_1_3_10_reg_321 | 32| 0| 32| 0| |tempB_1_3_12_reg_357 | 32| 0| 32| 0| |tempB_1_3_13_reg_369 | 32| 0| 32| 0| |tempB_1_3_23_reg_1463 | 32| 0| 32| 0| |tempB_1_3_7_reg_309 | 32| 0| 32| 0| |tempB_1_3_s_reg_285 | 32| 0| 32| 0| |tempResult_0_1_reg_1592 | 32| 0| 32| 0| |tempResult_0_1_s_reg_464 | 32| 0| 32| 0| |tempResult_0_2_s_reg_452 | 32| 0| 32| 0| |tempResult_0_3_11_reg_1578 | 32| 0| 32| 0| |tempResult_0_3_7_reg_476 | 32| 0| 32| 0| |tempResult_0_3_reg_440 | 32| 0| 32| 0| |tempResult_1_1_reg_1598 | 32| 0| 32| 0| |tempResult_1_1_s_reg_416 | 32| 0| 32| 0| |tempResult_1_2_s_reg_404 | 32| 0| 32| 0| |tempResult_1_3_11_reg_1585 | 32| 0| 32| 0| |tempResult_1_3_7_reg_428 | 32| 0| 32| 0| |tempResult_1_3_reg_392 | 32| 0| 32| 0| |tempResult_load_phi_reg_1653 | 32| 0| 32| 0| |tmp_10_reg_1568 | 32| 0| 32| 0| |tmp_14_reg_1446 | 1| 0| 1| 0| |tmp_3_reg_1525 | 32| 0| 32| 0| |tmp_4_reg_1530 | 32| 0| 32| 0| |tmp_6_reg_1535 | 32| 0| 32| 0| |tmp_7_reg_1540 | 32| 0| 32| 0| |tmp_8_reg_1545 | 32| 0| 32| 0| |tmp_9_reg_1550 | 32| 0| 32| 0| |tmp_reg_1368 | 1| 0| 1| 0| |tmp_s_reg_1563 | 32| 0| 32| 0| +----------------------------------------+----+----+-----+-----------+ |Total |1479| 0| 1483| 4| +----------------------------------------+----+----+-----+-----------+ ================================================================ == Interface ================================================================ * Summary: +------------------------+-----+-----+------------+--------------+--------------+ | RTL Ports | Dir | Bits| Protocol | Source Object| C Type | +------------------------+-----+-----+------------+--------------+--------------+ |s_axi_AXILiteS_AWVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_AWREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_AWADDR | in | 6| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WDATA | in | 32| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WSTRB | in | 4| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARADDR | in | 6| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RVALID | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RREADY | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RDATA | out | 32| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RRESP | out | 2| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BVALID | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BREADY | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BRESP | out | 2| s_axi | AXILiteS | scalar | |ap_clk | in | 1| ap_ctrl_hs | vector_mult | return value | |ap_rst_n | in | 1| ap_ctrl_hs | vector_mult | return value | |interrupt | out | 1| ap_ctrl_hs | vector_mult | return value | |m_axi_gmem_AWVALID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_AWREADY | in | 1| m_axi | gmem | pointer | |m_axi_gmem_AWADDR | out | 32| m_axi | gmem | pointer | |m_axi_gmem_AWID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_AWLEN | out | 8| m_axi | gmem | pointer | |m_axi_gmem_AWSIZE | out | 3| m_axi | gmem | pointer | |m_axi_gmem_AWBURST | out | 2| m_axi | gmem | pointer | |m_axi_gmem_AWLOCK | out | 2| m_axi | gmem | pointer | |m_axi_gmem_AWCACHE | out | 4| m_axi | gmem | pointer | |m_axi_gmem_AWPROT | out | 3| m_axi | gmem | pointer | |m_axi_gmem_AWQOS | out | 4| m_axi | gmem | pointer | |m_axi_gmem_AWREGION | out | 4| m_axi | gmem | pointer | |m_axi_gmem_AWUSER | out | 1| m_axi | gmem | pointer | |m_axi_gmem_WVALID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_WREADY | in | 1| m_axi | gmem | pointer | |m_axi_gmem_WDATA | out | 32| m_axi | gmem | pointer | |m_axi_gmem_WSTRB | out | 4| m_axi | gmem | pointer | |m_axi_gmem_WLAST | out | 1| m_axi | gmem | pointer | |m_axi_gmem_WID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_WUSER | out | 1| m_axi | gmem | pointer | |m_axi_gmem_ARVALID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_ARREADY | in | 1| m_axi | gmem | pointer | |m_axi_gmem_ARADDR | out | 32| m_axi | gmem | pointer | |m_axi_gmem_ARID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_ARLEN | out | 8| m_axi | gmem | pointer | |m_axi_gmem_ARSIZE | out | 3| m_axi | gmem | pointer | |m_axi_gmem_ARBURST | out | 2| m_axi | gmem | pointer | |m_axi_gmem_ARLOCK | out | 2| m_axi | gmem | pointer | |m_axi_gmem_ARCACHE | out | 4| m_axi | gmem | pointer | |m_axi_gmem_ARPROT | out | 3| m_axi | gmem | pointer | |m_axi_gmem_ARQOS | out | 4| m_axi | gmem | pointer | |m_axi_gmem_ARREGION | out | 4| m_axi | gmem | pointer | |m_axi_gmem_ARUSER | out | 1| m_axi | gmem | pointer | |m_axi_gmem_RVALID | in | 1| m_axi | gmem | pointer | |m_axi_gmem_RREADY | out | 1| m_axi | gmem | pointer | |m_axi_gmem_RDATA | in | 32| m_axi | gmem | pointer | |m_axi_gmem_RLAST | in | 1| m_axi | gmem | pointer | |m_axi_gmem_RID | in | 1| m_axi | gmem | pointer | |m_axi_gmem_RUSER | in | 1| m_axi | gmem | pointer | |m_axi_gmem_RRESP | in | 2| m_axi | gmem | pointer | |m_axi_gmem_BVALID | in | 1| m_axi | gmem | pointer | |m_axi_gmem_BREADY | out | 1| m_axi | gmem | pointer | |m_axi_gmem_BRESP | in | 2| m_axi | gmem | pointer | |m_axi_gmem_BID | in | 1| m_axi | gmem | pointer | |m_axi_gmem_BUSER | in | 1| m_axi | gmem | pointer | +------------------------+-----+-----+------------+--------------+--------------+ ============================================================ + Verbose Summary: Synthesis Manager ============================================================ InlineROM: 1 ExposeGlobal: 0 ============================================================ + Verbose Summary: CDFG Model ============================================================ IsTopModel: 1 ResetActiveHigh: 1 IsCombinational: 2 IsDatapathOnly: 2 HasWiredReturn: 1 HasMFsm: 0 HasVarLatency: 1 IsPipeline: 0 IsRtlPipelined: 0 IsInstanceOverlapped: 0 IsDontTouch: 0 HasImplIP: 0 IsGatedGlobalClock: 0 + Individual pipeline summary: * Pipeline-0: initiation interval (II) = 1, depth = 3 * Pipeline-1: initiation interval (II) = 1, depth = 3 * Pipeline-2: initiation interval (II) = 1, depth = 3 * Pipeline-3: initiation interval (II) = 1, depth = 2 ============================================================ + Verbose Summary: Schedule ============================================================ * Number of FSM states : 33 * Pipeline : 4 Pipeline-0 : II = 1, D = 3, States = { 9 10 11 } Pipeline-1 : II = 1, D = 3, States = { 19 20 21 } Pipeline-2 : II = 1, D = 3, States = { 23 24 25 } Pipeline-3 : II = 1, D = 2, States = { 27 28 } * Dataflow Pipeline: 0 * FSM state transitions: 1 --> 2 / true 2 --> 3 / true 3 --> 4 / true 4 --> 5 / true 5 --> 6 / true 6 --> 7 / true 7 --> 8 / true 8 --> 9 / true 9 --> 12 / (exitcond1) 10 / (!exitcond1) 10 --> 11 / true 11 --> 9 / true 12 --> 13 / true 13 --> 14 / true 14 --> 15 / true 15 --> 16 / true 16 --> 17 / true 17 --> 18 / true 18 --> 19 / true 19 --> 22 / (exitcond9) 20 / (!exitcond9) 20 --> 21 / true 21 --> 19 / true 22 --> 23 / true 23 --> 26 / (exitcond) 24 / (!exitcond) 24 --> 25 / true 25 --> 23 / true 26 --> 27 / true 27 --> 29 / (exitcond2) 28 / (!exitcond2) 28 --> 27 / true 29 --> 30 / true 30 --> 31 / true 31 --> 32 / true 32 --> 33 / true 33 --> * FSM state operations: : 1.00ns ST_1 : Operation 34 [1/1] (1.00ns) ---> "%result_read = call i32 @_ssdm_op_Read.s_axilite.i32(i32 %result)" ---> Core 10 's_axilite' ST_1 : Operation 35 [1/1] (1.00ns) ---> "%B_read = call i32 @_ssdm_op_Read.s_axilite.i32(i32 %B)" ---> Core 10 's_axilite' ST_1 : Operation 36 [1/1] (1.00ns) ---> "%A_read = call i32 @_ssdm_op_Read.s_axilite.i32(i32 %A)" ---> Core 10 's_axilite' ST_1 : Operation 37 [1/1] (0.00ns) ---> "%result5 = call i30 @_ssdm_op_PartSelect.i30.i32.i32.i32(i32 %result_read, i32 2, i32 31)" ST_1 : Operation 38 [1/1] (0.00ns) ---> "%B3 = call i30 @_ssdm_op_PartSelect.i30.i32.i32.i32(i32 %B_read, i32 2, i32 31)" ST_1 : Operation 39 [1/1] (0.00ns) ---> "%A1 = call i30 @_ssdm_op_PartSelect.i30.i32.i32.i32(i32 %A_read, i32 2, i32 31)" : 8.75ns ST_2 : Operation 40 [1/1] (0.00ns) ---> "%tmp_13 = zext i30 %A1 to i64" ST_2 : Operation 41 [1/1] (0.00ns) ---> "%gmem_addr_2 = getelementptr i32* %gmem, i64 %tmp_13" ST_2 : Operation 42 [7/7] (8.75ns) ---> "%gmem_addr_2_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 8)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' : 8.75ns ST_3 : Operation 43 [6/7] (8.75ns) ---> "%gmem_addr_2_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 8)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' : 8.75ns ST_4 : Operation 44 [5/7] (8.75ns) ---> "%gmem_addr_2_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 8)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' : 8.75ns ST_5 : Operation 45 [4/7] (8.75ns) ---> "%gmem_addr_2_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 8)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' : 8.75ns ST_6 : Operation 46 [3/7] (8.75ns) ---> "%gmem_addr_2_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 8)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' : 8.75ns ST_7 : Operation 47 [2/7] (8.75ns) ---> "%gmem_addr_2_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 8)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' : 8.75ns ST_8 : Operation 48 [1/1] (0.00ns) ---> "%tmp_1 = zext i30 %result5 to i64" ST_8 : Operation 49 [1/1] (0.00ns) ---> "%gmem_addr = getelementptr i32* %gmem, i64 %tmp_1" ST_8 : Operation 50 [1/1] (0.00ns) ---> "%tmp_5 = zext i30 %B3 to i64" ST_8 : Operation 51 [1/1] (0.00ns) ---> "%gmem_addr_1 = getelementptr i32* %gmem, i64 %tmp_5" ST_8 : Operation 52 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecBitsMap(i32* %gmem), !map !11" ST_8 : Operation 53 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecTopModule([12 x i8]* @vector_mult_str) nounwind" ST_8 : Operation 54 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32 0, [10 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1, [1 x i8]* @p_str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1) nounwind" [vector_mult/vector_mult.cpp:5] ST_8 : Operation 55 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32 %result, [10 x i8]* @mode5, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @bundle6, [6 x i8]* @p_str3, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)" ST_8 : Operation 56 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32 %B, [10 x i8]* @mode3, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @bundle4, [6 x i8]* @p_str3, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)" ST_8 : Operation 57 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32* %gmem, [6 x i8]* @p_str2, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @p_str1, [6 x i8]* @p_str3, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)" ST_8 : Operation 58 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32 %A, [10 x i8]* @mode, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @bundle, [6 x i8]* @p_str3, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)" ST_8 : Operation 59 [1/7] (8.75ns) ---> "%gmem_addr_2_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 8)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' ST_8 : Operation 60 [1/1] (1.76ns) ---> "br label %burst.rd.header" : 2.23ns ST_9 : Operation 61 [1/1] (0.00ns) ---> "%tempA_1_3_s = phi i32 [ undef, %0 ], [ %tempA_1_3_1, %burst.rd.body_ifconv ]" ST_9 : Operation 62 [1/1] (0.00ns) ---> "%tempA_1_2_s = phi i32 [ undef, %0 ], [ %tempA_1_3_15, %burst.rd.body_ifconv ]" ST_9 : Operation 63 [1/1] (0.00ns) ---> "%tempA_1_3_7 = phi i32 [ undef, %0 ], [ %tempA_1_3_16, %burst.rd.body_ifconv ]" ST_9 : Operation 64 [1/1] (0.00ns) ---> "%tempA_1_3_10 = phi i32 [ undef, %0 ], [ %tempA_1_3_17, %burst.rd.body_ifconv ]" ST_9 : Operation 65 [1/1] (0.00ns) ---> "%tempA_0_3_s = phi i32 [ undef, %0 ], [ %tempA_1_3_18, %burst.rd.body_ifconv ]" ST_9 : Operation 66 [1/1] (0.00ns) ---> "%tempA_0_2_s = phi i32 [ undef, %0 ], [ %tempA_1_3_19, %burst.rd.body_ifconv ]" ST_9 : Operation 67 [1/1] (0.00ns) ---> "%tempA_1_3_12 = phi i32 [ undef, %0 ], [ %tempA_1_3_20, %burst.rd.body_ifconv ]" ST_9 : Operation 68 [1/1] (0.00ns) ---> "%tempA_1_3_13 = phi i32 [ undef, %0 ], [ %tempA_1_3_21, %burst.rd.body_ifconv ]" ST_9 : Operation 69 [1/1] (0.00ns) ---> "%indvar = phi i4 [ 0, %0 ], [ %indvar_next, %burst.rd.body_ifconv ]" ST_9 : Operation 70 [1/1] (1.30ns) ---> "%exitcond1 = icmp eq i4 %indvar, -8" ---> Core 25 'Cmp' ST_9 : Operation 71 [1/1] (1.73ns) ---> "%indvar_next = add i4 %indvar, 1" ---> Core 14 'AddSub' ST_9 : Operation 72 [1/1] (0.00ns) ---> "br i1 %exitcond1, label %burst.rd.header5.preheader, label %burst.rd.body_ifconv" ST_9 : Operation 73 [1/1] (0.00ns) ---> "%tmp = trunc i4 %indvar to i1" ST_9 : Operation 74 [1/1] (0.00ns) ---> "%newIndex84_t = call i2 @_ssdm_op_PartSelect.i2.i4.i32.i32(i4 %indvar, i32 1, i32 2)" : 8.75ns ST_10 : Operation 75 [1/1] (8.75ns) ---> "%tempA_1_3_23 = call i32 @_ssdm_op_Read.m_axi.i32P(i32* %gmem_addr_2)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' : 4.63ns ST_11 : Operation 76 [1/1] (0.00ns) ---> "%empty = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 8, i64 8, i64 8) nounwind" ST_11 : Operation 77 [1/1] (0.00ns) ---> "%burstread_rbegin = call i32 (...)* @_ssdm_op_SpecRegionBegin([17 x i8]* @burstread_OC_region_s) nounwind" ST_11 : Operation 78 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecPipeline(i32 1, i32 1, i32 1, i32 0, [1 x i8]* @p_str6)" ST_11 : Operation 79 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecLoopName([15 x i8]* @memcpy_OC_tempA_OC_A)" ST_11 : Operation 80 [1/1] (0.95ns) ---> "%sel_tmp = icmp eq i2 %newIndex84_t, -2" ---> Core 25 'Cmp' ST_11 : Operation 81 [1/1] (0.00ns) (grouped into LUT with out node tempA_1_3_3) ---> "%tempA_1_3 = select i1 %sel_tmp, i32 %tempA_1_3_s, i32 %tempA_1_3_23" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 82 [1/1] (0.95ns) ---> "%sel_tmp2 = icmp eq i2 %newIndex84_t, 1" ---> Core 25 'Cmp' ST_11 : Operation 83 [1/1] (1.37ns) (out node of the LUT) ---> "%tempA_1_3_3 = select i1 %sel_tmp2, i32 %tempA_1_3_s, i32 %tempA_1_3" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 84 [1/1] (0.95ns) ---> "%sel_tmp4 = icmp eq i2 %newIndex84_t, 0" ---> Core 25 'Cmp' ST_11 : Operation 85 [1/1] (0.00ns) (grouped into LUT with out node tempA_1_3_1) ---> "%tempA_1_3_2 = select i1 %sel_tmp4, i32 %tempA_1_3_s, i32 %tempA_1_3_3" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 86 [1/1] (0.00ns) (grouped into LUT with out node tempA_1_3_5) ---> "%tempA_1_3_4 = select i1 %sel_tmp, i32 %tempA_1_3_23, i32 %tempA_1_2_s" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 87 [1/1] (1.37ns) (out node of the LUT) ---> "%tempA_1_3_5 = select i1 %sel_tmp2, i32 %tempA_1_2_s, i32 %tempA_1_3_4" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 88 [1/1] (0.00ns) (grouped into LUT with out node tempA_1_3_15) ---> "%tempA_1_3_6 = select i1 %sel_tmp4, i32 %tempA_1_2_s, i32 %tempA_1_3_5" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 89 [1/1] (0.00ns) (grouped into LUT with out node tempA_1_3_9) ---> "%tempA_1_3_8 = select i1 %sel_tmp2, i32 %tempA_1_3_23, i32 %tempA_1_3_7" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 90 [1/1] (1.37ns) (out node of the LUT) ---> "%tempA_1_3_9 = select i1 %sel_tmp4, i32 %tempA_1_3_7, i32 %tempA_1_3_8" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 91 [1/1] (0.00ns) (grouped into LUT with out node tempA_1_3_17) ---> "%tempA_1_3_11 = select i1 %sel_tmp4, i32 %tempA_1_3_23, i32 %tempA_1_3_10" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 92 [1/1] (0.00ns) (grouped into LUT with out node tempA_1_3_21) ---> "%tempA_1_3_14 = select i1 %sel_tmp4, i32 %tempA_1_3_23, i32 %tempA_1_3_13" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 93 [1/1] (1.37ns) (out node of the LUT) ---> "%tempA_1_3_1 = select i1 %tmp, i32 %tempA_1_3_2, i32 %tempA_1_3_s" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 94 [1/1] (1.37ns) (out node of the LUT) ---> "%tempA_1_3_15 = select i1 %tmp, i32 %tempA_1_3_6, i32 %tempA_1_2_s" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 95 [1/1] (1.37ns) (out node of the LUT) ---> "%tempA_1_3_16 = select i1 %tmp, i32 %tempA_1_3_9, i32 %tempA_1_3_7" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 96 [1/1] (1.37ns) (out node of the LUT) ---> "%tempA_1_3_17 = select i1 %tmp, i32 %tempA_1_3_11, i32 %tempA_1_3_10" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 97 [1/1] (0.93ns) ---> "%or_cond = or i1 %tmp, %sel_tmp4" ---> Core 27 'LogicGate' ST_11 : Operation 98 [1/1] (0.00ns) (grouped into LUT with out node or_cond2) ---> "%or_cond1 = or i1 %sel_tmp2, %sel_tmp" ---> Core 27 'LogicGate' ST_11 : Operation 99 [1/1] (0.93ns) (out node of the LUT) ---> "%or_cond2 = or i1 %or_cond, %or_cond1" ---> Core 27 'LogicGate' ST_11 : Operation 100 [1/1] (1.37ns) ---> "%tempA_1_3_18 = select i1 %or_cond2, i32 %tempA_0_3_s, i32 %tempA_1_3_23" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 101 [1/1] (0.00ns) (grouped into LUT with out node newSel1) ---> "%newSel = select i1 %sel_tmp2, i32 %tempA_0_2_s, i32 %tempA_1_3_23" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 102 [1/1] (1.37ns) (out node of the LUT) ---> "%newSel1 = select i1 %or_cond, i32 %tempA_0_2_s, i32 %newSel" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 103 [1/1] (1.37ns) (out node of the LUT) ---> "%tempA_1_3_19 = select i1 %or_cond2, i32 %newSel1, i32 %tempA_0_2_s" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 104 [1/1] (0.00ns) (grouped into LUT with out node tempA_1_3_20) ---> "%newSel3 = select i1 %sel_tmp2, i32 %tempA_1_3_23, i32 %tempA_1_3_12" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 105 [1/1] (1.37ns) (out node of the LUT) ---> "%tempA_1_3_20 = select i1 %or_cond, i32 %tempA_1_3_12, i32 %newSel3" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 106 [1/1] (1.37ns) (out node of the LUT) ---> "%tempA_1_3_21 = select i1 %tmp, i32 %tempA_1_3_13, i32 %tempA_1_3_14" [vector_mult/vector_mult.cpp:6] ---> Core 26 'Sel' ST_11 : Operation 107 [1/1] (0.00ns) ---> "%burstread_rend = call i32 (...)* @_ssdm_op_SpecRegionEnd([17 x i8]* @burstread_OC_region_s, i32 %burstread_rbegin) nounwind" ST_11 : Operation 108 [1/1] (0.00ns) ---> "br label %burst.rd.header" : 8.75ns ST_12 : Operation 109 [7/7] (8.75ns) ---> "%gmem_addr_1_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 8)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' : 8.75ns ST_13 : Operation 110 [6/7] (8.75ns) ---> "%gmem_addr_1_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 8)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' : 8.75ns ST_14 : Operation 111 [5/7] (8.75ns) ---> "%gmem_addr_1_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 8)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' : 8.75ns ST_15 : Operation 112 [4/7] (8.75ns) ---> "%gmem_addr_1_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 8)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' : 8.75ns ST_16 : Operation 113 [3/7] (8.75ns) ---> "%gmem_addr_1_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 8)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' : 8.75ns ST_17 : Operation 114 [2/7] (8.75ns) ---> "%gmem_addr_1_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 8)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' : 8.75ns ST_18 : Operation 115 [1/7] (8.75ns) ---> "%gmem_addr_1_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 8)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' ST_18 : Operation 116 [1/1] (1.76ns) ---> "br label %burst.rd.header5" : 2.23ns ST_19 : Operation 117 [1/1] (0.00ns) ---> "%tempB_1_3_s = phi i32 [ %tempB_1_3_1, %burst.rd.body6_ifconv ], [ undef, %burst.rd.header5.preheader ]" ST_19 : Operation 118 [1/1] (0.00ns) ---> "%tempB_1_2_s = phi i32 [ %tempB_1_3_15, %burst.rd.body6_ifconv ], [ undef, %burst.rd.header5.preheader ]" ST_19 : Operation 119 [1/1] (0.00ns) ---> "%tempB_1_3_7 = phi i32 [ %tempB_1_3_16, %burst.rd.body6_ifconv ], [ undef, %burst.rd.header5.preheader ]" ST_19 : Operation 120 [1/1] (0.00ns) ---> "%tempB_1_3_10 = phi i32 [ %tempB_1_3_17, %burst.rd.body6_ifconv ], [ undef, %burst.rd.header5.preheader ]" ST_19 : Operation 121 [1/1] (0.00ns) ---> "%tempB_0_3_s = phi i32 [ %tempB_1_3_18, %burst.rd.body6_ifconv ], [ undef, %burst.rd.header5.preheader ]" ST_19 : Operation 122 [1/1] (0.00ns) ---> "%tempB_0_2_s = phi i32 [ %tempB_1_3_19, %burst.rd.body6_ifconv ], [ undef, %burst.rd.header5.preheader ]" ST_19 : Operation 123 [1/1] (0.00ns) ---> "%tempB_1_3_12 = phi i32 [ %tempB_1_3_20, %burst.rd.body6_ifconv ], [ undef, %burst.rd.header5.preheader ]" ST_19 : Operation 124 [1/1] (0.00ns) ---> "%tempB_1_3_13 = phi i32 [ %tempB_1_3_21, %burst.rd.body6_ifconv ], [ undef, %burst.rd.header5.preheader ]" ST_19 : Operation 125 [1/1] (0.00ns) ---> "%indvar7 = phi i4 [ %indvar_next8, %burst.rd.body6_ifconv ], [ 0, %burst.rd.header5.preheader ]" ST_19 : Operation 126 [1/1] (1.30ns) ---> "%exitcond9 = icmp eq i4 %indvar7, -8" ---> Core 25 'Cmp' ST_19 : Operation 127 [1/1] (1.73ns) ---> "%indvar_next8 = add i4 %indvar7, 1" ---> Core 14 'AddSub' ST_19 : Operation 128 [1/1] (0.00ns) ---> "br i1 %exitcond9, label %burst.rd.end4.0.preheader, label %burst.rd.body6_ifconv" ST_19 : Operation 129 [1/1] (0.00ns) ---> "%tmp_14 = trunc i4 %indvar7 to i1" ST_19 : Operation 130 [1/1] (0.00ns) ---> "%newIndex58_t = call i2 @_ssdm_op_PartSelect.i2.i4.i32.i32(i4 %indvar7, i32 1, i32 2)" : 8.75ns ST_20 : Operation 131 [1/1] (8.75ns) ---> "%tempB_1_3_23 = call i32 @_ssdm_op_Read.m_axi.i32P(i32* %gmem_addr_1)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' : 4.63ns ST_21 : Operation 132 [1/1] (0.00ns) ---> "%empty_6 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 8, i64 8, i64 8) nounwind" ST_21 : Operation 133 [1/1] (0.00ns) ---> "%burstread_rbegin1 = call i32 (...)* @_ssdm_op_SpecRegionBegin([17 x i8]* @burstread_OC_region_s) nounwind" ST_21 : Operation 134 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecPipeline(i32 1, i32 1, i32 1, i32 0, [1 x i8]* @p_str7)" ST_21 : Operation 135 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecLoopName([15 x i8]* @memcpy_OC_tempB_OC_B)" ST_21 : Operation 136 [1/1] (0.95ns) ---> "%sel_tmp8 = icmp eq i2 %newIndex58_t, -2" ---> Core 25 'Cmp' ST_21 : Operation 137 [1/1] (0.00ns) (grouped into LUT with out node tempB_1_3_3) ---> "%tempB_1_3 = select i1 %sel_tmp8, i32 %tempB_1_3_s, i32 %tempB_1_3_23" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 138 [1/1] (0.95ns) ---> "%sel_tmp1 = icmp eq i2 %newIndex58_t, 1" ---> Core 25 'Cmp' ST_21 : Operation 139 [1/1] (1.37ns) (out node of the LUT) ---> "%tempB_1_3_3 = select i1 %sel_tmp1, i32 %tempB_1_3_s, i32 %tempB_1_3" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 140 [1/1] (0.95ns) ---> "%sel_tmp3 = icmp eq i2 %newIndex58_t, 0" ---> Core 25 'Cmp' ST_21 : Operation 141 [1/1] (0.00ns) (grouped into LUT with out node tempB_1_3_1) ---> "%tempB_1_3_2 = select i1 %sel_tmp3, i32 %tempB_1_3_s, i32 %tempB_1_3_3" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 142 [1/1] (0.00ns) (grouped into LUT with out node tempB_1_3_5) ---> "%tempB_1_3_4 = select i1 %sel_tmp8, i32 %tempB_1_3_23, i32 %tempB_1_2_s" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 143 [1/1] (1.37ns) (out node of the LUT) ---> "%tempB_1_3_5 = select i1 %sel_tmp1, i32 %tempB_1_2_s, i32 %tempB_1_3_4" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 144 [1/1] (0.00ns) (grouped into LUT with out node tempB_1_3_15) ---> "%tempB_1_3_6 = select i1 %sel_tmp3, i32 %tempB_1_2_s, i32 %tempB_1_3_5" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 145 [1/1] (0.00ns) (grouped into LUT with out node tempB_1_3_9) ---> "%tempB_1_3_8 = select i1 %sel_tmp1, i32 %tempB_1_3_23, i32 %tempB_1_3_7" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 146 [1/1] (1.37ns) (out node of the LUT) ---> "%tempB_1_3_9 = select i1 %sel_tmp3, i32 %tempB_1_3_7, i32 %tempB_1_3_8" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 147 [1/1] (0.00ns) (grouped into LUT with out node tempB_1_3_17) ---> "%tempB_1_3_11 = select i1 %sel_tmp3, i32 %tempB_1_3_23, i32 %tempB_1_3_10" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 148 [1/1] (0.00ns) (grouped into LUT with out node tempB_1_3_21) ---> "%tempB_1_3_14 = select i1 %sel_tmp3, i32 %tempB_1_3_23, i32 %tempB_1_3_13" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 149 [1/1] (1.37ns) (out node of the LUT) ---> "%tempB_1_3_1 = select i1 %tmp_14, i32 %tempB_1_3_2, i32 %tempB_1_3_s" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 150 [1/1] (1.37ns) (out node of the LUT) ---> "%tempB_1_3_15 = select i1 %tmp_14, i32 %tempB_1_3_6, i32 %tempB_1_2_s" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 151 [1/1] (1.37ns) (out node of the LUT) ---> "%tempB_1_3_16 = select i1 %tmp_14, i32 %tempB_1_3_9, i32 %tempB_1_3_7" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 152 [1/1] (1.37ns) (out node of the LUT) ---> "%tempB_1_3_17 = select i1 %tmp_14, i32 %tempB_1_3_11, i32 %tempB_1_3_10" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 153 [1/1] (0.93ns) ---> "%or_cond7 = or i1 %tmp_14, %sel_tmp3" ---> Core 27 'LogicGate' ST_21 : Operation 154 [1/1] (0.00ns) (grouped into LUT with out node or_cond9) ---> "%or_cond8 = or i1 %sel_tmp1, %sel_tmp8" ---> Core 27 'LogicGate' ST_21 : Operation 155 [1/1] (0.93ns) (out node of the LUT) ---> "%or_cond9 = or i1 %or_cond7, %or_cond8" ---> Core 27 'LogicGate' ST_21 : Operation 156 [1/1] (1.37ns) ---> "%tempB_1_3_18 = select i1 %or_cond9, i32 %tempB_0_3_s, i32 %tempB_1_3_23" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 157 [1/1] (0.00ns) (grouped into LUT with out node newSel7) ---> "%newSel6 = select i1 %sel_tmp1, i32 %tempB_0_2_s, i32 %tempB_1_3_23" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 158 [1/1] (1.37ns) (out node of the LUT) ---> "%newSel7 = select i1 %or_cond7, i32 %tempB_0_2_s, i32 %newSel6" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 159 [1/1] (1.37ns) (out node of the LUT) ---> "%tempB_1_3_19 = select i1 %or_cond9, i32 %newSel7, i32 %tempB_0_2_s" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 160 [1/1] (0.00ns) (grouped into LUT with out node tempB_1_3_20) ---> "%newSel9 = select i1 %sel_tmp1, i32 %tempB_1_3_23, i32 %tempB_1_3_12" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 161 [1/1] (1.37ns) (out node of the LUT) ---> "%tempB_1_3_20 = select i1 %or_cond7, i32 %tempB_1_3_12, i32 %newSel9" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 162 [1/1] (1.37ns) (out node of the LUT) ---> "%tempB_1_3_21 = select i1 %tmp_14, i32 %tempB_1_3_13, i32 %tempB_1_3_14" [vector_mult/vector_mult.cpp:7] ---> Core 26 'Sel' ST_21 : Operation 163 [1/1] (0.00ns) ---> "%burstread_rend12 = call i32 (...)* @_ssdm_op_SpecRegionEnd([17 x i8]* @burstread_OC_region_s, i32 %burstread_rbegin1) nounwind" ST_21 : Operation 164 [1/1] (0.00ns) ---> "br label %burst.rd.header5" : 1.77ns ST_22 : Operation 165 [1/1] (1.76ns) ---> "br label %burst.rd.end4.0" [vector_mult/vector_mult.cpp:8] : 2.23ns ST_23 : Operation 166 [1/1] (0.00ns) ---> "%tempResult_1_3 = phi i32 [ %tempResult_1_3_2, %burst.rd.end4.1_ifconv ], [ undef, %burst.rd.end4.0.preheader ]" ST_23 : Operation 167 [1/1] (0.00ns) ---> "%tempResult_1_2_s = phi i32 [ %tempResult_1_3_6, %burst.rd.end4.1_ifconv ], [ undef, %burst.rd.end4.0.preheader ]" ST_23 : Operation 168 [1/1] (0.00ns) ---> "%tempResult_1_1_s = phi i32 [ %tempResult_1_3_10, %burst.rd.end4.1_ifconv ], [ undef, %burst.rd.end4.0.preheader ]" ST_23 : Operation 169 [1/1] (0.00ns) ---> "%tempResult_1_3_7 = phi i32 [ %tempResult_1_3_8, %burst.rd.end4.1_ifconv ], [ undef, %burst.rd.end4.0.preheader ]" ST_23 : Operation 170 [1/1] (0.00ns) ---> "%tempResult_0_3 = phi i32 [ %tempResult_0_3_2, %burst.rd.end4.1_ifconv ], [ undef, %burst.rd.end4.0.preheader ]" ST_23 : Operation 171 [1/1] (0.00ns) ---> "%tempResult_0_2_s = phi i32 [ %tempResult_0_3_6, %burst.rd.end4.1_ifconv ], [ undef, %burst.rd.end4.0.preheader ]" ST_23 : Operation 172 [1/1] (0.00ns) ---> "%tempResult_0_1_s = phi i32 [ %tempResult_0_3_10, %burst.rd.end4.1_ifconv ], [ undef, %burst.rd.end4.0.preheader ]" ST_23 : Operation 173 [1/1] (0.00ns) ---> "%tempResult_0_3_7 = phi i32 [ %tempResult_0_3_8, %burst.rd.end4.1_ifconv ], [ undef, %burst.rd.end4.0.preheader ]" ST_23 : Operation 174 [1/1] (0.00ns) ---> "%i = phi i4 [ %i_1_3, %burst.rd.end4.1_ifconv ], [ 0, %burst.rd.end4.0.preheader ]" [vector_mult/vector_mult.cpp:8] ST_23 : Operation 175 [1/1] (1.30ns) ---> "%exitcond = icmp eq i4 %i, -8" [vector_mult/vector_mult.cpp:8] ---> Core 25 'Cmp' ST_23 : Operation 176 [1/1] (0.00ns) ---> "br i1 %exitcond, label %burst.wr.header.preheader, label %burst.rd.end4.1_ifconv" [vector_mult/vector_mult.cpp:8] ST_23 : Operation 177 [1/1] (0.00ns) ---> "%newIndex78_t = call i2 @_ssdm_op_PartSelect.i2.i4.i32.i32(i4 %i, i32 1, i32 2)" [vector_mult/vector_mult.cpp:8] ST_23 : Operation 178 [1/1] (1.95ns) ---> "%tmp_3 = call i32 @_ssdm_op_Mux.ap_auto.4i32.i2(i32 %tempA_1_3_13, i32 %tempA_1_3_12, i32 %tempA_0_2_s, i32 %tempA_0_3_s, i2 %newIndex78_t) nounwind" [vector_mult/vector_mult.cpp:6] ---> Core 31 'MuxnS' ST_23 : Operation 179 [1/1] (1.95ns) ---> "%tmp_4 = call i32 @_ssdm_op_Mux.ap_auto.4i32.i2(i32 %tempB_1_3_13, i32 %tempB_1_3_12, i32 %tempB_0_2_s, i32 %tempB_0_3_s, i2 %newIndex78_t) nounwind" [vector_mult/vector_mult.cpp:7] ---> Core 31 'MuxnS' ST_23 : Operation 180 [1/1] (1.95ns) ---> "%tmp_6 = call i32 @_ssdm_op_Mux.ap_auto.4i32.i2(i32 %tempA_1_3_10, i32 %tempA_1_3_7, i32 %tempA_1_2_s, i32 %tempA_1_3_s, i2 %newIndex78_t) nounwind" [vector_mult/vector_mult.cpp:6] ---> Core 31 'MuxnS' ST_23 : Operation 181 [1/1] (1.95ns) ---> "%tmp_7 = call i32 @_ssdm_op_Mux.ap_auto.4i32.i2(i32 %tempB_1_3_10, i32 %tempB_1_3_7, i32 %tempB_1_2_s, i32 %tempB_1_3_s, i2 %newIndex78_t) nounwind" [vector_mult/vector_mult.cpp:7] ---> Core 31 'MuxnS' ST_23 : Operation 182 [1/1] (0.00ns) ---> "%newIndex68_t = or i2 %newIndex78_t, 1" [vector_mult/vector_mult.cpp:8] ST_23 : Operation 183 [1/1] (1.95ns) ---> "%tmp_8 = call i32 @_ssdm_op_Mux.ap_auto.4i32.i2(i32 %tempA_1_3_13, i32 %tempA_1_3_12, i32 %tempA_0_2_s, i32 %tempA_0_3_s, i2 %newIndex68_t) nounwind" [vector_mult/vector_mult.cpp:6] ---> Core 31 'MuxnS' ST_23 : Operation 184 [1/1] (1.95ns) ---> "%tmp_9 = call i32 @_ssdm_op_Mux.ap_auto.4i32.i2(i32 %tempB_1_3_13, i32 %tempB_1_3_12, i32 %tempB_0_2_s, i32 %tempB_0_3_s, i2 %newIndex68_t) nounwind" [vector_mult/vector_mult.cpp:7] ---> Core 31 'MuxnS' ST_23 : Operation 185 [1/1] (0.95ns) ---> "%cond = icmp eq i2 %newIndex68_t, 1" [vector_mult/vector_mult.cpp:9] ---> Core 25 'Cmp' ST_23 : Operation 186 [1/1] (1.95ns) ---> "%tmp_s = call i32 @_ssdm_op_Mux.ap_auto.4i32.i2(i32 %tempA_1_3_10, i32 %tempA_1_3_7, i32 %tempA_1_2_s, i32 %tempA_1_3_s, i2 %newIndex68_t) nounwind" [vector_mult/vector_mult.cpp:6] ---> Core 31 'MuxnS' ST_23 : Operation 187 [1/1] (1.95ns) ---> "%tmp_10 = call i32 @_ssdm_op_Mux.ap_auto.4i32.i2(i32 %tempB_1_3_10, i32 %tempB_1_3_7, i32 %tempB_1_2_s, i32 %tempB_1_3_s, i2 %newIndex68_t) nounwind" [vector_mult/vector_mult.cpp:7] ---> Core 31 'MuxnS' ST_23 : Operation 188 [1/1] (1.73ns) ---> "%i_1_3 = add i4 %i, 4" [vector_mult/vector_mult.cpp:8] ---> Core 14 'AddSub' : 8.51ns ST_24 : Operation 189 [1/1] (8.51ns) ---> "%tempResult_0_3_11 = mul nsw i32 %tmp_4, %tmp_3" [vector_mult/vector_mult.cpp:9] ---> Core 16 'Mul' ST_24 : Operation 190 [1/1] (8.51ns) ---> "%tempResult_1_3_11 = mul nsw i32 %tmp_7, %tmp_6" [vector_mult/vector_mult.cpp:9] ---> Core 16 'Mul' ST_24 : Operation 191 [1/1] (8.51ns) ---> "%tempResult_0_1 = mul nsw i32 %tmp_9, %tmp_8" [vector_mult/vector_mult.cpp:9] ---> Core 16 'Mul' ST_24 : Operation 192 [1/1] (8.51ns) ---> "%tempResult_1_1 = mul nsw i32 %tmp_10, %tmp_s" [vector_mult/vector_mult.cpp:9] ---> Core 16 'Mul' : 3.70ns ST_25 : Operation 193 [1/1] (0.00ns) ---> "%empty_7 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 2, i64 2, i64 2) nounwind" ST_25 : Operation 194 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecLoopName([17 x i8]* @p_str5) nounwind" [vector_mult/vector_mult.cpp:10] ST_25 : Operation 195 [1/1] (0.00ns) ---> "%tmp_2 = call i32 (...)* @_ssdm_op_SpecRegionBegin([17 x i8]* @p_str5) nounwind" [vector_mult/vector_mult.cpp:10] ST_25 : Operation 196 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind" [vector_mult/vector_mult.cpp:10] ST_25 : Operation 197 [1/1] (0.95ns) ---> "%sel_tmp5 = icmp eq i2 %newIndex78_t, -2" [vector_mult/vector_mult.cpp:8] ---> Core 25 'Cmp' ST_25 : Operation 198 [1/1] (0.00ns) (grouped into LUT with out node tempResult_0_3_1) ---> "%tempResult_0_3_4 = select i1 %sel_tmp5, i32 %tempResult_0_3, i32 %tempResult_0_3_11" [vector_mult/vector_mult.cpp:8] ---> Core 26 'Sel' ST_25 : Operation 199 [1/1] (0.95ns) ---> "%sel_tmp6 = icmp eq i2 %newIndex78_t, 0" [vector_mult/vector_mult.cpp:8] ---> Core 25 'Cmp' ST_25 : Operation 200 [1/1] (1.37ns) (out node of the LUT) ---> "%tempResult_0_3_1 = select i1 %sel_tmp6, i32 %tempResult_0_3, i32 %tempResult_0_3_4" [vector_mult/vector_mult.cpp:8] ---> Core 26 'Sel' ST_25 : Operation 201 [1/1] (0.00ns) (grouped into LUT with out node tempResult_0_3_6) ---> "%tempResult_0_3_5 = select i1 %sel_tmp5, i32 %tempResult_0_3_11, i32 %tempResult_0_2_s" [vector_mult/vector_mult.cpp:8] ---> Core 26 'Sel' ST_25 : Operation 202 [1/1] (1.37ns) (out node of the LUT) ---> "%tempResult_0_3_6 = select i1 %sel_tmp6, i32 %tempResult_0_2_s, i32 %tempResult_0_3_5" [vector_mult/vector_mult.cpp:8] ---> Core 26 'Sel' ST_25 : Operation 203 [1/1] (1.37ns) ---> "%tempResult_0_3_8 = select i1 %sel_tmp6, i32 %tempResult_0_3_11, i32 %tempResult_0_3_7" [vector_mult/vector_mult.cpp:8] ---> Core 26 'Sel' ST_25 : Operation 204 [1/1] (0.00ns) ---> "%empty_8 = call i32 (...)* @_ssdm_op_SpecRegionEnd([17 x i8]* @p_str5, i32 %tmp_2) nounwind" [vector_mult/vector_mult.cpp:9] ST_25 : Operation 205 [1/1] (0.00ns) (grouped into LUT with out node tempResult_1_3_1) ---> "%tempResult_1_3_4 = select i1 %sel_tmp5, i32 %tempResult_1_3, i32 %tempResult_1_3_11" [vector_mult/vector_mult.cpp:8] ---> Core 26 'Sel' ST_25 : Operation 206 [1/1] (1.37ns) (out node of the LUT) ---> "%tempResult_1_3_1 = select i1 %sel_tmp6, i32 %tempResult_1_3, i32 %tempResult_1_3_4" [vector_mult/vector_mult.cpp:8] ---> Core 26 'Sel' ST_25 : Operation 207 [1/1] (0.00ns) (grouped into LUT with out node tempResult_1_3_6) ---> "%tempResult_1_3_5 = select i1 %sel_tmp5, i32 %tempResult_1_3_11, i32 %tempResult_1_2_s" [vector_mult/vector_mult.cpp:8] ---> Core 26 'Sel' ST_25 : Operation 208 [1/1] (1.37ns) (out node of the LUT) ---> "%tempResult_1_3_6 = select i1 %sel_tmp6, i32 %tempResult_1_2_s, i32 %tempResult_1_3_5" [vector_mult/vector_mult.cpp:8] ---> Core 26 'Sel' ST_25 : Operation 209 [1/1] (1.37ns) ---> "%tempResult_1_3_8 = select i1 %sel_tmp6, i32 %tempResult_1_3_11, i32 %tempResult_1_3_7" [vector_mult/vector_mult.cpp:8] ---> Core 26 'Sel' ST_25 : Operation 210 [1/1] (1.37ns) (out node of the LUT) ---> "%tempResult_0_3_2 = select i1 %cond, i32 %tempResult_0_3_1, i32 %tempResult_0_1" [vector_mult/vector_mult.cpp:9] ---> Core 26 'Sel' ST_25 : Operation 211 [1/1] (1.37ns) ---> "%tempResult_0_3_10 = select i1 %cond, i32 %tempResult_0_1, i32 %tempResult_0_1_s" [vector_mult/vector_mult.cpp:9] ---> Core 26 'Sel' ST_25 : Operation 212 [1/1] (1.37ns) (out node of the LUT) ---> "%tempResult_1_3_2 = select i1 %cond, i32 %tempResult_1_3_1, i32 %tempResult_1_1" [vector_mult/vector_mult.cpp:9] ---> Core 26 'Sel' ST_25 : Operation 213 [1/1] (1.37ns) ---> "%tempResult_1_3_10 = select i1 %cond, i32 %tempResult_1_1, i32 %tempResult_1_1_s" [vector_mult/vector_mult.cpp:9] ---> Core 26 'Sel' ST_25 : Operation 214 [1/1] (0.00ns) ---> "br label %burst.rd.end4.0" [vector_mult/vector_mult.cpp:8] : 8.75ns ST_26 : Operation 215 [1/1] (8.75ns) ---> "%gmem_addr_wr_req = call i1 @_ssdm_op_WriteReq.m_axi.i32P(i32* %gmem_addr, i32 8)" [vector_mult/vector_mult.cpp:10] ---> Core 9 'm_axi' ST_26 : Operation 216 [1/1] (1.76ns) ---> "br label %burst.wr.header" : 3.33ns ST_27 : Operation 217 [1/1] (0.00ns) ---> "%indvar1 = phi i4 [ %indvar_next1, %burst.wr.body_ifconv ], [ 0, %burst.wr.header.preheader ]" ST_27 : Operation 218 [1/1] (1.30ns) ---> "%exitcond2 = icmp eq i4 %indvar1, -8" ---> Core 25 'Cmp' ST_27 : Operation 219 [1/1] (1.73ns) ---> "%indvar_next1 = add i4 %indvar1, 1" ---> Core 14 'AddSub' ST_27 : Operation 220 [1/1] (0.00ns) ---> "br i1 %exitcond2, label %memcpy.tail, label %burst.wr.body_ifconv" ST_27 : Operation 221 [1/1] (0.00ns) ---> "%tmp_15 = trunc i4 %indvar1 to i1" ST_27 : Operation 222 [1/1] (0.00ns) ---> "%newIndex30_t = call i2 @_ssdm_op_PartSelect.i2.i4.i32.i32(i4 %indvar1, i32 1, i32 2)" ST_27 : Operation 223 [1/1] (1.95ns) ---> "%tmp_11 = call i32 @_ssdm_op_Mux.ap_auto.4i32.i2(i32 %tempResult_1_3_7, i32 %tempResult_1_1_s, i32 %tempResult_1_2_s, i32 %tempResult_1_3, i2 %newIndex30_t) nounwind" [vector_mult/vector_mult.cpp:8] ---> Core 31 'MuxnS' ST_27 : Operation 224 [1/1] (1.95ns) ---> "%tmp_12 = call i32 @_ssdm_op_Mux.ap_auto.4i32.i2(i32 %tempResult_0_3_7, i32 %tempResult_0_1_s, i32 %tempResult_0_2_s, i32 %tempResult_0_3, i2 %newIndex30_t) nounwind" [vector_mult/vector_mult.cpp:8] ---> Core 31 'MuxnS' ST_27 : Operation 225 [1/1] (1.37ns) ---> "%tempResult_load_phi = select i1 %tmp_15, i32 %tmp_11, i32 %tmp_12" [vector_mult/vector_mult.cpp:10] ---> Core 26 'Sel' : 8.75ns ST_28 : Operation 226 [1/1] (0.00ns) ---> "%empty_9 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 8, i64 8, i64 8) nounwind" ST_28 : Operation 227 [1/1] (0.00ns) ---> "%burstwrite_rbegin = call i32 (...)* @_ssdm_op_SpecRegionBegin([18 x i8]* @burstwrite_OC_region) nounwind" ST_28 : Operation 228 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecPipeline(i32 1, i32 1, i32 1, i32 0, [1 x i8]* @p_str8)" ST_28 : Operation 229 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecLoopName([29 x i8]* @memcpy_OC_result_OC_s)" ST_28 : Operation 230 [1/1] (8.75ns) ---> "call void @_ssdm_op_Write.m_axi.i32P(i32* %gmem_addr, i32 %tempResult_load_phi, i4 -1)" [vector_mult/vector_mult.cpp:10] ---> Core 9 'm_axi' ST_28 : Operation 231 [1/1] (0.00ns) ---> "%burstwrite_rend = call i32 (...)* @_ssdm_op_SpecRegionEnd([18 x i8]* @burstwrite_OC_region, i32 %burstwrite_rbegin) nounwind" ST_28 : Operation 232 [1/1] (0.00ns) ---> "br label %burst.wr.header" : 8.75ns ST_29 : Operation 233 [5/5] (8.75ns) ---> "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %gmem_addr)" [vector_mult/vector_mult.cpp:10] ---> Core 9 'm_axi' : 8.75ns ST_30 : Operation 234 [4/5] (8.75ns) ---> "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %gmem_addr)" [vector_mult/vector_mult.cpp:10] ---> Core 9 'm_axi' : 8.75ns ST_31 : Operation 235 [3/5] (8.75ns) ---> "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %gmem_addr)" [vector_mult/vector_mult.cpp:10] ---> Core 9 'm_axi' : 8.75ns ST_32 : Operation 236 [2/5] (8.75ns) ---> "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %gmem_addr)" [vector_mult/vector_mult.cpp:10] ---> Core 9 'm_axi' : 8.75ns ST_33 : Operation 237 [1/5] (8.75ns) ---> "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %gmem_addr)" [vector_mult/vector_mult.cpp:10] ---> Core 9 'm_axi' ST_33 : Operation 238 [1/1] (0.00ns) ---> "ret void" [vector_mult/vector_mult.cpp:11] ============================================================ + Verbose Summary: Binding ============================================================ STG Binding: ---------------- STG Properties BEGIN ---------------- - Is combinational: 0 - Is one-state seq: 0 - Is datapath-only: 0 - Is pipelined: 0 - Is top level: 1 Port [ Return ] is wired: 1; IO mode=ap_ctrl_hs:ce=0 Port [ gmem]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=2; type=4; pingpong=0; private_global=0; IO mode=m_axi:ce=0 Port [ A]: wired=1; compound=0; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=0; pingpong=0; private_global=0; IO mode=ap_none:ce=0 Port [ B]: wired=1; compound=0; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=0; pingpong=0; private_global=0; IO mode=ap_none:ce=0 Port [ result]: wired=1; compound=0; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=0; pingpong=0; private_global=0; IO mode=ap_none:ce=0 ---------------- STG Properties END ------------------ ---------------- Datapath Model BEGIN ---------------- result_read (read ) [ 0000000000000000000000000000000000] B_read (read ) [ 0000000000000000000000000000000000] A_read (read ) [ 0000000000000000000000000000000000] result5 (partselect ) [ 0011111110000000000000000000000000] B3 (partselect ) [ 0011111110000000000000000000000000] A1 (partselect ) [ 0010000000000000000000000000000000] tmp_13 (zext ) [ 0000000000000000000000000000000000] gmem_addr_2 (getelementptr ) [ 0001111111110000000000000000000000] tmp_1 (zext ) [ 0000000000000000000000000000000000] gmem_addr (getelementptr ) [ 0000000001111111111111111111111111] tmp_5 (zext ) [ 0000000000000000000000000000000000] gmem_addr_1 (getelementptr ) [ 0000000001111111111111000000000000] StgValue_52 (specbitsmap ) [ 0000000000000000000000000000000000] StgValue_53 (spectopmodule ) [ 0000000000000000000000000000000000] StgValue_54 (specinterface ) [ 0000000000000000000000000000000000] StgValue_55 (specinterface ) [ 0000000000000000000000000000000000] StgValue_56 (specinterface ) [ 0000000000000000000000000000000000] StgValue_57 (specinterface ) [ 0000000000000000000000000000000000] StgValue_58 (specinterface ) [ 0000000000000000000000000000000000] gmem_addr_2_rd_req (readreq ) [ 0000000000000000000000000000000000] StgValue_60 (br ) [ 0000000011110000000000000000000000] tempA_1_3_s (phi ) [ 0000000001111111111111111100000000] tempA_1_2_s (phi ) [ 0000000001111111111111111100000000] tempA_1_3_7 (phi ) [ 0000000001111111111111111100000000] tempA_1_3_10 (phi ) [ 0000000001111111111111111100000000] tempA_0_3_s (phi ) [ 0000000001111111111111111100000000] tempA_0_2_s (phi ) [ 0000000001111111111111111100000000] tempA_1_3_12 (phi ) [ 0000000001111111111111111100000000] tempA_1_3_13 (phi ) [ 0000000001111111111111111100000000] indvar (phi ) [ 0000000001000000000000000000000000] exitcond1 (icmp ) [ 0000000001110000000000000000000000] indvar_next (add ) [ 0000000011110000000000000000000000] StgValue_72 (br ) [ 0000000000000000000000000000000000] tmp (trunc ) [ 0000000001110000000000000000000000] newIndex84_t (partselect ) [ 0000000001110000000000000000000000] tempA_1_3_23 (read ) [ 0000000001010000000000000000000000] empty (speclooptripcount) [ 0000000000000000000000000000000000] burstread_rbegin (specregionbegin ) [ 0000000000000000000000000000000000] StgValue_78 (specpipeline ) [ 0000000000000000000000000000000000] StgValue_79 (specloopname ) [ 0000000000000000000000000000000000] sel_tmp (icmp ) [ 0000000000000000000000000000000000] tempA_1_3 (select ) [ 0000000000000000000000000000000000] sel_tmp2 (icmp ) [ 0000000000000000000000000000000000] tempA_1_3_3 (select ) [ 0000000000000000000000000000000000] sel_tmp4 (icmp ) [ 0000000000000000000000000000000000] tempA_1_3_2 (select ) [ 0000000000000000000000000000000000] tempA_1_3_4 (select ) [ 0000000000000000000000000000000000] tempA_1_3_5 (select ) [ 0000000000000000000000000000000000] tempA_1_3_6 (select ) [ 0000000000000000000000000000000000] tempA_1_3_8 (select ) [ 0000000000000000000000000000000000] tempA_1_3_9 (select ) [ 0000000000000000000000000000000000] tempA_1_3_11 (select ) [ 0000000000000000000000000000000000] tempA_1_3_14 (select ) [ 0000000000000000000000000000000000] tempA_1_3_1 (select ) [ 0000000011110000000000000000000000] tempA_1_3_15 (select ) [ 0000000011110000000000000000000000] tempA_1_3_16 (select ) [ 0000000011110000000000000000000000] tempA_1_3_17 (select ) [ 0000000011110000000000000000000000] or_cond (or ) [ 0000000000000000000000000000000000] or_cond1 (or ) [ 0000000000000000000000000000000000] or_cond2 (or ) [ 0000000000000000000000000000000000] tempA_1_3_18 (select ) [ 0000000011110000000000000000000000] newSel (select ) [ 0000000000000000000000000000000000] newSel1 (select ) [ 0000000000000000000000000000000000] tempA_1_3_19 (select ) [ 0000000011110000000000000000000000] newSel3 (select ) [ 0000000000000000000000000000000000] tempA_1_3_20 (select ) [ 0000000011110000000000000000000000] tempA_1_3_21 (select ) [ 0000000011110000000000000000000000] burstread_rend (specregionend ) [ 0000000000000000000000000000000000] StgValue_108 (br ) [ 0000000011110000000000000000000000] gmem_addr_1_rd_req (readreq ) [ 0000000000000000000000000000000000] StgValue_116 (br ) [ 0000000000000000001111000000000000] tempB_1_3_s (phi ) [ 0000000000000000000111111100000000] tempB_1_2_s (phi ) [ 0000000000000000000111111100000000] tempB_1_3_7 (phi ) [ 0000000000000000000111111100000000] tempB_1_3_10 (phi ) [ 0000000000000000000111111100000000] tempB_0_3_s (phi ) [ 0000000000000000000111111100000000] tempB_0_2_s (phi ) [ 0000000000000000000111111100000000] tempB_1_3_12 (phi ) [ 0000000000000000000111111100000000] tempB_1_3_13 (phi ) [ 0000000000000000000111111100000000] indvar7 (phi ) [ 0000000000000000000100000000000000] exitcond9 (icmp ) [ 0000000000000000000111000000000000] indvar_next8 (add ) [ 0000000000000000001111000000000000] StgValue_128 (br ) [ 0000000000000000000000000000000000] tmp_14 (trunc ) [ 0000000000000000000111000000000000] newIndex58_t (partselect ) [ 0000000000000000000111000000000000] tempB_1_3_23 (read ) [ 0000000000000000000101000000000000] empty_6 (speclooptripcount) [ 0000000000000000000000000000000000] burstread_rbegin1 (specregionbegin ) [ 0000000000000000000000000000000000] StgValue_134 (specpipeline ) [ 0000000000000000000000000000000000] StgValue_135 (specloopname ) [ 0000000000000000000000000000000000] sel_tmp8 (icmp ) [ 0000000000000000000000000000000000] tempB_1_3 (select ) [ 0000000000000000000000000000000000] sel_tmp1 (icmp ) [ 0000000000000000000000000000000000] tempB_1_3_3 (select ) [ 0000000000000000000000000000000000] sel_tmp3 (icmp ) [ 0000000000000000000000000000000000] tempB_1_3_2 (select ) [ 0000000000000000000000000000000000] tempB_1_3_4 (select ) [ 0000000000000000000000000000000000] tempB_1_3_5 (select ) [ 0000000000000000000000000000000000] tempB_1_3_6 (select ) [ 0000000000000000000000000000000000] tempB_1_3_8 (select ) [ 0000000000000000000000000000000000] tempB_1_3_9 (select ) [ 0000000000000000000000000000000000] tempB_1_3_11 (select ) [ 0000000000000000000000000000000000] tempB_1_3_14 (select ) [ 0000000000000000000000000000000000] tempB_1_3_1 (select ) [ 0000000000000000001111000000000000] tempB_1_3_15 (select ) [ 0000000000000000001111000000000000] tempB_1_3_16 (select ) [ 0000000000000000001111000000000000] tempB_1_3_17 (select ) [ 0000000000000000001111000000000000] or_cond7 (or ) [ 0000000000000000000000000000000000] or_cond8 (or ) [ 0000000000000000000000000000000000] or_cond9 (or ) [ 0000000000000000000000000000000000] tempB_1_3_18 (select ) [ 0000000000000000001111000000000000] newSel6 (select ) [ 0000000000000000000000000000000000] newSel7 (select ) [ 0000000000000000000000000000000000] tempB_1_3_19 (select ) [ 0000000000000000001111000000000000] newSel9 (select ) [ 0000000000000000000000000000000000] tempB_1_3_20 (select ) [ 0000000000000000001111000000000000] tempB_1_3_21 (select ) [ 0000000000000000001111000000000000] burstread_rend12 (specregionend ) [ 0000000000000000000000000000000000] StgValue_164 (br ) [ 0000000000000000001111000000000000] StgValue_165 (br ) [ 0000000000000000000000111100000000] tempResult_1_3 (phi ) [ 0000000000000000000000011111100000] tempResult_1_2_s (phi ) [ 0000000000000000000000011111100000] tempResult_1_1_s (phi ) [ 0000000000000000000000011111100000] tempResult_1_3_7 (phi ) [ 0000000000000000000000011111100000] tempResult_0_3 (phi ) [ 0000000000000000000000011111100000] tempResult_0_2_s (phi ) [ 0000000000000000000000011111100000] tempResult_0_1_s (phi ) [ 0000000000000000000000011111100000] tempResult_0_3_7 (phi ) [ 0000000000000000000000011111100000] i (phi ) [ 0000000000000000000000010000000000] exitcond (icmp ) [ 0000000000000000000000011100000000] StgValue_176 (br ) [ 0000000000000000000000000000000000] newIndex78_t (partselect ) [ 0000000000000000000000011100000000] tmp_3 (mux ) [ 0000000000000000000000011000000000] tmp_4 (mux ) [ 0000000000000000000000011000000000] tmp_6 (mux ) [ 0000000000000000000000011000000000] tmp_7 (mux ) [ 0000000000000000000000011000000000] newIndex68_t (or ) [ 0000000000000000000000000000000000] tmp_8 (mux ) [ 0000000000000000000000011000000000] tmp_9 (mux ) [ 0000000000000000000000011000000000] cond (icmp ) [ 0000000000000000000000011100000000] tmp_s (mux ) [ 0000000000000000000000011000000000] tmp_10 (mux ) [ 0000000000000000000000011000000000] i_1_3 (add ) [ 0000000000000000000000111100000000] tempResult_0_3_11 (mul ) [ 0000000000000000000000010100000000] tempResult_1_3_11 (mul ) [ 0000000000000000000000010100000000] tempResult_0_1 (mul ) [ 0000000000000000000000010100000000] tempResult_1_1 (mul ) [ 0000000000000000000000010100000000] empty_7 (speclooptripcount) [ 0000000000000000000000000000000000] StgValue_194 (specloopname ) [ 0000000000000000000000000000000000] tmp_2 (specregionbegin ) [ 0000000000000000000000000000000000] StgValue_196 (specpipeline ) [ 0000000000000000000000000000000000] sel_tmp5 (icmp ) [ 0000000000000000000000000000000000] tempResult_0_3_4 (select ) [ 0000000000000000000000000000000000] sel_tmp6 (icmp ) [ 0000000000000000000000000000000000] tempResult_0_3_1 (select ) [ 0000000000000000000000000000000000] tempResult_0_3_5 (select ) [ 0000000000000000000000000000000000] tempResult_0_3_6 (select ) [ 0000000000000000000000111100000000] tempResult_0_3_8 (select ) [ 0000000000000000000000111100000000] empty_8 (specregionend ) [ 0000000000000000000000000000000000] tempResult_1_3_4 (select ) [ 0000000000000000000000000000000000] tempResult_1_3_1 (select ) [ 0000000000000000000000000000000000] tempResult_1_3_5 (select ) [ 0000000000000000000000000000000000] tempResult_1_3_6 (select ) [ 0000000000000000000000111100000000] tempResult_1_3_8 (select ) [ 0000000000000000000000111100000000] tempResult_0_3_2 (select ) [ 0000000000000000000000111100000000] tempResult_0_3_10 (select ) [ 0000000000000000000000111100000000] tempResult_1_3_2 (select ) [ 0000000000000000000000111100000000] tempResult_1_3_10 (select ) [ 0000000000000000000000111100000000] StgValue_214 (br ) [ 0000000000000000000000111100000000] gmem_addr_wr_req (writereq ) [ 0000000000000000000000000000000000] StgValue_216 (br ) [ 0000000000000000000000000011100000] indvar1 (phi ) [ 0000000000000000000000000001000000] exitcond2 (icmp ) [ 0000000000000000000000000001100000] indvar_next1 (add ) [ 0000000000000000000000000011100000] StgValue_220 (br ) [ 0000000000000000000000000000000000] tmp_15 (trunc ) [ 0000000000000000000000000000000000] newIndex30_t (partselect ) [ 0000000000000000000000000000000000] tmp_11 (mux ) [ 0000000000000000000000000000000000] tmp_12 (mux ) [ 0000000000000000000000000000000000] tempResult_load_phi (select ) [ 0000000000000000000000000001100000] empty_9 (speclooptripcount) [ 0000000000000000000000000000000000] burstwrite_rbegin (specregionbegin ) [ 0000000000000000000000000000000000] StgValue_228 (specpipeline ) [ 0000000000000000000000000000000000] StgValue_229 (specloopname ) [ 0000000000000000000000000000000000] StgValue_230 (write ) [ 0000000000000000000000000000000000] burstwrite_rend (specregionend ) [ 0000000000000000000000000000000000] StgValue_232 (br ) [ 0000000000000000000000000011100000] gmem_addr_wr_resp (writeresp ) [ 0000000000000000000000000000000000] StgValue_238 (ret ) [ 0000000000000000000000000000000000] ---------------- Datapath Model END ------------------ * FSMD analyzer results: - Output states: Port: gmem | {26 28 29 30 31 32 33 } - Input state : Port: vector_mult : gmem | {2 3 4 5 6 7 8 10 12 13 14 15 16 17 18 20 } Port: vector_mult : A | {1 } Port: vector_mult : B | {1 } Port: vector_mult : result | {1 } - Chain level: State 1 State 2 gmem_addr_2 : 1 gmem_addr_2_rd_req : 2 State 3 State 4 State 5 State 6 State 7 State 8 gmem_addr : 1 gmem_addr_1 : 1 State 9 exitcond1 : 1 indvar_next : 1 StgValue_72 : 2 tmp : 1 newIndex84_t : 1 State 10 State 11 tempA_1_3 : 1 tempA_1_3_3 : 2 tempA_1_3_2 : 3 tempA_1_3_4 : 1 tempA_1_3_5 : 2 tempA_1_3_6 : 3 tempA_1_3_8 : 1 tempA_1_3_9 : 2 tempA_1_3_11 : 1 tempA_1_3_14 : 1 tempA_1_3_1 : 4 tempA_1_3_15 : 4 tempA_1_3_16 : 3 tempA_1_3_17 : 2 or_cond : 1 or_cond1 : 1 or_cond2 : 1 tempA_1_3_18 : 1 newSel : 1 newSel1 : 1 tempA_1_3_19 : 2 newSel3 : 1 tempA_1_3_20 : 1 tempA_1_3_21 : 2 burstread_rend : 1 State 12 State 13 State 14 State 15 State 16 State 17 State 18 State 19 exitcond9 : 1 indvar_next8 : 1 StgValue_128 : 2 tmp_14 : 1 newIndex58_t : 1 State 20 State 21 tempB_1_3 : 1 tempB_1_3_3 : 2 tempB_1_3_2 : 3 tempB_1_3_4 : 1 tempB_1_3_5 : 2 tempB_1_3_6 : 3 tempB_1_3_8 : 1 tempB_1_3_9 : 2 tempB_1_3_11 : 1 tempB_1_3_14 : 1 tempB_1_3_1 : 4 tempB_1_3_15 : 4 tempB_1_3_16 : 3 tempB_1_3_17 : 2 or_cond7 : 1 or_cond8 : 1 or_cond9 : 1 tempB_1_3_18 : 1 newSel6 : 1 newSel7 : 1 tempB_1_3_19 : 2 newSel9 : 1 tempB_1_3_20 : 1 tempB_1_3_21 : 2 burstread_rend12 : 1 State 22 State 23 exitcond : 1 StgValue_176 : 2 newIndex78_t : 1 tmp_3 : 2 tmp_4 : 2 tmp_6 : 2 tmp_7 : 2 newIndex68_t : 2 tmp_8 : 2 tmp_9 : 2 cond : 2 tmp_s : 2 tmp_10 : 2 i_1_3 : 1 State 24 State 25 tempResult_0_3_4 : 1 tempResult_0_3_1 : 2 tempResult_0_3_5 : 1 tempResult_0_3_6 : 2 tempResult_0_3_8 : 1 empty_8 : 1 tempResult_1_3_4 : 1 tempResult_1_3_1 : 2 tempResult_1_3_5 : 1 tempResult_1_3_6 : 2 tempResult_1_3_8 : 1 tempResult_0_3_2 : 3 tempResult_1_3_2 : 3 State 26 State 27 exitcond2 : 1 indvar_next1 : 1 StgValue_220 : 2 tmp_15 : 1 newIndex30_t : 1 tmp_11 : 2 tmp_12 : 2 tempResult_load_phi : 3 State 28 burstwrite_rend : 1 State 29 State 30 State 31 State 32 State 33 ============================================================ + Verbose Summary: Datapath Resource usage ============================================================ * Functional unit list: |----------|-----------------------------|---------|---------|---------| | Operation| Functional Unit | DSP48E | FF | LUT | |----------|-----------------------------|---------|---------|---------| | | tempA_1_3_fu_599 | 0 | 0 | 32 | | | tempA_1_3_3_fu_611 | 0 | 0 | 32 | | | tempA_1_3_2_fu_624 | 0 | 0 | 32 | | | tempA_1_3_4_fu_632 | 0 | 0 | 32 | | | tempA_1_3_5_fu_639 | 0 | 0 | 32 | | | tempA_1_3_6_fu_647 | 0 | 0 | 32 | | | tempA_1_3_8_fu_655 | 0 | 0 | 32 | | | tempA_1_3_9_fu_662 | 0 | 0 | 32 | | | tempA_1_3_11_fu_670 | 0 | 0 | 32 | | | tempA_1_3_14_fu_677 | 0 | 0 | 32 | | | tempA_1_3_1_fu_684 | 0 | 0 | 32 | | | tempA_1_3_15_fu_691 | 0 | 0 | 32 | | | tempA_1_3_16_fu_698 | 0 | 0 | 32 | | | tempA_1_3_17_fu_705 | 0 | 0 | 32 | | | tempA_1_3_18_fu_729 | 0 | 0 | 32 | | | newSel_fu_736 | 0 | 0 | 32 | | | newSel1_fu_743 | 0 | 0 | 32 | | | tempA_1_3_19_fu_751 | 0 | 0 | 32 | | | newSel3_fu_759 | 0 | 0 | 32 | | | tempA_1_3_20_fu_766 | 0 | 0 | 32 | | | tempA_1_3_21_fu_774 | 0 | 0 | 32 | | | tempB_1_3_fu_812 | 0 | 0 | 32 | | | tempB_1_3_3_fu_824 | 0 | 0 | 32 | | | tempB_1_3_2_fu_837 | 0 | 0 | 32 | | | tempB_1_3_4_fu_845 | 0 | 0 | 32 | | | tempB_1_3_5_fu_852 | 0 | 0 | 32 | | | tempB_1_3_6_fu_860 | 0 | 0 | 32 | | | tempB_1_3_8_fu_868 | 0 | 0 | 32 | | select | tempB_1_3_9_fu_875 | 0 | 0 | 32 | | | tempB_1_3_11_fu_883 | 0 | 0 | 32 | | | tempB_1_3_14_fu_890 | 0 | 0 | 32 | | | tempB_1_3_1_fu_897 | 0 | 0 | 32 | | | tempB_1_3_15_fu_904 | 0 | 0 | 32 | | | tempB_1_3_16_fu_911 | 0 | 0 | 32 | | | tempB_1_3_17_fu_918 | 0 | 0 | 32 | | | tempB_1_3_18_fu_942 | 0 | 0 | 32 | | | newSel6_fu_949 | 0 | 0 | 32 | | | newSel7_fu_956 | 0 | 0 | 32 | | | tempB_1_3_19_fu_964 | 0 | 0 | 32 | | | newSel9_fu_972 | 0 | 0 | 32 | | | tempB_1_3_20_fu_979 | 0 | 0 | 32 | | | tempB_1_3_21_fu_987 | 0 | 0 | 32 | | | tempResult_0_3_4_fu_1161 | 0 | 0 | 32 | | | tempResult_0_3_1_fu_1173 | 0 | 0 | 32 | | | tempResult_0_3_5_fu_1181 | 0 | 0 | 32 | | | tempResult_0_3_6_fu_1188 | 0 | 0 | 32 | | | tempResult_0_3_8_fu_1196 | 0 | 0 | 32 | | | tempResult_1_3_4_fu_1203 | 0 | 0 | 32 | | | tempResult_1_3_1_fu_1210 | 0 | 0 | 32 | | | tempResult_1_3_5_fu_1218 | 0 | 0 | 32 | | | tempResult_1_3_6_fu_1225 | 0 | 0 | 32 | | | tempResult_1_3_8_fu_1233 | 0 | 0 | 32 | | | tempResult_0_3_2_fu_1240 | 0 | 0 | 32 | | | tempResult_0_3_10_fu_1246 | 0 | 0 | 32 | | | tempResult_1_3_2_fu_1252 | 0 | 0 | 32 | | | tempResult_1_3_10_fu_1258 | 0 | 0 | 32 | | | tempResult_load_phi_fu_1318 | 0 | 0 | 32 | |----------|-----------------------------|---------|---------|---------| | | tmp_3_fu_1010 | 0 | 0 | 21 | | | tmp_4_fu_1024 | 0 | 0 | 21 | | | tmp_6_fu_1038 | 0 | 0 | 21 | | | tmp_7_fu_1052 | 0 | 0 | 21 | | mux | tmp_8_fu_1072 | 0 | 0 | 21 | | | tmp_9_fu_1086 | 0 | 0 | 21 | | | tmp_s_fu_1106 | 0 | 0 | 21 | | | tmp_10_fu_1120 | 0 | 0 | 21 | | | tmp_11_fu_1290 | 0 | 0 | 21 | | | tmp_12_fu_1304 | 0 | 0 | 21 | |----------|-----------------------------|---------|---------|---------| | | exitcond1_fu_568 | 0 | 0 | 9 | | | sel_tmp_fu_594 | 0 | 0 | 8 | | | sel_tmp2_fu_606 | 0 | 0 | 8 | | | sel_tmp4_fu_619 | 0 | 0 | 8 | | | exitcond9_fu_781 | 0 | 0 | 9 | | | sel_tmp8_fu_807 | 0 | 0 | 8 | | icmp | sel_tmp1_fu_819 | 0 | 0 | 8 | | | sel_tmp3_fu_832 | 0 | 0 | 8 | | | exitcond_fu_994 | 0 | 0 | 9 | | | cond_fu_1100 | 0 | 0 | 8 | | | sel_tmp5_fu_1156 | 0 | 0 | 8 | | | sel_tmp6_fu_1168 | 0 | 0 | 8 | | | exitcond2_fu_1264 | 0 | 0 | 9 | |----------|-----------------------------|---------|---------|---------| | | tempResult_0_3_11_fu_1140 | 3 | 0 | 20 | | mul | tempResult_1_3_11_fu_1144 | 3 | 0 | 20 | | | tempResult_0_1_fu_1148 | 3 | 0 | 20 | | | tempResult_1_1_fu_1152 | 3 | 0 | 20 | |----------|-----------------------------|---------|---------|---------| | | indvar_next_fu_574 | 0 | 0 | 13 | | add | indvar_next8_fu_787 | 0 | 0 | 13 | | | i_1_3_fu_1134 | 0 | 0 | 13 | | | indvar_next1_fu_1270 | 0 | 0 | 13 | |----------|-----------------------------|---------|---------|---------| | | or_cond_fu_712 | 0 | 0 | 8 | | | or_cond1_fu_717 | 0 | 0 | 8 | | | or_cond2_fu_723 | 0 | 0 | 8 | | or | or_cond7_fu_925 | 0 | 0 | 8 | | | or_cond8_fu_930 | 0 | 0 | 8 | | | or_cond9_fu_936 | 0 | 0 | 8 | | | newIndex68_t_fu_1066 | 0 | 0 | 0 | |----------|-----------------------------|---------|---------|---------| | | result_read_read_fu_120 | 0 | 0 | 0 | | | B_read_read_fu_126 | 0 | 0 | 0 | | read | A_read_read_fu_132 | 0 | 0 | 0 | | | tempA_1_3_23_read_fu_145 | 0 | 0 | 0 | | | tempB_1_3_23_read_fu_157 | 0 | 0 | 0 | |----------|-----------------------------|---------|---------|---------| | readreq | grp_readreq_fu_138 | 0 | 0 | 0 | | | grp_readreq_fu_150 | 0 | 0 | 0 | |----------|-----------------------------|---------|---------|---------| | writeresp| grp_writeresp_fu_162 | 0 | 0 | 0 | |----------|-----------------------------|---------|---------|---------| | write | StgValue_230_write_fu_169 | 0 | 0 | 0 | |----------|-----------------------------|---------|---------|---------| | | result5_fu_510 | 0 | 0 | 0 | | | B3_fu_520 | 0 | 0 | 0 | | | A1_fu_530 | 0 | 0 | 0 | |partselect| newIndex84_t_fu_584 | 0 | 0 | 0 | | | newIndex58_t_fu_797 | 0 | 0 | 0 | | | newIndex78_t_fu_1000 | 0 | 0 | 0 | | | newIndex30_t_fu_1280 | 0 | 0 | 0 | |----------|-----------------------------|---------|---------|---------| | | tmp_13_fu_540 | 0 | 0 | 0 | | zext | tmp_1_fu_550 | 0 | 0 | 0 | | | tmp_5_fu_559 | 0 | 0 | 0 | |----------|-----------------------------|---------|---------|---------| | | tmp_fu_580 | 0 | 0 | 0 | | trunc | tmp_14_fu_793 | 0 | 0 | 0 | | | tmp_15_fu_1276 | 0 | 0 | 0 | |----------|-----------------------------|---------|---------|---------| | Total | | 12 | 0 | 2322 | |----------|-----------------------------|---------|---------|---------| Memories: N/A * Register list: +----------------------------+--------+ | | FF | +----------------------------+--------+ | A1_reg_1336 | 30 | | B3_reg_1331 | 30 | | cond_reg_1555 | 1 | | exitcond1_reg_1359 | 1 | | exitcond2_reg_1644 | 1 | | exitcond9_reg_1437 | 1 | | exitcond_reg_1515 | 1 | | gmem_addr_1_reg_1353 | 32 | | gmem_addr_2_reg_1341 | 32 | | gmem_addr_reg_1347 | 32 | | i_1_3_reg_1573 | 4 | | i_reg_488 | 4 | | indvar1_reg_499 | 4 | | indvar7_reg_381 | 4 | | indvar_next1_reg_1648 | 4 | | indvar_next8_reg_1441 | 4 | | indvar_next_reg_1363 | 4 | | indvar_reg_274 | 4 | | newIndex58_t_reg_1456 | 2 | | newIndex78_t_reg_1519 | 2 | | newIndex84_t_reg_1378 | 2 | | result5_reg_1326 | 30 | | tempA_0_2_s_reg_238 | 32 | | tempA_0_3_s_reg_226 | 32 | | tempA_1_2_s_reg_190 | 32 | | tempA_1_3_10_reg_214 | 32 | | tempA_1_3_12_reg_250 | 32 | | tempA_1_3_13_reg_262 | 32 | | tempA_1_3_15_reg_1402 | 32 | | tempA_1_3_16_reg_1407 | 32 | | tempA_1_3_17_reg_1412 | 32 | | tempA_1_3_18_reg_1417 | 32 | | tempA_1_3_19_reg_1422 | 32 | | tempA_1_3_1_reg_1397 | 32 | | tempA_1_3_20_reg_1427 | 32 | | tempA_1_3_21_reg_1432 | 32 | | tempA_1_3_23_reg_1385 | 32 | | tempA_1_3_7_reg_202 | 32 | | tempA_1_3_s_reg_178 | 32 | | tempB_0_2_s_reg_345 | 32 | | tempB_0_3_s_reg_333 | 32 | | tempB_1_2_s_reg_297 | 32 | | tempB_1_3_10_reg_321 | 32 | | tempB_1_3_12_reg_357 | 32 | | tempB_1_3_13_reg_369 | 32 | | tempB_1_3_15_reg_1480 | 32 | | tempB_1_3_16_reg_1485 | 32 | | tempB_1_3_17_reg_1490 | 32 | | tempB_1_3_18_reg_1495 | 32 | | tempB_1_3_19_reg_1500 | 32 | | tempB_1_3_1_reg_1475 | 32 | | tempB_1_3_20_reg_1505 | 32 | | tempB_1_3_21_reg_1510 | 32 | | tempB_1_3_23_reg_1463 | 32 | | tempB_1_3_7_reg_309 | 32 | | tempB_1_3_s_reg_285 | 32 | | tempResult_0_1_reg_1592 | 32 | | tempResult_0_1_s_reg_464 | 32 | | tempResult_0_2_s_reg_452 | 32 | | tempResult_0_3_10_reg_1629 | 32 | | tempResult_0_3_11_reg_1578 | 32 | | tempResult_0_3_2_reg_1624 | 32 | | tempResult_0_3_6_reg_1604 | 32 | | tempResult_0_3_7_reg_476 | 32 | | tempResult_0_3_8_reg_1609 | 32 | | tempResult_0_3_reg_440 | 32 | | tempResult_1_1_reg_1598 | 32 | | tempResult_1_1_s_reg_416 | 32 | | tempResult_1_2_s_reg_404 | 32 | | tempResult_1_3_10_reg_1639 | 32 | | tempResult_1_3_11_reg_1585 | 32 | | tempResult_1_3_2_reg_1634 | 32 | | tempResult_1_3_6_reg_1614 | 32 | | tempResult_1_3_7_reg_428 | 32 | | tempResult_1_3_8_reg_1619 | 32 | | tempResult_1_3_reg_392 | 32 | |tempResult_load_phi_reg_1653| 32 | | tmp_10_reg_1568 | 32 | | tmp_14_reg_1446 | 1 | | tmp_3_reg_1525 | 32 | | tmp_4_reg_1530 | 32 | | tmp_6_reg_1535 | 32 | | tmp_7_reg_1540 | 32 | | tmp_8_reg_1545 | 32 | | tmp_9_reg_1550 | 32 | | tmp_reg_1368 | 1 | | tmp_s_reg_1563 | 32 | +----------------------------+--------+ | Total | 2247 | +----------------------------+--------+ * Multiplexer (MUX) list: |--------------------------|------|------|------|--------||---------||---------| | Comp | Pin | Size | BW | S x BW || Delay || LUT | |--------------------------|------|------|------|--------||---------||---------| | grp_readreq_fu_138 | p1 | 2 | 32 | 64 || 9 | | grp_writeresp_fu_162 | p0 | 2 | 1 | 2 | | tempA_1_3_s_reg_178 | p0 | 2 | 32 | 64 || 9 | | tempA_1_2_s_reg_190 | p0 | 2 | 32 | 64 || 9 | | tempA_1_3_7_reg_202 | p0 | 2 | 32 | 64 || 9 | | tempA_1_3_10_reg_214 | p0 | 2 | 32 | 64 || 9 | | tempA_0_3_s_reg_226 | p0 | 2 | 32 | 64 || 9 | | tempA_0_2_s_reg_238 | p0 | 2 | 32 | 64 || 9 | | tempA_1_3_12_reg_250 | p0 | 2 | 32 | 64 || 9 | | tempA_1_3_13_reg_262 | p0 | 2 | 32 | 64 || 9 | | tempB_1_3_s_reg_285 | p0 | 2 | 32 | 64 || 9 | | tempB_1_2_s_reg_297 | p0 | 2 | 32 | 64 || 9 | | tempB_1_3_7_reg_309 | p0 | 2 | 32 | 64 || 9 | | tempB_1_3_10_reg_321 | p0 | 2 | 32 | 64 || 9 | | tempB_0_3_s_reg_333 | p0 | 2 | 32 | 64 || 9 | | tempB_0_2_s_reg_345 | p0 | 2 | 32 | 64 || 9 | | tempB_1_3_12_reg_357 | p0 | 2 | 32 | 64 || 9 | | tempB_1_3_13_reg_369 | p0 | 2 | 32 | 64 || 9 | | tempResult_1_3_reg_392 | p0 | 2 | 32 | 64 || 9 | | tempResult_1_2_s_reg_404 | p0 | 2 | 32 | 64 || 9 | | tempResult_1_1_s_reg_416 | p0 | 2 | 32 | 64 || 9 | | tempResult_1_3_7_reg_428 | p0 | 2 | 32 | 64 || 9 | | tempResult_0_3_reg_440 | p0 | 2 | 32 | 64 || 9 | | tempResult_0_2_s_reg_452 | p0 | 2 | 32 | 64 || 9 | | tempResult_0_1_s_reg_464 | p0 | 2 | 32 | 64 || 9 | | tempResult_0_3_7_reg_476 | p0 | 2 | 32 | 64 || 9 | |--------------------------|------|------|------|--------||---------||---------| | Total | | | | 1602 || 45.994 || 225 | |--------------------------|------|------|------|--------||---------||---------| * Summary: +-----------+--------+--------+--------+--------+ | | DSP48E | Delay | FF | LUT | +-----------+--------+--------+--------+--------+ | Function | 12 | - | 0 | 2322 | | Memory | - | - | - | - | |Multiplexer| - | 45 | - | 225 | | Register | - | - | 2247 | - | +-----------+--------+--------+--------+--------+ | Total | 12 | 45 | 2247 | 2547 | +-----------+--------+--------+--------+--------+