================================================================ == Vivado HLS Report for 'vector_mult' ================================================================ * Date: Mon Mar 19 10:51:09 2018 * Version: 2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017) * Project: vector_mult * Solution: solution2 * Product family: zynq * Target device: xc7z020clg484-1 ================================================================ == Performance Estimates ================================================================ + Timing (ns): * Summary: +--------+-------+----------+------------+ | Clock | Target| Estimated| Uncertainty| +--------+-------+----------+------------+ |ap_clk | 10.00| 8.75| 1.25| +--------+-------+----------+------------+ + Latency (clock cycles): * Summary: +-----+-----+-----+-----+---------+ | Latency | Interval | Pipeline| | min | max | min | max | Type | +-----+-----+-----+-----+---------+ | 58| 58| 58| 58| none | +-----+-----+-----+-----+---------+ + Detail: * Instance: N/A * Loop: +--------------------------------+-----+-----+----------+-----------+-----------+------+----------+ | | Latency | Iteration| Initiation Interval | Trip | | | Loop Name | min | max | Latency | achieved | target | Count| Pipelined| +--------------------------------+-----+-----+----------+-----------+-----------+------+----------+ |- memcpy.tempA.A | 9| 9| 3| 1| 1| 8| yes | |- memcpy.tempB.B | 9| 9| 3| 1| 1| 8| yes | |- vector_mult_loop | 6| 6| 5| 2| 1| 2| yes | |- memcpy.result.tempResult.gep | 9| 9| 3| 1| 1| 8| yes | +--------------------------------+-----+-----+----------+-----------+-----------+------+----------+ ================================================================ == Utilization Estimates ================================================================ * Summary: +-----------------+---------+-------+--------+-------+ | Name | BRAM_18K| DSP48E| FF | LUT | +-----------------+---------+-------+--------+-------+ |DSP | -| -| -| -| |Expression | -| 6| 0| 294| |FIFO | -| -| -| -| |Instance | 2| -| 662| 812| |Memory | 2| -| 128| 8| |Multiplexer | -| -| -| 495| |Register | -| -| 545| -| +-----------------+---------+-------+--------+-------+ |Total | 4| 6| 1335| 1609| +-----------------+---------+-------+--------+-------+ |Available | 280| 220| 106400| 53200| +-----------------+---------+-------+--------+-------+ |Utilization (%) | 1| 2| 1| 3| +-----------------+---------+-------+--------+-------+ + Detail: * Instance: +------------------------------+----------------------------+---------+-------+-----+-----+ | Instance | Module | BRAM_18K| DSP48E| FF | LUT | +------------------------------+----------------------------+---------+-------+-----+-----+ |vector_mult_AXILiteS_s_axi_U |vector_mult_AXILiteS_s_axi | 0| 0| 150| 232| |vector_mult_gmem_m_axi_U |vector_mult_gmem_m_axi | 2| 0| 512| 580| +------------------------------+----------------------------+---------+-------+-----+-----+ |Total | | 2| 0| 662| 812| +------------------------------+----------------------------+---------+-------+-----+-----+ * DSP48: N/A * Memory: +--------------+----------------------+---------+----+----+------+-----+------+-------------+ | Memory | Module | BRAM_18K| FF | LUT| Words| Bits| Banks| W*Bits*Banks| +--------------+----------------------+---------+----+----+------+-----+------+-------------+ |tempA_U |vector_mult_tempA | 0| 64| 4| 8| 32| 1| 256| |tempB_U |vector_mult_tempA | 0| 64| 4| 8| 32| 1| 256| |tempResult_U |vector_mult_tempRbkb | 2| 0| 0| 8| 32| 1| 256| +--------------+----------------------+---------+----+----+------+-----+------+-------------+ |Total | | 2| 128| 8| 24| 96| 3| 768| +--------------+----------------------+---------+----+----+------+-----+------+-------------+ * FIFO: N/A * Expression: +-----------------------------------+----------+-------+---+----+------------+------------+ | Variable Name | Operation| DSP48E| FF| LUT| Bitwidth P0| Bitwidth P1| +-----------------------------------+----------+-------+---+----+------------+------------+ |grp_fu_381_p2 | * | 3| 0| 20| 32| 32| |grp_fu_387_p2 | * | 3| 0| 20| 32| 32| |i_1_3_fu_545_p2 | + | 0| 0| 13| 3| 4| |indvar_next1_fu_557_p2 | + | 0| 0| 13| 4| 1| |indvar_next8_fu_484_p2 | + | 0| 0| 13| 4| 1| |indvar_next_fu_467_p2 | + | 0| 0| 13| 4| 1| |ap_block_pp0_stage0_11001 | and | 0| 0| 8| 1| 1| |ap_block_pp1_stage0_11001 | and | 0| 0| 8| 1| 1| |ap_block_pp3_stage0_11001 | and | 0| 0| 8| 1| 1| |ap_block_state10_pp0_stage0_iter1 | and | 0| 0| 8| 1| 1| |ap_block_state20_pp1_stage0_iter1 | and | 0| 0| 8| 1| 1| |ap_block_state31_io | and | 0| 0| 8| 1| 1| |ap_condition_329 | and | 0| 0| 8| 1| 1| |ap_condition_348 | and | 0| 0| 8| 1| 1| |exitcond1_fu_461_p2 | icmp | 0| 0| 11| 4| 5| |exitcond2_fu_551_p2 | icmp | 0| 0| 11| 4| 5| |exitcond9_fu_478_p2 | icmp | 0| 0| 11| 4| 5| |exitcond_fu_495_p2 | icmp | 0| 0| 11| 4| 5| |i_1_1_fu_523_p2 | or | 0| 0| 10| 3| 2| |i_1_2_fu_534_p2 | or | 0| 0| 10| 3| 2| |i_1_s_fu_511_p2 | or | 0| 0| 10| 3| 1| |ap_enable_pp0 | xor | 0| 0| 8| 1| 2| |ap_enable_pp1 | xor | 0| 0| 8| 1| 2| |ap_enable_pp2 | xor | 0| 0| 8| 1| 2| |ap_enable_pp3 | xor | 0| 0| 8| 1| 2| |ap_enable_reg_pp0_iter1 | xor | 0| 0| 8| 2| 1| |ap_enable_reg_pp1_iter1 | xor | 0| 0| 8| 2| 1| |ap_enable_reg_pp2_iter1 | xor | 0| 0| 8| 2| 1| |ap_enable_reg_pp3_iter1 | xor | 0| 0| 8| 2| 1| +-----------------------------------+----------+-------+---+----+------------+------------+ |Total | | 6| 0| 294| 124| 116| +-----------------------------------+----------+-------+---+----+------------+------------+ * Multiplexer: +----------------------------------+-----+-----------+-----+-----------+ | Name | LUT | Input Size| Bits| Total Bits| +----------------------------------+-----+-----------+-----+-----------+ |ap_NS_fsm | 129| 28| 1| 28| |ap_enable_reg_pp0_iter1 | 9| 2| 1| 2| |ap_enable_reg_pp0_iter2 | 9| 2| 1| 2| |ap_enable_reg_pp1_iter1 | 9| 2| 1| 2| |ap_enable_reg_pp1_iter2 | 9| 2| 1| 2| |ap_enable_reg_pp2_iter1 | 9| 2| 1| 2| |ap_enable_reg_pp2_iter2 | 9| 2| 1| 2| |ap_enable_reg_pp3_iter1 | 9| 2| 1| 2| |ap_enable_reg_pp3_iter2 | 9| 2| 1| 2| |ap_phi_mux_i_phi_fu_342_p4 | 9| 2| 4| 8| |ap_phi_mux_indvar7_phi_fu_330_p4 | 9| 2| 4| 8| |ap_phi_mux_indvar_phi_fu_318_p4 | 9| 2| 4| 8| |ap_sig_ioackin_gmem_ARREADY | 9| 2| 1| 2| |ap_sig_ioackin_gmem_AWREADY | 9| 2| 1| 2| |ap_sig_ioackin_gmem_WREADY | 9| 2| 1| 2| |gmem_ARADDR | 15| 3| 32| 96| |gmem_blk_n_AR | 9| 2| 1| 2| |gmem_blk_n_AW | 9| 2| 1| 2| |gmem_blk_n_B | 9| 2| 1| 2| |gmem_blk_n_R | 9| 2| 1| 2| |gmem_blk_n_W | 9| 2| 1| 2| |i_reg_338 | 9| 2| 4| 8| |indvar1_reg_350 | 9| 2| 4| 8| |indvar7_reg_326 | 9| 2| 4| 8| |indvar_reg_314 | 9| 2| 4| 8| |reg_361 | 9| 2| 32| 64| |reg_366 | 9| 2| 32| 64| |reg_371 | 9| 2| 32| 64| |reg_376 | 9| 2| 32| 64| |tempA_address0 | 21| 4| 3| 12| |tempA_address1 | 15| 3| 3| 9| |tempB_address0 | 21| 4| 3| 12| |tempB_address1 | 15| 3| 3| 9| |tempResult_address0 | 21| 4| 3| 12| |tempResult_address1 | 15| 3| 3| 9| +----------------------------------+-----+-----------+-----+-----------+ |Total | 495| 106| 223| 531| +----------------------------------+-----+-----------+-----+-----------+ * Register: +------------------------------------+----+----+-----+-----------+ | Name | FF | LUT| Bits| Const Bits| +------------------------------------+----+----+-----+-----------+ |A1_reg_578 | 30| 0| 30| 0| |B3_reg_573 | 30| 0| 30| 0| |ap_CS_fsm | 27| 0| 27| 0| |ap_enable_reg_pp0_iter0 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter1 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter2 | 1| 0| 1| 0| |ap_enable_reg_pp1_iter0 | 1| 0| 1| 0| |ap_enable_reg_pp1_iter1 | 1| 0| 1| 0| |ap_enable_reg_pp1_iter2 | 1| 0| 1| 0| |ap_enable_reg_pp2_iter0 | 1| 0| 1| 0| |ap_enable_reg_pp2_iter1 | 1| 0| 1| 0| |ap_enable_reg_pp2_iter2 | 1| 0| 1| 0| |ap_enable_reg_pp3_iter0 | 1| 0| 1| 0| |ap_enable_reg_pp3_iter1 | 1| 0| 1| 0| |ap_enable_reg_pp3_iter2 | 1| 0| 1| 0| |ap_reg_ioackin_gmem_ARREADY | 1| 0| 1| 0| |ap_reg_ioackin_gmem_AWREADY | 1| 0| 1| 0| |ap_reg_ioackin_gmem_WREADY | 1| 0| 1| 0| |ap_reg_pp0_iter1_exitcond1_reg_601 | 1| 0| 1| 0| |ap_reg_pp0_iter1_indvar_reg_314 | 4| 0| 4| 0| |ap_reg_pp1_iter1_exitcond9_reg_615 | 1| 0| 1| 0| |ap_reg_pp1_iter1_indvar7_reg_326 | 4| 0| 4| 0| |ap_reg_pp2_iter1_exitcond_reg_629 | 1| 0| 1| 0| |ap_reg_pp2_iter1_tmp_2_1_reg_654 | 2| 0| 64| 62| |ap_reg_pp2_iter1_tmp_2_2_reg_669 | 2| 0| 64| 62| |ap_reg_pp2_iter1_tmp_2_3_reg_684 | 1| 0| 64| 63| |ap_reg_pp2_iter1_tmp_s_reg_639 | 4| 0| 64| 60| |ap_reg_pp3_iter1_exitcond2_reg_704 | 1| 0| 1| 0| |exitcond1_reg_601 | 1| 0| 1| 0| |exitcond2_reg_704 | 1| 0| 1| 0| |exitcond9_reg_615 | 1| 0| 1| 0| |exitcond_reg_629 | 1| 0| 1| 0| |gmem_addr_1_read_reg_624 | 32| 0| 32| 0| |gmem_addr_1_reg_595 | 30| 0| 32| 2| |gmem_addr_2_read_reg_610 | 32| 0| 32| 0| |gmem_addr_reg_589 | 30| 0| 32| 2| |i_1_3_reg_699 | 4| 0| 4| 0| |i_reg_338 | 4| 0| 4| 0| |indvar1_reg_350 | 4| 0| 4| 0| |indvar7_reg_326 | 4| 0| 4| 0| |indvar_next8_reg_619 | 4| 0| 4| 0| |indvar_next_reg_605 | 4| 0| 4| 0| |indvar_reg_314 | 4| 0| 4| 0| |reg_361 | 32| 0| 32| 0| |reg_366 | 32| 0| 32| 0| |reg_371 | 32| 0| 32| 0| |reg_376 | 32| 0| 32| 0| |reg_393 | 32| 0| 32| 0| |reg_398 | 32| 0| 32| 0| |result5_reg_568 | 30| 0| 30| 0| |tempResult_load_reg_718 | 32| 0| 32| 0| |tmp_2_1_reg_654 | 2| 0| 64| 62| |tmp_2_2_reg_669 | 2| 0| 64| 62| |tmp_2_3_reg_684 | 1| 0| 64| 63| |tmp_8_reg_633 | 3| 0| 3| 0| |tmp_s_reg_639 | 4| 0| 64| 60| +------------------------------------+----+----+-----+-----------+ |Total | 545| 0| 1043| 498| +------------------------------------+----+----+-----+-----------+ ================================================================ == Interface ================================================================ * Summary: +------------------------+-----+-----+------------+--------------+--------------+ | RTL Ports | Dir | Bits| Protocol | Source Object| C Type | +------------------------+-----+-----+------------+--------------+--------------+ |s_axi_AXILiteS_AWVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_AWREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_AWADDR | in | 6| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WDATA | in | 32| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WSTRB | in | 4| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARADDR | in | 6| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RVALID | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RREADY | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RDATA | out | 32| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RRESP | out | 2| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BVALID | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BREADY | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BRESP | out | 2| s_axi | AXILiteS | scalar | |ap_clk | in | 1| ap_ctrl_hs | vector_mult | return value | |ap_rst_n | in | 1| ap_ctrl_hs | vector_mult | return value | |interrupt | out | 1| ap_ctrl_hs | vector_mult | return value | |m_axi_gmem_AWVALID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_AWREADY | in | 1| m_axi | gmem | pointer | |m_axi_gmem_AWADDR | out | 32| m_axi | gmem | pointer | |m_axi_gmem_AWID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_AWLEN | out | 8| m_axi | gmem | pointer | |m_axi_gmem_AWSIZE | out | 3| m_axi | gmem | pointer | |m_axi_gmem_AWBURST | out | 2| m_axi | gmem | pointer | |m_axi_gmem_AWLOCK | out | 2| m_axi | gmem | pointer | |m_axi_gmem_AWCACHE | out | 4| m_axi | gmem | pointer | |m_axi_gmem_AWPROT | out | 3| m_axi | gmem | pointer | |m_axi_gmem_AWQOS | out | 4| m_axi | gmem | pointer | |m_axi_gmem_AWREGION | out | 4| m_axi | gmem | pointer | |m_axi_gmem_AWUSER | out | 1| m_axi | gmem | pointer | |m_axi_gmem_WVALID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_WREADY | in | 1| m_axi | gmem | pointer | |m_axi_gmem_WDATA | out | 32| m_axi | gmem | pointer | |m_axi_gmem_WSTRB | out | 4| m_axi | gmem | pointer | |m_axi_gmem_WLAST | out | 1| m_axi | gmem | pointer | |m_axi_gmem_WID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_WUSER | out | 1| m_axi | gmem | pointer | |m_axi_gmem_ARVALID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_ARREADY | in | 1| m_axi | gmem | pointer | |m_axi_gmem_ARADDR | out | 32| m_axi | gmem | pointer | |m_axi_gmem_ARID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_ARLEN | out | 8| m_axi | gmem | pointer | |m_axi_gmem_ARSIZE | out | 3| m_axi | gmem | pointer | |m_axi_gmem_ARBURST | out | 2| m_axi | gmem | pointer | |m_axi_gmem_ARLOCK | out | 2| m_axi | gmem | pointer | |m_axi_gmem_ARCACHE | out | 4| m_axi | gmem | pointer | |m_axi_gmem_ARPROT | out | 3| m_axi | gmem | pointer | |m_axi_gmem_ARQOS | out | 4| m_axi | gmem | pointer | |m_axi_gmem_ARREGION | out | 4| m_axi | gmem | pointer | |m_axi_gmem_ARUSER | out | 1| m_axi | gmem | pointer | |m_axi_gmem_RVALID | in | 1| m_axi | gmem | pointer | |m_axi_gmem_RREADY | out | 1| m_axi | gmem | pointer | |m_axi_gmem_RDATA | in | 32| m_axi | gmem | pointer | |m_axi_gmem_RLAST | in | 1| m_axi | gmem | pointer | |m_axi_gmem_RID | in | 1| m_axi | gmem | pointer | |m_axi_gmem_RUSER | in | 1| m_axi | gmem | pointer | |m_axi_gmem_RRESP | in | 2| m_axi | gmem | pointer | |m_axi_gmem_BVALID | in | 1| m_axi | gmem | pointer | |m_axi_gmem_BREADY | out | 1| m_axi | gmem | pointer | |m_axi_gmem_BRESP | in | 2| m_axi | gmem | pointer | |m_axi_gmem_BID | in | 1| m_axi | gmem | pointer | |m_axi_gmem_BUSER | in | 1| m_axi | gmem | pointer | +------------------------+-----+-----+------------+--------------+--------------+