================================================================ == Vivado HLS Report for 'vector_mult' ================================================================ * Date: Mon Mar 19 10:51:09 2018 * Version: 2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017) * Project: vector_mult * Solution: solution2 * Product family: zynq * Target device: xc7z020clg484-1 ================================================================ == Performance Estimates ================================================================ + Timing (ns): * Summary: +--------+-------+----------+------------+ | Clock | Target| Estimated| Uncertainty| +--------+-------+----------+------------+ |ap_clk | 10.00| 8.75| 1.25| +--------+-------+----------+------------+ + Latency (clock cycles): * Summary: +-----+-----+-----+-----+---------+ | Latency | Interval | Pipeline| | min | max | min | max | Type | +-----+-----+-----+-----+---------+ | 58| 58| 58| 58| none | +-----+-----+-----+-----+---------+ + Detail: * Instance: N/A * Loop: +--------------------------------+-----+-----+----------+-----------+-----------+------+----------+ | | Latency | Iteration| Initiation Interval | Trip | | | Loop Name | min | max | Latency | achieved | target | Count| Pipelined| +--------------------------------+-----+-----+----------+-----------+-----------+------+----------+ |- memcpy.tempA.A | 9| 9| 3| 1| 1| 8| yes | |- memcpy.tempB.B | 9| 9| 3| 1| 1| 8| yes | |- vector_mult_loop | 6| 6| 5| 2| 1| 2| yes | |- memcpy.result.tempResult.gep | 9| 9| 3| 1| 1| 8| yes | +--------------------------------+-----+-----+----------+-----------+-----------+------+----------+ ============================================================ + Verbose Summary: Synthesis Manager ============================================================ InlineROM: 1 ExposeGlobal: 0 ============================================================ + Verbose Summary: CDFG Model ============================================================ IsTopModel: 1 ResetActiveHigh: 1 IsCombinational: 0 IsDatapathOnly: 0 HasWiredReturn: 1 HasMFsm: 0 HasVarLatency: 1 IsPipeline: 0 IsRtlPipelined: 0 IsInstanceOverlapped: 0 IsDontTouch: 0 HasImplIP: 0 IsGatedGlobalClock: 0 + Individual pipeline summary: * Pipeline-0: initiation interval (II) = 1, depth = 3 * Pipeline-1: initiation interval (II) = 1, depth = 3 * Pipeline-2: initiation interval (II) = 2, depth = 5 * Pipeline-3: initiation interval (II) = 1, depth = 3 ============================================================ + Verbose Summary: Schedule ============================================================ * Number of FSM states : 36 * Pipeline : 4 Pipeline-0 : II = 1, D = 3, States = { 9 10 11 } Pipeline-1 : II = 1, D = 3, States = { 19 20 21 } Pipeline-2 : II = 2, D = 5, States = { 23 24 25 26 27 } Pipeline-3 : II = 1, D = 3, States = { 29 30 31 } * Dataflow Pipeline: 0 * FSM state transitions: 1 --> 2 / true 2 --> 3 / true 3 --> 4 / true 4 --> 5 / true 5 --> 6 / true 6 --> 7 / true 7 --> 8 / true 8 --> 9 / true 9 --> 12 / (exitcond1) 10 / (!exitcond1) 10 --> 11 / true 11 --> 9 / true 12 --> 13 / true 13 --> 14 / true 14 --> 15 / true 15 --> 16 / true 16 --> 17 / true 17 --> 18 / true 18 --> 19 / true 19 --> 22 / (exitcond9) 20 / (!exitcond9) 20 --> 21 / true 21 --> 19 / true 22 --> 23 / true 23 --> 28 / (exitcond) 24 / (!exitcond) 24 --> 25 / true 25 --> 26 / true 26 --> 27 / true 27 --> 23 / true 28 --> 29 / true 29 --> 32 / (exitcond2) 30 / (!exitcond2) 30 --> 31 / true 31 --> 29 / true 32 --> 33 / true 33 --> 34 / true 34 --> 35 / true 35 --> 36 / true 36 --> * FSM state operations: : 1.00ns ST_1 : Operation 37 [1/1] (1.00ns) ---> "%result_read = call i32 @_ssdm_op_Read.s_axilite.i32(i32 %result)" ---> Core 10 's_axilite' ST_1 : Operation 38 [1/1] (1.00ns) ---> "%B_read = call i32 @_ssdm_op_Read.s_axilite.i32(i32 %B)" ---> Core 10 's_axilite' ST_1 : Operation 39 [1/1] (1.00ns) ---> "%A_read = call i32 @_ssdm_op_Read.s_axilite.i32(i32 %A)" ---> Core 10 's_axilite' ST_1 : Operation 40 [1/1] (0.00ns) ---> "%result5 = call i30 @_ssdm_op_PartSelect.i30.i32.i32.i32(i32 %result_read, i32 2, i32 31)" ST_1 : Operation 41 [1/1] (0.00ns) ---> "%B3 = call i30 @_ssdm_op_PartSelect.i30.i32.i32.i32(i32 %B_read, i32 2, i32 31)" ST_1 : Operation 42 [1/1] (0.00ns) ---> "%A1 = call i30 @_ssdm_op_PartSelect.i30.i32.i32.i32(i32 %A_read, i32 2, i32 31)" ST_1 : Operation 43 [1/1] (0.00ns) ---> "%tempA = alloca [8 x i32], align 16" [vector_mult/vector_mult.cpp:5] ---> Core 37 'RAM' ST_1 : Operation 44 [1/1] (0.00ns) ---> "%tempB = alloca [8 x i32], align 16" [vector_mult/vector_mult.cpp:5] ---> Core 37 'RAM' ST_1 : Operation 45 [1/1] (0.00ns) ---> "%tempResult = alloca [8 x i32], align 16" [vector_mult/vector_mult.cpp:5] ---> Core 37 'RAM' : 8.75ns ST_2 : Operation 46 [1/1] (0.00ns) ---> "%tmp_7 = zext i30 %A1 to i64" ST_2 : Operation 47 [1/1] (0.00ns) ---> "%gmem_addr_2 = getelementptr i32* %gmem, i64 %tmp_7" ST_2 : Operation 48 [7/7] (8.75ns) ---> "%gmem_addr_2_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 8)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' : 8.75ns ST_3 : Operation 49 [6/7] (8.75ns) ---> "%gmem_addr_2_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 8)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' : 8.75ns ST_4 : Operation 50 [5/7] (8.75ns) ---> "%gmem_addr_2_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 8)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' : 8.75ns ST_5 : Operation 51 [4/7] (8.75ns) ---> "%gmem_addr_2_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 8)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' : 8.75ns ST_6 : Operation 52 [3/7] (8.75ns) ---> "%gmem_addr_2_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 8)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' : 8.75ns ST_7 : Operation 53 [2/7] (8.75ns) ---> "%gmem_addr_2_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 8)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' : 8.75ns ST_8 : Operation 54 [1/1] (0.00ns) ---> "%tmp_4 = zext i30 %result5 to i64" ST_8 : Operation 55 [1/1] (0.00ns) ---> "%gmem_addr = getelementptr i32* %gmem, i64 %tmp_4" ST_8 : Operation 56 [1/1] (0.00ns) ---> "%tmp_6 = zext i30 %B3 to i64" ST_8 : Operation 57 [1/1] (0.00ns) ---> "%gmem_addr_1 = getelementptr i32* %gmem, i64 %tmp_6" ST_8 : Operation 58 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecBitsMap(i32* %gmem), !map !11" ST_8 : Operation 59 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecTopModule([12 x i8]* @vector_mult_str) nounwind" ST_8 : Operation 60 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32 0, [10 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1, [1 x i8]* @p_str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1) nounwind" [vector_mult/vector_mult.cpp:5] ST_8 : Operation 61 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32 %result, [10 x i8]* @mode5, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @bundle6, [6 x i8]* @p_str3, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)" ST_8 : Operation 62 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32 %B, [10 x i8]* @mode3, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @bundle4, [6 x i8]* @p_str3, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)" ST_8 : Operation 63 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32* %gmem, [6 x i8]* @p_str2, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @p_str1, [6 x i8]* @p_str3, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)" ST_8 : Operation 64 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32 %A, [10 x i8]* @mode, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @bundle, [6 x i8]* @p_str3, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)" ST_8 : Operation 65 [1/7] (8.75ns) ---> "%gmem_addr_2_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 8)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' ST_8 : Operation 66 [1/1] (1.76ns) ---> "br label %burst.rd.header" : 1.74ns ST_9 : Operation 67 [1/1] (0.00ns) ---> "%indvar = phi i4 [ 0, %0 ], [ %indvar_next, %burst.rd.body ]" ST_9 : Operation 68 [1/1] (1.30ns) ---> "%exitcond1 = icmp eq i4 %indvar, -8" ---> Core 25 'Cmp' ST_9 : Operation 69 [1/1] (1.73ns) ---> "%indvar_next = add i4 %indvar, 1" ---> Core 14 'AddSub' ST_9 : Operation 70 [1/1] (0.00ns) ---> "br i1 %exitcond1, label %burst.rd.header5.preheader, label %burst.rd.body" : 8.75ns ST_10 : Operation 71 [1/1] (8.75ns) ---> "%gmem_addr_2_read = call i32 @_ssdm_op_Read.m_axi.i32P(i32* %gmem_addr_2)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' : 2.32ns ST_11 : Operation 72 [1/1] (0.00ns) ---> "%empty = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 8, i64 8, i64 8) nounwind" ST_11 : Operation 73 [1/1] (0.00ns) ---> "%burstread_rbegin = call i32 (...)* @_ssdm_op_SpecRegionBegin([17 x i8]* @burstread_OC_region_s) nounwind" ST_11 : Operation 74 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecPipeline(i32 1, i32 1, i32 1, i32 0, [1 x i8]* @p_str5)" ST_11 : Operation 75 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecLoopName([15 x i8]* @memcpy_OC_tempA_OC_A)" ST_11 : Operation 76 [1/1] (0.00ns) ---> "%tmp = zext i4 %indvar to i64" [vector_mult/vector_mult.cpp:6] ST_11 : Operation 77 [1/1] (0.00ns) ---> "%tempA_addr = getelementptr [8 x i32]* %tempA, i64 0, i64 %tmp" [vector_mult/vector_mult.cpp:6] ST_11 : Operation 78 [1/1] (2.32ns) ---> "store i32 %gmem_addr_2_read, i32* %tempA_addr, align 4" [vector_mult/vector_mult.cpp:6] ---> Core 37 'RAM' ST_11 : Operation 79 [1/1] (0.00ns) ---> "%burstread_rend = call i32 (...)* @_ssdm_op_SpecRegionEnd([17 x i8]* @burstread_OC_region_s, i32 %burstread_rbegin) nounwind" ST_11 : Operation 80 [1/1] (0.00ns) ---> "br label %burst.rd.header" : 8.75ns ST_12 : Operation 81 [7/7] (8.75ns) ---> "%gmem_addr_1_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 8)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' : 8.75ns ST_13 : Operation 82 [6/7] (8.75ns) ---> "%gmem_addr_1_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 8)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' : 8.75ns ST_14 : Operation 83 [5/7] (8.75ns) ---> "%gmem_addr_1_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 8)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' : 8.75ns ST_15 : Operation 84 [4/7] (8.75ns) ---> "%gmem_addr_1_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 8)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' : 8.75ns ST_16 : Operation 85 [3/7] (8.75ns) ---> "%gmem_addr_1_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 8)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' : 8.75ns ST_17 : Operation 86 [2/7] (8.75ns) ---> "%gmem_addr_1_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 8)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' : 8.75ns ST_18 : Operation 87 [1/7] (8.75ns) ---> "%gmem_addr_1_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 8)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' ST_18 : Operation 88 [1/1] (1.76ns) ---> "br label %burst.rd.header5" : 1.74ns ST_19 : Operation 89 [1/1] (0.00ns) ---> "%indvar7 = phi i4 [ %indvar_next8, %burst.rd.body6 ], [ 0, %burst.rd.header5.preheader ]" ST_19 : Operation 90 [1/1] (1.30ns) ---> "%exitcond9 = icmp eq i4 %indvar7, -8" ---> Core 25 'Cmp' ST_19 : Operation 91 [1/1] (1.73ns) ---> "%indvar_next8 = add i4 %indvar7, 1" ---> Core 14 'AddSub' ST_19 : Operation 92 [1/1] (0.00ns) ---> "br i1 %exitcond9, label %burst.rd.end4.0.preheader, label %burst.rd.body6" : 8.75ns ST_20 : Operation 93 [1/1] (8.75ns) ---> "%gmem_addr_1_read = call i32 @_ssdm_op_Read.m_axi.i32P(i32* %gmem_addr_1)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' : 2.32ns ST_21 : Operation 94 [1/1] (0.00ns) ---> "%empty_5 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 8, i64 8, i64 8) nounwind" ST_21 : Operation 95 [1/1] (0.00ns) ---> "%burstread_rbegin1 = call i32 (...)* @_ssdm_op_SpecRegionBegin([17 x i8]* @burstread_OC_region_s) nounwind" ST_21 : Operation 96 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecPipeline(i32 1, i32 1, i32 1, i32 0, [1 x i8]* @p_str6)" ST_21 : Operation 97 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecLoopName([15 x i8]* @memcpy_OC_tempB_OC_B)" ST_21 : Operation 98 [1/1] (0.00ns) ---> "%tmp_1 = zext i4 %indvar7 to i64" [vector_mult/vector_mult.cpp:7] ST_21 : Operation 99 [1/1] (0.00ns) ---> "%tempB_addr = getelementptr [8 x i32]* %tempB, i64 0, i64 %tmp_1" [vector_mult/vector_mult.cpp:7] ST_21 : Operation 100 [1/1] (2.32ns) ---> "store i32 %gmem_addr_1_read, i32* %tempB_addr, align 4" [vector_mult/vector_mult.cpp:7] ---> Core 37 'RAM' ST_21 : Operation 101 [1/1] (0.00ns) ---> "%burstread_rend12 = call i32 (...)* @_ssdm_op_SpecRegionEnd([17 x i8]* @burstread_OC_region_s, i32 %burstread_rbegin1) nounwind" ST_21 : Operation 102 [1/1] (0.00ns) ---> "br label %burst.rd.header5" : 1.77ns ST_22 : Operation 103 [1/1] (1.76ns) ---> "br label %burst.rd.end4.0" [vector_mult/vector_mult.cpp:8] : 2.32ns ST_23 : Operation 104 [1/1] (0.00ns) ---> "%i = phi i4 [ %i_1_3, %burst.rd.end4.1 ], [ 0, %burst.rd.end4.0.preheader ]" [vector_mult/vector_mult.cpp:8] ST_23 : Operation 105 [1/1] (1.30ns) ---> "%exitcond = icmp eq i4 %i, -8" [vector_mult/vector_mult.cpp:8] ---> Core 25 'Cmp' ST_23 : Operation 106 [1/1] (0.00ns) ---> "br i1 %exitcond, label %burst.wr.header.preheader, label %burst.rd.end4.1" [vector_mult/vector_mult.cpp:8] ST_23 : Operation 107 [1/1] (0.00ns) ---> "%tmp_8 = trunc i4 %i to i3" [vector_mult/vector_mult.cpp:8] ST_23 : Operation 108 [1/1] (0.00ns) ---> "%tmp_s = zext i4 %i to i64" [vector_mult/vector_mult.cpp:9] ST_23 : Operation 109 [1/1] (0.00ns) ---> "%tempA_addr_1 = getelementptr inbounds [8 x i32]* %tempA, i64 0, i64 %tmp_s" [vector_mult/vector_mult.cpp:9] ST_23 : Operation 110 [2/2] (2.32ns) ---> "%tempA_load = load i32* %tempA_addr_1, align 16" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' ST_23 : Operation 111 [1/1] (0.00ns) ---> "%tempB_addr_1 = getelementptr inbounds [8 x i32]* %tempB, i64 0, i64 %tmp_s" [vector_mult/vector_mult.cpp:9] ST_23 : Operation 112 [2/2] (2.32ns) ---> "%tempB_load = load i32* %tempB_addr_1, align 16" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' ST_23 : Operation 113 [1/1] (0.00ns) ---> "%i_1_s = or i3 %tmp_8, 1" [vector_mult/vector_mult.cpp:8] ST_23 : Operation 114 [1/1] (0.00ns) ---> "%tmp_2_1 = zext i3 %i_1_s to i64" [vector_mult/vector_mult.cpp:9] ST_23 : Operation 115 [1/1] (0.00ns) ---> "%tempA_addr_2 = getelementptr inbounds [8 x i32]* %tempA, i64 0, i64 %tmp_2_1" [vector_mult/vector_mult.cpp:9] ST_23 : Operation 116 [2/2] (2.32ns) ---> "%tempA_load_1 = load i32* %tempA_addr_2, align 4" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' ST_23 : Operation 117 [1/1] (0.00ns) ---> "%tempB_addr_2 = getelementptr inbounds [8 x i32]* %tempB, i64 0, i64 %tmp_2_1" [vector_mult/vector_mult.cpp:9] ST_23 : Operation 118 [2/2] (2.32ns) ---> "%tempB_load_1 = load i32* %tempB_addr_2, align 4" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' : 2.32ns ST_24 : Operation 119 [1/2] (2.32ns) ---> "%tempA_load = load i32* %tempA_addr_1, align 16" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' ST_24 : Operation 120 [1/2] (2.32ns) ---> "%tempB_load = load i32* %tempB_addr_1, align 16" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' ST_24 : Operation 121 [1/2] (2.32ns) ---> "%tempA_load_1 = load i32* %tempA_addr_2, align 4" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' ST_24 : Operation 122 [1/2] (2.32ns) ---> "%tempB_load_1 = load i32* %tempB_addr_2, align 4" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' ST_24 : Operation 123 [1/1] (0.00ns) ---> "%i_1_1 = or i3 %tmp_8, 2" [vector_mult/vector_mult.cpp:8] ST_24 : Operation 124 [1/1] (0.00ns) ---> "%tmp_2_2 = zext i3 %i_1_1 to i64" [vector_mult/vector_mult.cpp:9] ST_24 : Operation 125 [1/1] (0.00ns) ---> "%tempA_addr_3 = getelementptr inbounds [8 x i32]* %tempA, i64 0, i64 %tmp_2_2" [vector_mult/vector_mult.cpp:9] ST_24 : Operation 126 [2/2] (2.32ns) ---> "%tempA_load_2 = load i32* %tempA_addr_3, align 8" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' ST_24 : Operation 127 [1/1] (0.00ns) ---> "%tempB_addr_3 = getelementptr inbounds [8 x i32]* %tempB, i64 0, i64 %tmp_2_2" [vector_mult/vector_mult.cpp:9] ST_24 : Operation 128 [2/2] (2.32ns) ---> "%tempB_load_2 = load i32* %tempB_addr_3, align 8" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' ST_24 : Operation 129 [1/1] (0.00ns) ---> "%i_1_2 = or i3 %tmp_8, 3" [vector_mult/vector_mult.cpp:8] ST_24 : Operation 130 [1/1] (0.00ns) ---> "%tmp_2_3 = zext i3 %i_1_2 to i64" [vector_mult/vector_mult.cpp:9] ST_24 : Operation 131 [1/1] (0.00ns) ---> "%tempA_addr_4 = getelementptr inbounds [8 x i32]* %tempA, i64 0, i64 %tmp_2_3" [vector_mult/vector_mult.cpp:9] ST_24 : Operation 132 [2/2] (2.32ns) ---> "%tempA_load_3 = load i32* %tempA_addr_4, align 4" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' ST_24 : Operation 133 [1/1] (0.00ns) ---> "%tempB_addr_4 = getelementptr inbounds [8 x i32]* %tempB, i64 0, i64 %tmp_2_3" [vector_mult/vector_mult.cpp:9] ST_24 : Operation 134 [2/2] (2.32ns) ---> "%tempB_load_3 = load i32* %tempB_addr_4, align 4" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' ST_24 : Operation 135 [1/1] (1.73ns) ---> "%i_1_3 = add i4 4, %i" [vector_mult/vector_mult.cpp:8] ---> Core 14 'AddSub' : 8.51ns ST_25 : Operation 136 [1/1] (8.51ns) ---> "%tmp_3 = mul nsw i32 %tempA_load, %tempB_load" [vector_mult/vector_mult.cpp:9] ---> Core 16 'Mul' ST_25 : Operation 137 [1/1] (8.51ns) ---> "%tmp_3_1 = mul nsw i32 %tempA_load_1, %tempB_load_1" [vector_mult/vector_mult.cpp:9] ---> Core 16 'Mul' ST_25 : Operation 138 [1/2] (2.32ns) ---> "%tempA_load_2 = load i32* %tempA_addr_3, align 8" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' ST_25 : Operation 139 [1/2] (2.32ns) ---> "%tempB_load_2 = load i32* %tempB_addr_3, align 8" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' ST_25 : Operation 140 [1/2] (2.32ns) ---> "%tempA_load_3 = load i32* %tempA_addr_4, align 4" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' ST_25 : Operation 141 [1/2] (2.32ns) ---> "%tempB_load_3 = load i32* %tempB_addr_4, align 4" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' : 8.51ns ST_26 : Operation 142 [1/1] (0.00ns) ---> "%tempResult_addr = getelementptr inbounds [8 x i32]* %tempResult, i64 0, i64 %tmp_s" [vector_mult/vector_mult.cpp:9] ST_26 : Operation 143 [1/1] (2.32ns) ---> "store i32 %tmp_3, i32* %tempResult_addr, align 16" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' ST_26 : Operation 144 [1/1] (0.00ns) ---> "%tempResult_addr_4 = getelementptr inbounds [8 x i32]* %tempResult, i64 0, i64 %tmp_2_1" [vector_mult/vector_mult.cpp:9] ST_26 : Operation 145 [1/1] (2.32ns) ---> "store i32 %tmp_3_1, i32* %tempResult_addr_4, align 4" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' ST_26 : Operation 146 [1/1] (8.51ns) ---> "%tmp_3_2 = mul nsw i32 %tempA_load_2, %tempB_load_2" [vector_mult/vector_mult.cpp:9] ---> Core 16 'Mul' ST_26 : Operation 147 [1/1] (8.51ns) ---> "%tmp_3_3 = mul nsw i32 %tempA_load_3, %tempB_load_3" [vector_mult/vector_mult.cpp:9] ---> Core 16 'Mul' : 2.32ns ST_27 : Operation 148 [1/1] (0.00ns) ---> "%empty_6 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 2, i64 2, i64 2) nounwind" ST_27 : Operation 149 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecLoopName([17 x i8]* @p_str4) nounwind" [vector_mult/vector_mult.cpp:10] ST_27 : Operation 150 [1/1] (0.00ns) ---> "%tmp_2 = call i32 (...)* @_ssdm_op_SpecRegionBegin([17 x i8]* @p_str4) nounwind" [vector_mult/vector_mult.cpp:10] ST_27 : Operation 151 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind" [vector_mult/vector_mult.cpp:10] ST_27 : Operation 152 [1/1] (0.00ns) ---> "%empty_7 = call i32 (...)* @_ssdm_op_SpecRegionEnd([17 x i8]* @p_str4, i32 %tmp_2) nounwind" [vector_mult/vector_mult.cpp:9] ST_27 : Operation 153 [1/1] (0.00ns) ---> "%tempResult_addr_2 = getelementptr inbounds [8 x i32]* %tempResult, i64 0, i64 %tmp_2_2" [vector_mult/vector_mult.cpp:9] ST_27 : Operation 154 [1/1] (2.32ns) ---> "store i32 %tmp_3_2, i32* %tempResult_addr_2, align 8" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' ST_27 : Operation 155 [1/1] (0.00ns) ---> "%tempResult_addr_3 = getelementptr inbounds [8 x i32]* %tempResult, i64 0, i64 %tmp_2_3" [vector_mult/vector_mult.cpp:9] ST_27 : Operation 156 [1/1] (2.32ns) ---> "store i32 %tmp_3_3, i32* %tempResult_addr_3, align 4" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' ST_27 : Operation 157 [1/1] (0.00ns) ---> "br label %burst.rd.end4.0" [vector_mult/vector_mult.cpp:8] : 8.75ns ST_28 : Operation 158 [1/1] (8.75ns) ---> "%gmem_addr_wr_req = call i1 @_ssdm_op_WriteReq.m_axi.i32P(i32* %gmem_addr, i32 8)" [vector_mult/vector_mult.cpp:10] ---> Core 9 'm_axi' ST_28 : Operation 159 [1/1] (1.76ns) ---> "br label %burst.wr.header" : 2.32ns ST_29 : Operation 160 [1/1] (0.00ns) ---> "%indvar1 = phi i4 [ %indvar_next1, %burst.wr.body ], [ 0, %burst.wr.header.preheader ]" ST_29 : Operation 161 [1/1] (1.30ns) ---> "%exitcond2 = icmp eq i4 %indvar1, -8" ---> Core 25 'Cmp' ST_29 : Operation 162 [1/1] (1.73ns) ---> "%indvar_next1 = add i4 %indvar1, 1" ---> Core 14 'AddSub' ST_29 : Operation 163 [1/1] (0.00ns) ---> "br i1 %exitcond2, label %memcpy.tail, label %burst.wr.body" ST_29 : Operation 164 [1/1] (0.00ns) ---> "%tmp_5 = zext i4 %indvar1 to i64" [vector_mult/vector_mult.cpp:10] ST_29 : Operation 165 [1/1] (0.00ns) ---> "%tempResult_addr_1 = getelementptr [8 x i32]* %tempResult, i64 0, i64 %tmp_5" [vector_mult/vector_mult.cpp:10] ST_29 : Operation 166 [2/2] (2.32ns) ---> "%tempResult_load = load i32* %tempResult_addr_1, align 4" [vector_mult/vector_mult.cpp:10] ---> Core 37 'RAM' : 2.32ns ST_30 : Operation 167 [1/2] (2.32ns) ---> "%tempResult_load = load i32* %tempResult_addr_1, align 4" [vector_mult/vector_mult.cpp:10] ---> Core 37 'RAM' : 8.75ns ST_31 : Operation 168 [1/1] (0.00ns) ---> "%empty_8 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 8, i64 8, i64 8) nounwind" ST_31 : Operation 169 [1/1] (0.00ns) ---> "%burstwrite_rbegin = call i32 (...)* @_ssdm_op_SpecRegionBegin([18 x i8]* @burstwrite_OC_region) nounwind" ST_31 : Operation 170 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecPipeline(i32 1, i32 1, i32 1, i32 0, [1 x i8]* @p_str7)" ST_31 : Operation 171 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecLoopName([29 x i8]* @memcpy_OC_result_OC_s)" ST_31 : Operation 172 [1/1] (8.75ns) ---> "call void @_ssdm_op_Write.m_axi.i32P(i32* %gmem_addr, i32 %tempResult_load, i4 -1)" [vector_mult/vector_mult.cpp:10] ---> Core 9 'm_axi' ST_31 : Operation 173 [1/1] (0.00ns) ---> "%burstwrite_rend = call i32 (...)* @_ssdm_op_SpecRegionEnd([18 x i8]* @burstwrite_OC_region, i32 %burstwrite_rbegin) nounwind" ST_31 : Operation 174 [1/1] (0.00ns) ---> "br label %burst.wr.header" : 8.75ns ST_32 : Operation 175 [5/5] (8.75ns) ---> "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %gmem_addr)" [vector_mult/vector_mult.cpp:10] ---> Core 9 'm_axi' : 8.75ns ST_33 : Operation 176 [4/5] (8.75ns) ---> "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %gmem_addr)" [vector_mult/vector_mult.cpp:10] ---> Core 9 'm_axi' : 8.75ns ST_34 : Operation 177 [3/5] (8.75ns) ---> "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %gmem_addr)" [vector_mult/vector_mult.cpp:10] ---> Core 9 'm_axi' : 8.75ns ST_35 : Operation 178 [2/5] (8.75ns) ---> "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %gmem_addr)" [vector_mult/vector_mult.cpp:10] ---> Core 9 'm_axi' : 8.75ns ST_36 : Operation 179 [1/5] (8.75ns) ---> "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %gmem_addr)" [vector_mult/vector_mult.cpp:10] ---> Core 9 'm_axi' ST_36 : Operation 180 [1/1] (0.00ns) ---> "ret void" [vector_mult/vector_mult.cpp:11] ============================================================ + Verbose Summary: Timing violations ============================================================ Target clock period: 10ns, clock uncertainty: 1.25ns. : 1ns The critical path consists of the following: s_axi read on port 'result' [5] (1 ns) : 8.75ns The critical path consists of the following: 'getelementptr' operation ('gmem_addr_2') [16] (0 ns) bus request on port 'gmem' (vector_mult/vector_mult.cpp:6) [27] (8.75 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:6) [27] (8.75 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:6) [27] (8.75 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:6) [27] (8.75 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:6) [27] (8.75 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:6) [27] (8.75 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:6) [27] (8.75 ns) : 1.74ns The critical path consists of the following: 'phi' operation ('indvar') with incoming values : ('indvar_next') [30] (0 ns) 'add' operation ('indvar_next') [32] (1.74 ns) : 8.75ns The critical path consists of the following: bus read on port 'gmem' (vector_mult/vector_mult.cpp:6) [40] (8.75 ns) : 2.32ns The critical path consists of the following: 'getelementptr' operation ('tempA_addr', vector_mult/vector_mult.cpp:6) [41] (0 ns) 'store' operation (vector_mult/vector_mult.cpp:6) of variable 'gmem_addr_2_read', vector_mult/vector_mult.cpp:6 on array 'tempA', vector_mult/vector_mult.cpp:5 [42] (2.32 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:7) [46] (8.75 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:7) [46] (8.75 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:7) [46] (8.75 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:7) [46] (8.75 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:7) [46] (8.75 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:7) [46] (8.75 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:7) [46] (8.75 ns) : 1.74ns The critical path consists of the following: 'phi' operation ('indvar7') with incoming values : ('indvar_next8') [49] (0 ns) 'add' operation ('indvar_next8') [51] (1.74 ns) : 8.75ns The critical path consists of the following: bus read on port 'gmem' (vector_mult/vector_mult.cpp:7) [59] (8.75 ns) : 2.32ns The critical path consists of the following: 'getelementptr' operation ('tempB_addr', vector_mult/vector_mult.cpp:7) [60] (0 ns) 'store' operation (vector_mult/vector_mult.cpp:7) of variable 'gmem_addr_1_read', vector_mult/vector_mult.cpp:7 on array 'tempB', vector_mult/vector_mult.cpp:5 [61] (2.32 ns) : 1.77ns The critical path consists of the following: multiplexor before 'phi' operation ('i', vector_mult/vector_mult.cpp:8) with incoming values : ('i_1_3', vector_mult/vector_mult.cpp:8) [67] (1.77 ns) : 2.32ns The critical path consists of the following: 'phi' operation ('i', vector_mult/vector_mult.cpp:8) with incoming values : ('i_1_3', vector_mult/vector_mult.cpp:8) [67] (0 ns) 'getelementptr' operation ('tempA_addr_1', vector_mult/vector_mult.cpp:9) [77] (0 ns) 'load' operation ('tempA_load', vector_mult/vector_mult.cpp:9) on array 'tempA', vector_mult/vector_mult.cpp:5 [78] (2.32 ns) : 2.32ns The critical path consists of the following: 'load' operation ('tempA_load', vector_mult/vector_mult.cpp:9) on array 'tempA', vector_mult/vector_mult.cpp:5 [78] (2.32 ns) : 8.51ns The critical path consists of the following: 'mul' operation ('tmp_3', vector_mult/vector_mult.cpp:9) [81] (8.51 ns) : 8.51ns The critical path consists of the following: 'mul' operation ('tmp_3_2', vector_mult/vector_mult.cpp:9) [100] (8.51 ns) : 2.32ns The critical path consists of the following: 'getelementptr' operation ('tempResult_addr_2', vector_mult/vector_mult.cpp:9) [101] (0 ns) 'store' operation (vector_mult/vector_mult.cpp:9) of variable 'tmp_3_2', vector_mult/vector_mult.cpp:9 on array 'tempResult', vector_mult/vector_mult.cpp:5 [102] (2.32 ns) : 8.75ns The critical path consists of the following: bus request on port 'gmem' (vector_mult/vector_mult.cpp:10) [115] (8.75 ns) : 2.32ns The critical path consists of the following: 'phi' operation ('indvar1') with incoming values : ('indvar_next1') [118] (0 ns) 'getelementptr' operation ('tempResult_addr_1', vector_mult/vector_mult.cpp:10) [128] (0 ns) 'load' operation ('tempResult_load', vector_mult/vector_mult.cpp:10) on array 'tempResult', vector_mult/vector_mult.cpp:5 [129] (2.32 ns) : 2.32ns The critical path consists of the following: 'load' operation ('tempResult_load', vector_mult/vector_mult.cpp:10) on array 'tempResult', vector_mult/vector_mult.cpp:5 [129] (2.32 ns) : 8.75ns The critical path consists of the following: bus write on port 'gmem' (vector_mult/vector_mult.cpp:10) [130] (8.75 ns) : 8.75ns The critical path consists of the following: bus access on port 'gmem' (vector_mult/vector_mult.cpp:10) [134] (8.75 ns) : 8.75ns The critical path consists of the following: bus access on port 'gmem' (vector_mult/vector_mult.cpp:10) [134] (8.75 ns) : 8.75ns The critical path consists of the following: bus access on port 'gmem' (vector_mult/vector_mult.cpp:10) [134] (8.75 ns) : 8.75ns The critical path consists of the following: bus access on port 'gmem' (vector_mult/vector_mult.cpp:10) [134] (8.75 ns) : 8.75ns The critical path consists of the following: bus access on port 'gmem' (vector_mult/vector_mult.cpp:10) [134] (8.75 ns) ============================================================ + Verbose Summary: Binding ============================================================ N/A * FSMD analyzer results: - Output states: - Input state : - Chain level: State 1 State 2 State 3 State 4 State 5 State 6 State 7 State 8 State 9 State 10 State 11 State 12 State 13 State 14 State 15 State 16 State 17 State 18 State 19 State 20 State 21 State 22 State 23 State 24 State 25 State 26 State 27 State 28 State 29 State 30 State 31 State 32 State 33 State 34 State 35 State 36 ============================================================ + Verbose Summary: Datapath Resource usage ============================================================ N/A