================================================================ == Vivado HLS Report for 'vector_mult' ================================================================ * Date: Mon Mar 19 10:51:09 2018 * Version: 2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017) * Project: vector_mult * Solution: solution2 * Product family: zynq * Target device: xc7z020clg484-1 ================================================================ == Performance Estimates ================================================================ + Timing (ns): * Summary: +--------+-------+----------+------------+ | Clock | Target| Estimated| Uncertainty| +--------+-------+----------+------------+ |ap_clk | 10.00| 8.75| 1.25| +--------+-------+----------+------------+ + Latency (clock cycles): * Summary: +-----+-----+-----+-----+---------+ | Latency | Interval | Pipeline| | min | max | min | max | Type | +-----+-----+-----+-----+---------+ | 58| 58| 58| 58| none | +-----+-----+-----+-----+---------+ + Detail: * Instance: N/A * Loop: +--------------------------------+-----+-----+----------+-----------+-----------+------+----------+ | | Latency | Iteration| Initiation Interval | Trip | | | Loop Name | min | max | Latency | achieved | target | Count| Pipelined| +--------------------------------+-----+-----+----------+-----------+-----------+------+----------+ |- memcpy.tempA.A | 9| 9| 3| 1| 1| 8| yes | |- memcpy.tempB.B | 9| 9| 3| 1| 1| 8| yes | |- vector_mult_loop | 6| 6| 5| 2| 1| 2| yes | |- memcpy.result.tempResult.gep | 9| 9| 3| 1| 1| 8| yes | +--------------------------------+-----+-----+----------+-----------+-----------+------+----------+ ================================================================ == Utilization Estimates ================================================================ * Summary: +-----------------+---------+-------+--------+-------+ | Name | BRAM_18K| DSP48E| FF | LUT | +-----------------+---------+-------+--------+-------+ |DSP | -| -| -| -| |Expression | -| 6| 0| 294| |FIFO | -| -| -| -| |Instance | 2| -| 662| 812| |Memory | 2| -| 128| 8| |Multiplexer | -| -| -| 495| |Register | -| -| 545| -| +-----------------+---------+-------+--------+-------+ |Total | 4| 6| 1335| 1609| +-----------------+---------+-------+--------+-------+ |Available | 280| 220| 106400| 53200| +-----------------+---------+-------+--------+-------+ |Utilization (%) | 1| 2| 1| 3| +-----------------+---------+-------+--------+-------+ + Detail: * Instance: +------------------------------+----------------------------+---------+-------+-----+-----+ | Instance | Module | BRAM_18K| DSP48E| FF | LUT | +------------------------------+----------------------------+---------+-------+-----+-----+ |vector_mult_AXILiteS_s_axi_U |vector_mult_AXILiteS_s_axi | 0| 0| 150| 232| |vector_mult_gmem_m_axi_U |vector_mult_gmem_m_axi | 2| 0| 512| 580| +------------------------------+----------------------------+---------+-------+-----+-----+ |Total | | 2| 0| 662| 812| +------------------------------+----------------------------+---------+-------+-----+-----+ * DSP48: N/A * Memory: +--------------+----------------------+---------+----+----+------+-----+------+-------------+ | Memory | Module | BRAM_18K| FF | LUT| Words| Bits| Banks| W*Bits*Banks| +--------------+----------------------+---------+----+----+------+-----+------+-------------+ |tempA_U |vector_mult_tempA | 0| 64| 4| 8| 32| 1| 256| |tempB_U |vector_mult_tempA | 0| 64| 4| 8| 32| 1| 256| |tempResult_U |vector_mult_tempRbkb | 2| 0| 0| 8| 32| 1| 256| +--------------+----------------------+---------+----+----+------+-----+------+-------------+ |Total | | 2| 128| 8| 24| 96| 3| 768| +--------------+----------------------+---------+----+----+------+-----+------+-------------+ * FIFO: N/A * Expression: +-----------------------------------+----------+-------+---+----+------------+------------+ | Variable Name | Operation| DSP48E| FF| LUT| Bitwidth P0| Bitwidth P1| +-----------------------------------+----------+-------+---+----+------------+------------+ |grp_fu_381_p2 | * | 3| 0| 20| 32| 32| |grp_fu_387_p2 | * | 3| 0| 20| 32| 32| |i_1_3_fu_545_p2 | + | 0| 0| 13| 3| 4| |indvar_next1_fu_557_p2 | + | 0| 0| 13| 4| 1| |indvar_next8_fu_484_p2 | + | 0| 0| 13| 4| 1| |indvar_next_fu_467_p2 | + | 0| 0| 13| 4| 1| |ap_block_pp0_stage0_11001 | and | 0| 0| 8| 1| 1| |ap_block_pp1_stage0_11001 | and | 0| 0| 8| 1| 1| |ap_block_pp3_stage0_11001 | and | 0| 0| 8| 1| 1| |ap_block_state10_pp0_stage0_iter1 | and | 0| 0| 8| 1| 1| |ap_block_state20_pp1_stage0_iter1 | and | 0| 0| 8| 1| 1| |ap_block_state31_io | and | 0| 0| 8| 1| 1| |ap_condition_329 | and | 0| 0| 8| 1| 1| |ap_condition_348 | and | 0| 0| 8| 1| 1| |exitcond1_fu_461_p2 | icmp | 0| 0| 11| 4| 5| |exitcond2_fu_551_p2 | icmp | 0| 0| 11| 4| 5| |exitcond9_fu_478_p2 | icmp | 0| 0| 11| 4| 5| |exitcond_fu_495_p2 | icmp | 0| 0| 11| 4| 5| |i_1_1_fu_523_p2 | or | 0| 0| 10| 3| 2| |i_1_2_fu_534_p2 | or | 0| 0| 10| 3| 2| |i_1_s_fu_511_p2 | or | 0| 0| 10| 3| 1| |ap_enable_pp0 | xor | 0| 0| 8| 1| 2| |ap_enable_pp1 | xor | 0| 0| 8| 1| 2| |ap_enable_pp2 | xor | 0| 0| 8| 1| 2| |ap_enable_pp3 | xor | 0| 0| 8| 1| 2| |ap_enable_reg_pp0_iter1 | xor | 0| 0| 8| 2| 1| |ap_enable_reg_pp1_iter1 | xor | 0| 0| 8| 2| 1| |ap_enable_reg_pp2_iter1 | xor | 0| 0| 8| 2| 1| |ap_enable_reg_pp3_iter1 | xor | 0| 0| 8| 2| 1| +-----------------------------------+----------+-------+---+----+------------+------------+ |Total | | 6| 0| 294| 124| 116| +-----------------------------------+----------+-------+---+----+------------+------------+ * Multiplexer: +----------------------------------+-----+-----------+-----+-----------+ | Name | LUT | Input Size| Bits| Total Bits| +----------------------------------+-----+-----------+-----+-----------+ |ap_NS_fsm | 129| 28| 1| 28| |ap_enable_reg_pp0_iter1 | 9| 2| 1| 2| |ap_enable_reg_pp0_iter2 | 9| 2| 1| 2| |ap_enable_reg_pp1_iter1 | 9| 2| 1| 2| |ap_enable_reg_pp1_iter2 | 9| 2| 1| 2| |ap_enable_reg_pp2_iter1 | 9| 2| 1| 2| |ap_enable_reg_pp2_iter2 | 9| 2| 1| 2| |ap_enable_reg_pp3_iter1 | 9| 2| 1| 2| |ap_enable_reg_pp3_iter2 | 9| 2| 1| 2| |ap_phi_mux_i_phi_fu_342_p4 | 9| 2| 4| 8| |ap_phi_mux_indvar7_phi_fu_330_p4 | 9| 2| 4| 8| |ap_phi_mux_indvar_phi_fu_318_p4 | 9| 2| 4| 8| |ap_sig_ioackin_gmem_ARREADY | 9| 2| 1| 2| |ap_sig_ioackin_gmem_AWREADY | 9| 2| 1| 2| |ap_sig_ioackin_gmem_WREADY | 9| 2| 1| 2| |gmem_ARADDR | 15| 3| 32| 96| |gmem_blk_n_AR | 9| 2| 1| 2| |gmem_blk_n_AW | 9| 2| 1| 2| |gmem_blk_n_B | 9| 2| 1| 2| |gmem_blk_n_R | 9| 2| 1| 2| |gmem_blk_n_W | 9| 2| 1| 2| |i_reg_338 | 9| 2| 4| 8| |indvar1_reg_350 | 9| 2| 4| 8| |indvar7_reg_326 | 9| 2| 4| 8| |indvar_reg_314 | 9| 2| 4| 8| |reg_361 | 9| 2| 32| 64| |reg_366 | 9| 2| 32| 64| |reg_371 | 9| 2| 32| 64| |reg_376 | 9| 2| 32| 64| |tempA_address0 | 21| 4| 3| 12| |tempA_address1 | 15| 3| 3| 9| |tempB_address0 | 21| 4| 3| 12| |tempB_address1 | 15| 3| 3| 9| |tempResult_address0 | 21| 4| 3| 12| |tempResult_address1 | 15| 3| 3| 9| +----------------------------------+-----+-----------+-----+-----------+ |Total | 495| 106| 223| 531| +----------------------------------+-----+-----------+-----+-----------+ * Register: +------------------------------------+----+----+-----+-----------+ | Name | FF | LUT| Bits| Const Bits| +------------------------------------+----+----+-----+-----------+ |A1_reg_578 | 30| 0| 30| 0| |B3_reg_573 | 30| 0| 30| 0| |ap_CS_fsm | 27| 0| 27| 0| |ap_enable_reg_pp0_iter0 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter1 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter2 | 1| 0| 1| 0| |ap_enable_reg_pp1_iter0 | 1| 0| 1| 0| |ap_enable_reg_pp1_iter1 | 1| 0| 1| 0| |ap_enable_reg_pp1_iter2 | 1| 0| 1| 0| |ap_enable_reg_pp2_iter0 | 1| 0| 1| 0| |ap_enable_reg_pp2_iter1 | 1| 0| 1| 0| |ap_enable_reg_pp2_iter2 | 1| 0| 1| 0| |ap_enable_reg_pp3_iter0 | 1| 0| 1| 0| |ap_enable_reg_pp3_iter1 | 1| 0| 1| 0| |ap_enable_reg_pp3_iter2 | 1| 0| 1| 0| |ap_reg_ioackin_gmem_ARREADY | 1| 0| 1| 0| |ap_reg_ioackin_gmem_AWREADY | 1| 0| 1| 0| |ap_reg_ioackin_gmem_WREADY | 1| 0| 1| 0| |ap_reg_pp0_iter1_exitcond1_reg_601 | 1| 0| 1| 0| |ap_reg_pp0_iter1_indvar_reg_314 | 4| 0| 4| 0| |ap_reg_pp1_iter1_exitcond9_reg_615 | 1| 0| 1| 0| |ap_reg_pp1_iter1_indvar7_reg_326 | 4| 0| 4| 0| |ap_reg_pp2_iter1_exitcond_reg_629 | 1| 0| 1| 0| |ap_reg_pp2_iter1_tmp_2_1_reg_654 | 2| 0| 64| 62| |ap_reg_pp2_iter1_tmp_2_2_reg_669 | 2| 0| 64| 62| |ap_reg_pp2_iter1_tmp_2_3_reg_684 | 1| 0| 64| 63| |ap_reg_pp2_iter1_tmp_s_reg_639 | 4| 0| 64| 60| |ap_reg_pp3_iter1_exitcond2_reg_704 | 1| 0| 1| 0| |exitcond1_reg_601 | 1| 0| 1| 0| |exitcond2_reg_704 | 1| 0| 1| 0| |exitcond9_reg_615 | 1| 0| 1| 0| |exitcond_reg_629 | 1| 0| 1| 0| |gmem_addr_1_read_reg_624 | 32| 0| 32| 0| |gmem_addr_1_reg_595 | 30| 0| 32| 2| |gmem_addr_2_read_reg_610 | 32| 0| 32| 0| |gmem_addr_reg_589 | 30| 0| 32| 2| |i_1_3_reg_699 | 4| 0| 4| 0| |i_reg_338 | 4| 0| 4| 0| |indvar1_reg_350 | 4| 0| 4| 0| |indvar7_reg_326 | 4| 0| 4| 0| |indvar_next8_reg_619 | 4| 0| 4| 0| |indvar_next_reg_605 | 4| 0| 4| 0| |indvar_reg_314 | 4| 0| 4| 0| |reg_361 | 32| 0| 32| 0| |reg_366 | 32| 0| 32| 0| |reg_371 | 32| 0| 32| 0| |reg_376 | 32| 0| 32| 0| |reg_393 | 32| 0| 32| 0| |reg_398 | 32| 0| 32| 0| |result5_reg_568 | 30| 0| 30| 0| |tempResult_load_reg_718 | 32| 0| 32| 0| |tmp_2_1_reg_654 | 2| 0| 64| 62| |tmp_2_2_reg_669 | 2| 0| 64| 62| |tmp_2_3_reg_684 | 1| 0| 64| 63| |tmp_8_reg_633 | 3| 0| 3| 0| |tmp_s_reg_639 | 4| 0| 64| 60| +------------------------------------+----+----+-----+-----------+ |Total | 545| 0| 1043| 498| +------------------------------------+----+----+-----+-----------+ ================================================================ == Interface ================================================================ * Summary: +------------------------+-----+-----+------------+--------------+--------------+ | RTL Ports | Dir | Bits| Protocol | Source Object| C Type | +------------------------+-----+-----+------------+--------------+--------------+ |s_axi_AXILiteS_AWVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_AWREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_AWADDR | in | 6| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WDATA | in | 32| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WSTRB | in | 4| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARADDR | in | 6| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RVALID | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RREADY | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RDATA | out | 32| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RRESP | out | 2| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BVALID | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BREADY | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BRESP | out | 2| s_axi | AXILiteS | scalar | |ap_clk | in | 1| ap_ctrl_hs | vector_mult | return value | |ap_rst_n | in | 1| ap_ctrl_hs | vector_mult | return value | |interrupt | out | 1| ap_ctrl_hs | vector_mult | return value | |m_axi_gmem_AWVALID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_AWREADY | in | 1| m_axi | gmem | pointer | |m_axi_gmem_AWADDR | out | 32| m_axi | gmem | pointer | |m_axi_gmem_AWID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_AWLEN | out | 8| m_axi | gmem | pointer | |m_axi_gmem_AWSIZE | out | 3| m_axi | gmem | pointer | |m_axi_gmem_AWBURST | out | 2| m_axi | gmem | pointer | |m_axi_gmem_AWLOCK | out | 2| m_axi | gmem | pointer | |m_axi_gmem_AWCACHE | out | 4| m_axi | gmem | pointer | |m_axi_gmem_AWPROT | out | 3| m_axi | gmem | pointer | |m_axi_gmem_AWQOS | out | 4| m_axi | gmem | pointer | |m_axi_gmem_AWREGION | out | 4| m_axi | gmem | pointer | |m_axi_gmem_AWUSER | out | 1| m_axi | gmem | pointer | |m_axi_gmem_WVALID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_WREADY | in | 1| m_axi | gmem | pointer | |m_axi_gmem_WDATA | out | 32| m_axi | gmem | pointer | |m_axi_gmem_WSTRB | out | 4| m_axi | gmem | pointer | |m_axi_gmem_WLAST | out | 1| m_axi | gmem | pointer | |m_axi_gmem_WID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_WUSER | out | 1| m_axi | gmem | pointer | |m_axi_gmem_ARVALID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_ARREADY | in | 1| m_axi | gmem | pointer | |m_axi_gmem_ARADDR | out | 32| m_axi | gmem | pointer | |m_axi_gmem_ARID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_ARLEN | out | 8| m_axi | gmem | pointer | |m_axi_gmem_ARSIZE | out | 3| m_axi | gmem | pointer | |m_axi_gmem_ARBURST | out | 2| m_axi | gmem | pointer | |m_axi_gmem_ARLOCK | out | 2| m_axi | gmem | pointer | |m_axi_gmem_ARCACHE | out | 4| m_axi | gmem | pointer | |m_axi_gmem_ARPROT | out | 3| m_axi | gmem | pointer | |m_axi_gmem_ARQOS | out | 4| m_axi | gmem | pointer | |m_axi_gmem_ARREGION | out | 4| m_axi | gmem | pointer | |m_axi_gmem_ARUSER | out | 1| m_axi | gmem | pointer | |m_axi_gmem_RVALID | in | 1| m_axi | gmem | pointer | |m_axi_gmem_RREADY | out | 1| m_axi | gmem | pointer | |m_axi_gmem_RDATA | in | 32| m_axi | gmem | pointer | |m_axi_gmem_RLAST | in | 1| m_axi | gmem | pointer | |m_axi_gmem_RID | in | 1| m_axi | gmem | pointer | |m_axi_gmem_RUSER | in | 1| m_axi | gmem | pointer | |m_axi_gmem_RRESP | in | 2| m_axi | gmem | pointer | |m_axi_gmem_BVALID | in | 1| m_axi | gmem | pointer | |m_axi_gmem_BREADY | out | 1| m_axi | gmem | pointer | |m_axi_gmem_BRESP | in | 2| m_axi | gmem | pointer | |m_axi_gmem_BID | in | 1| m_axi | gmem | pointer | |m_axi_gmem_BUSER | in | 1| m_axi | gmem | pointer | +------------------------+-----+-----+------------+--------------+--------------+ ============================================================ + Verbose Summary: Synthesis Manager ============================================================ InlineROM: 1 ExposeGlobal: 0 ============================================================ + Verbose Summary: CDFG Model ============================================================ IsTopModel: 1 ResetActiveHigh: 1 IsCombinational: 2 IsDatapathOnly: 2 HasWiredReturn: 1 HasMFsm: 0 HasVarLatency: 1 IsPipeline: 0 IsRtlPipelined: 0 IsInstanceOverlapped: 0 IsDontTouch: 0 HasImplIP: 0 IsGatedGlobalClock: 0 + Individual pipeline summary: * Pipeline-0: initiation interval (II) = 1, depth = 3 * Pipeline-1: initiation interval (II) = 1, depth = 3 * Pipeline-2: initiation interval (II) = 2, depth = 5 * Pipeline-3: initiation interval (II) = 1, depth = 3 ============================================================ + Verbose Summary: Schedule ============================================================ * Number of FSM states : 36 * Pipeline : 4 Pipeline-0 : II = 1, D = 3, States = { 9 10 11 } Pipeline-1 : II = 1, D = 3, States = { 19 20 21 } Pipeline-2 : II = 2, D = 5, States = { 23 24 25 26 27 } Pipeline-3 : II = 1, D = 3, States = { 29 30 31 } * Dataflow Pipeline: 0 * FSM state transitions: 1 --> 2 / true 2 --> 3 / true 3 --> 4 / true 4 --> 5 / true 5 --> 6 / true 6 --> 7 / true 7 --> 8 / true 8 --> 9 / true 9 --> 12 / (exitcond1) 10 / (!exitcond1) 10 --> 11 / true 11 --> 9 / true 12 --> 13 / true 13 --> 14 / true 14 --> 15 / true 15 --> 16 / true 16 --> 17 / true 17 --> 18 / true 18 --> 19 / true 19 --> 22 / (exitcond9) 20 / (!exitcond9) 20 --> 21 / true 21 --> 19 / true 22 --> 23 / true 23 --> 28 / (exitcond) 24 / (!exitcond) 24 --> 25 / true 25 --> 26 / true 26 --> 27 / true 27 --> 23 / true 28 --> 29 / true 29 --> 32 / (exitcond2) 30 / (!exitcond2) 30 --> 31 / true 31 --> 29 / true 32 --> 33 / true 33 --> 34 / true 34 --> 35 / true 35 --> 36 / true 36 --> * FSM state operations: : 2.32ns ST_1 : Operation 37 [1/1] (1.00ns) ---> "%result_read = call i32 @_ssdm_op_Read.s_axilite.i32(i32 %result)" ---> Core 10 's_axilite' ST_1 : Operation 38 [1/1] (1.00ns) ---> "%B_read = call i32 @_ssdm_op_Read.s_axilite.i32(i32 %B)" ---> Core 10 's_axilite' ST_1 : Operation 39 [1/1] (1.00ns) ---> "%A_read = call i32 @_ssdm_op_Read.s_axilite.i32(i32 %A)" ---> Core 10 's_axilite' ST_1 : Operation 40 [1/1] (0.00ns) ---> "%result5 = call i30 @_ssdm_op_PartSelect.i30.i32.i32.i32(i32 %result_read, i32 2, i32 31)" ST_1 : Operation 41 [1/1] (0.00ns) ---> "%B3 = call i30 @_ssdm_op_PartSelect.i30.i32.i32.i32(i32 %B_read, i32 2, i32 31)" ST_1 : Operation 42 [1/1] (0.00ns) ---> "%A1 = call i30 @_ssdm_op_PartSelect.i30.i32.i32.i32(i32 %A_read, i32 2, i32 31)" ST_1 : Operation 43 [1/1] (2.32ns) ---> "%tempA = alloca [8 x i32], align 16" [vector_mult/vector_mult.cpp:5] ---> Core 37 'RAM' ST_1 : Operation 44 [1/1] (2.32ns) ---> "%tempB = alloca [8 x i32], align 16" [vector_mult/vector_mult.cpp:5] ---> Core 37 'RAM' ST_1 : Operation 45 [1/1] (2.32ns) ---> "%tempResult = alloca [8 x i32], align 16" [vector_mult/vector_mult.cpp:5] ---> Core 37 'RAM' : 8.75ns ST_2 : Operation 46 [1/1] (0.00ns) ---> "%tmp_7 = zext i30 %A1 to i64" ST_2 : Operation 47 [1/1] (0.00ns) ---> "%gmem_addr_2 = getelementptr i32* %gmem, i64 %tmp_7" ST_2 : Operation 48 [7/7] (8.75ns) ---> "%gmem_addr_2_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 8)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' : 8.75ns ST_3 : Operation 49 [6/7] (8.75ns) ---> "%gmem_addr_2_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 8)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' : 8.75ns ST_4 : Operation 50 [5/7] (8.75ns) ---> "%gmem_addr_2_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 8)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' : 8.75ns ST_5 : Operation 51 [4/7] (8.75ns) ---> "%gmem_addr_2_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 8)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' : 8.75ns ST_6 : Operation 52 [3/7] (8.75ns) ---> "%gmem_addr_2_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 8)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' : 8.75ns ST_7 : Operation 53 [2/7] (8.75ns) ---> "%gmem_addr_2_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 8)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' : 8.75ns ST_8 : Operation 54 [1/1] (0.00ns) ---> "%tmp_4 = zext i30 %result5 to i64" ST_8 : Operation 55 [1/1] (0.00ns) ---> "%gmem_addr = getelementptr i32* %gmem, i64 %tmp_4" ST_8 : Operation 56 [1/1] (0.00ns) ---> "%tmp_6 = zext i30 %B3 to i64" ST_8 : Operation 57 [1/1] (0.00ns) ---> "%gmem_addr_1 = getelementptr i32* %gmem, i64 %tmp_6" ST_8 : Operation 58 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecBitsMap(i32* %gmem), !map !11" ST_8 : Operation 59 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecTopModule([12 x i8]* @vector_mult_str) nounwind" ST_8 : Operation 60 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32 0, [10 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1, [1 x i8]* @p_str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1) nounwind" [vector_mult/vector_mult.cpp:5] ST_8 : Operation 61 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32 %result, [10 x i8]* @mode5, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @bundle6, [6 x i8]* @p_str3, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)" ST_8 : Operation 62 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32 %B, [10 x i8]* @mode3, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @bundle4, [6 x i8]* @p_str3, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)" ST_8 : Operation 63 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32* %gmem, [6 x i8]* @p_str2, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @p_str1, [6 x i8]* @p_str3, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)" ST_8 : Operation 64 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32 %A, [10 x i8]* @mode, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @bundle, [6 x i8]* @p_str3, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)" ST_8 : Operation 65 [1/7] (8.75ns) ---> "%gmem_addr_2_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 8)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' ST_8 : Operation 66 [1/1] (1.76ns) ---> "br label %burst.rd.header" : 1.74ns ST_9 : Operation 67 [1/1] (0.00ns) ---> "%indvar = phi i4 [ 0, %0 ], [ %indvar_next, %burst.rd.body ]" ST_9 : Operation 68 [1/1] (1.30ns) ---> "%exitcond1 = icmp eq i4 %indvar, -8" ---> Core 25 'Cmp' ST_9 : Operation 69 [1/1] (1.73ns) ---> "%indvar_next = add i4 %indvar, 1" ---> Core 14 'AddSub' ST_9 : Operation 70 [1/1] (0.00ns) ---> "br i1 %exitcond1, label %burst.rd.header5.preheader, label %burst.rd.body" : 8.75ns ST_10 : Operation 71 [1/1] (8.75ns) ---> "%gmem_addr_2_read = call i32 @_ssdm_op_Read.m_axi.i32P(i32* %gmem_addr_2)" [vector_mult/vector_mult.cpp:6] ---> Core 9 'm_axi' : 2.32ns ST_11 : Operation 72 [1/1] (0.00ns) ---> "%empty = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 8, i64 8, i64 8) nounwind" ST_11 : Operation 73 [1/1] (0.00ns) ---> "%burstread_rbegin = call i32 (...)* @_ssdm_op_SpecRegionBegin([17 x i8]* @burstread_OC_region_s) nounwind" ST_11 : Operation 74 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecPipeline(i32 1, i32 1, i32 1, i32 0, [1 x i8]* @p_str5)" ST_11 : Operation 75 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecLoopName([15 x i8]* @memcpy_OC_tempA_OC_A)" ST_11 : Operation 76 [1/1] (0.00ns) ---> "%tmp = zext i4 %indvar to i64" [vector_mult/vector_mult.cpp:6] ST_11 : Operation 77 [1/1] (0.00ns) ---> "%tempA_addr = getelementptr [8 x i32]* %tempA, i64 0, i64 %tmp" [vector_mult/vector_mult.cpp:6] ST_11 : Operation 78 [1/1] (2.32ns) ---> "store i32 %gmem_addr_2_read, i32* %tempA_addr, align 4" [vector_mult/vector_mult.cpp:6] ---> Core 37 'RAM' ST_11 : Operation 79 [1/1] (0.00ns) ---> "%burstread_rend = call i32 (...)* @_ssdm_op_SpecRegionEnd([17 x i8]* @burstread_OC_region_s, i32 %burstread_rbegin) nounwind" ST_11 : Operation 80 [1/1] (0.00ns) ---> "br label %burst.rd.header" : 8.75ns ST_12 : Operation 81 [7/7] (8.75ns) ---> "%gmem_addr_1_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 8)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' : 8.75ns ST_13 : Operation 82 [6/7] (8.75ns) ---> "%gmem_addr_1_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 8)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' : 8.75ns ST_14 : Operation 83 [5/7] (8.75ns) ---> "%gmem_addr_1_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 8)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' : 8.75ns ST_15 : Operation 84 [4/7] (8.75ns) ---> "%gmem_addr_1_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 8)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' : 8.75ns ST_16 : Operation 85 [3/7] (8.75ns) ---> "%gmem_addr_1_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 8)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' : 8.75ns ST_17 : Operation 86 [2/7] (8.75ns) ---> "%gmem_addr_1_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 8)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' : 8.75ns ST_18 : Operation 87 [1/7] (8.75ns) ---> "%gmem_addr_1_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 8)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' ST_18 : Operation 88 [1/1] (1.76ns) ---> "br label %burst.rd.header5" : 1.74ns ST_19 : Operation 89 [1/1] (0.00ns) ---> "%indvar7 = phi i4 [ %indvar_next8, %burst.rd.body6 ], [ 0, %burst.rd.header5.preheader ]" ST_19 : Operation 90 [1/1] (1.30ns) ---> "%exitcond9 = icmp eq i4 %indvar7, -8" ---> Core 25 'Cmp' ST_19 : Operation 91 [1/1] (1.73ns) ---> "%indvar_next8 = add i4 %indvar7, 1" ---> Core 14 'AddSub' ST_19 : Operation 92 [1/1] (0.00ns) ---> "br i1 %exitcond9, label %burst.rd.end4.0.preheader, label %burst.rd.body6" : 8.75ns ST_20 : Operation 93 [1/1] (8.75ns) ---> "%gmem_addr_1_read = call i32 @_ssdm_op_Read.m_axi.i32P(i32* %gmem_addr_1)" [vector_mult/vector_mult.cpp:7] ---> Core 9 'm_axi' : 2.32ns ST_21 : Operation 94 [1/1] (0.00ns) ---> "%empty_5 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 8, i64 8, i64 8) nounwind" ST_21 : Operation 95 [1/1] (0.00ns) ---> "%burstread_rbegin1 = call i32 (...)* @_ssdm_op_SpecRegionBegin([17 x i8]* @burstread_OC_region_s) nounwind" ST_21 : Operation 96 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecPipeline(i32 1, i32 1, i32 1, i32 0, [1 x i8]* @p_str6)" ST_21 : Operation 97 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecLoopName([15 x i8]* @memcpy_OC_tempB_OC_B)" ST_21 : Operation 98 [1/1] (0.00ns) ---> "%tmp_1 = zext i4 %indvar7 to i64" [vector_mult/vector_mult.cpp:7] ST_21 : Operation 99 [1/1] (0.00ns) ---> "%tempB_addr = getelementptr [8 x i32]* %tempB, i64 0, i64 %tmp_1" [vector_mult/vector_mult.cpp:7] ST_21 : Operation 100 [1/1] (2.32ns) ---> "store i32 %gmem_addr_1_read, i32* %tempB_addr, align 4" [vector_mult/vector_mult.cpp:7] ---> Core 37 'RAM' ST_21 : Operation 101 [1/1] (0.00ns) ---> "%burstread_rend12 = call i32 (...)* @_ssdm_op_SpecRegionEnd([17 x i8]* @burstread_OC_region_s, i32 %burstread_rbegin1) nounwind" ST_21 : Operation 102 [1/1] (0.00ns) ---> "br label %burst.rd.header5" : 1.77ns ST_22 : Operation 103 [1/1] (1.76ns) ---> "br label %burst.rd.end4.0" [vector_mult/vector_mult.cpp:8] : 2.32ns ST_23 : Operation 104 [1/1] (0.00ns) ---> "%i = phi i4 [ %i_1_3, %burst.rd.end4.1 ], [ 0, %burst.rd.end4.0.preheader ]" [vector_mult/vector_mult.cpp:8] ST_23 : Operation 105 [1/1] (1.30ns) ---> "%exitcond = icmp eq i4 %i, -8" [vector_mult/vector_mult.cpp:8] ---> Core 25 'Cmp' ST_23 : Operation 106 [1/1] (0.00ns) ---> "br i1 %exitcond, label %burst.wr.header.preheader, label %burst.rd.end4.1" [vector_mult/vector_mult.cpp:8] ST_23 : Operation 107 [1/1] (0.00ns) ---> "%tmp_8 = trunc i4 %i to i3" [vector_mult/vector_mult.cpp:8] ST_23 : Operation 108 [1/1] (0.00ns) ---> "%tmp_s = zext i4 %i to i64" [vector_mult/vector_mult.cpp:9] ST_23 : Operation 109 [1/1] (0.00ns) ---> "%tempA_addr_1 = getelementptr inbounds [8 x i32]* %tempA, i64 0, i64 %tmp_s" [vector_mult/vector_mult.cpp:9] ST_23 : Operation 110 [2/2] (2.32ns) ---> "%tempA_load = load i32* %tempA_addr_1, align 16" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' ST_23 : Operation 111 [1/1] (0.00ns) ---> "%tempB_addr_1 = getelementptr inbounds [8 x i32]* %tempB, i64 0, i64 %tmp_s" [vector_mult/vector_mult.cpp:9] ST_23 : Operation 112 [2/2] (2.32ns) ---> "%tempB_load = load i32* %tempB_addr_1, align 16" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' ST_23 : Operation 113 [1/1] (0.00ns) ---> "%i_1_s = or i3 %tmp_8, 1" [vector_mult/vector_mult.cpp:8] ST_23 : Operation 114 [1/1] (0.00ns) ---> "%tmp_2_1 = zext i3 %i_1_s to i64" [vector_mult/vector_mult.cpp:9] ST_23 : Operation 115 [1/1] (0.00ns) ---> "%tempA_addr_2 = getelementptr inbounds [8 x i32]* %tempA, i64 0, i64 %tmp_2_1" [vector_mult/vector_mult.cpp:9] ST_23 : Operation 116 [2/2] (2.32ns) ---> "%tempA_load_1 = load i32* %tempA_addr_2, align 4" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' ST_23 : Operation 117 [1/1] (0.00ns) ---> "%tempB_addr_2 = getelementptr inbounds [8 x i32]* %tempB, i64 0, i64 %tmp_2_1" [vector_mult/vector_mult.cpp:9] ST_23 : Operation 118 [2/2] (2.32ns) ---> "%tempB_load_1 = load i32* %tempB_addr_2, align 4" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' : 2.32ns ST_24 : Operation 119 [1/2] (2.32ns) ---> "%tempA_load = load i32* %tempA_addr_1, align 16" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' ST_24 : Operation 120 [1/2] (2.32ns) ---> "%tempB_load = load i32* %tempB_addr_1, align 16" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' ST_24 : Operation 121 [1/2] (2.32ns) ---> "%tempA_load_1 = load i32* %tempA_addr_2, align 4" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' ST_24 : Operation 122 [1/2] (2.32ns) ---> "%tempB_load_1 = load i32* %tempB_addr_2, align 4" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' ST_24 : Operation 123 [1/1] (0.00ns) ---> "%i_1_1 = or i3 %tmp_8, 2" [vector_mult/vector_mult.cpp:8] ST_24 : Operation 124 [1/1] (0.00ns) ---> "%tmp_2_2 = zext i3 %i_1_1 to i64" [vector_mult/vector_mult.cpp:9] ST_24 : Operation 125 [1/1] (0.00ns) ---> "%tempA_addr_3 = getelementptr inbounds [8 x i32]* %tempA, i64 0, i64 %tmp_2_2" [vector_mult/vector_mult.cpp:9] ST_24 : Operation 126 [2/2] (2.32ns) ---> "%tempA_load_2 = load i32* %tempA_addr_3, align 8" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' ST_24 : Operation 127 [1/1] (0.00ns) ---> "%tempB_addr_3 = getelementptr inbounds [8 x i32]* %tempB, i64 0, i64 %tmp_2_2" [vector_mult/vector_mult.cpp:9] ST_24 : Operation 128 [2/2] (2.32ns) ---> "%tempB_load_2 = load i32* %tempB_addr_3, align 8" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' ST_24 : Operation 129 [1/1] (0.00ns) ---> "%i_1_2 = or i3 %tmp_8, 3" [vector_mult/vector_mult.cpp:8] ST_24 : Operation 130 [1/1] (0.00ns) ---> "%tmp_2_3 = zext i3 %i_1_2 to i64" [vector_mult/vector_mult.cpp:9] ST_24 : Operation 131 [1/1] (0.00ns) ---> "%tempA_addr_4 = getelementptr inbounds [8 x i32]* %tempA, i64 0, i64 %tmp_2_3" [vector_mult/vector_mult.cpp:9] ST_24 : Operation 132 [2/2] (2.32ns) ---> "%tempA_load_3 = load i32* %tempA_addr_4, align 4" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' ST_24 : Operation 133 [1/1] (0.00ns) ---> "%tempB_addr_4 = getelementptr inbounds [8 x i32]* %tempB, i64 0, i64 %tmp_2_3" [vector_mult/vector_mult.cpp:9] ST_24 : Operation 134 [2/2] (2.32ns) ---> "%tempB_load_3 = load i32* %tempB_addr_4, align 4" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' ST_24 : Operation 135 [1/1] (1.73ns) ---> "%i_1_3 = add i4 4, %i" [vector_mult/vector_mult.cpp:8] ---> Core 14 'AddSub' : 8.51ns ST_25 : Operation 136 [1/1] (8.51ns) ---> "%tmp_3 = mul nsw i32 %tempA_load, %tempB_load" [vector_mult/vector_mult.cpp:9] ---> Core 16 'Mul' ST_25 : Operation 137 [1/1] (8.51ns) ---> "%tmp_3_1 = mul nsw i32 %tempA_load_1, %tempB_load_1" [vector_mult/vector_mult.cpp:9] ---> Core 16 'Mul' ST_25 : Operation 138 [1/2] (2.32ns) ---> "%tempA_load_2 = load i32* %tempA_addr_3, align 8" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' ST_25 : Operation 139 [1/2] (2.32ns) ---> "%tempB_load_2 = load i32* %tempB_addr_3, align 8" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' ST_25 : Operation 140 [1/2] (2.32ns) ---> "%tempA_load_3 = load i32* %tempA_addr_4, align 4" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' ST_25 : Operation 141 [1/2] (2.32ns) ---> "%tempB_load_3 = load i32* %tempB_addr_4, align 4" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' : 8.51ns ST_26 : Operation 142 [1/1] (0.00ns) ---> "%tempResult_addr = getelementptr inbounds [8 x i32]* %tempResult, i64 0, i64 %tmp_s" [vector_mult/vector_mult.cpp:9] ST_26 : Operation 143 [1/1] (2.32ns) ---> "store i32 %tmp_3, i32* %tempResult_addr, align 16" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' ST_26 : Operation 144 [1/1] (0.00ns) ---> "%tempResult_addr_4 = getelementptr inbounds [8 x i32]* %tempResult, i64 0, i64 %tmp_2_1" [vector_mult/vector_mult.cpp:9] ST_26 : Operation 145 [1/1] (2.32ns) ---> "store i32 %tmp_3_1, i32* %tempResult_addr_4, align 4" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' ST_26 : Operation 146 [1/1] (8.51ns) ---> "%tmp_3_2 = mul nsw i32 %tempA_load_2, %tempB_load_2" [vector_mult/vector_mult.cpp:9] ---> Core 16 'Mul' ST_26 : Operation 147 [1/1] (8.51ns) ---> "%tmp_3_3 = mul nsw i32 %tempA_load_3, %tempB_load_3" [vector_mult/vector_mult.cpp:9] ---> Core 16 'Mul' : 2.32ns ST_27 : Operation 148 [1/1] (0.00ns) ---> "%empty_6 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 2, i64 2, i64 2) nounwind" ST_27 : Operation 149 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecLoopName([17 x i8]* @p_str4) nounwind" [vector_mult/vector_mult.cpp:10] ST_27 : Operation 150 [1/1] (0.00ns) ---> "%tmp_2 = call i32 (...)* @_ssdm_op_SpecRegionBegin([17 x i8]* @p_str4) nounwind" [vector_mult/vector_mult.cpp:10] ST_27 : Operation 151 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind" [vector_mult/vector_mult.cpp:10] ST_27 : Operation 152 [1/1] (0.00ns) ---> "%empty_7 = call i32 (...)* @_ssdm_op_SpecRegionEnd([17 x i8]* @p_str4, i32 %tmp_2) nounwind" [vector_mult/vector_mult.cpp:9] ST_27 : Operation 153 [1/1] (0.00ns) ---> "%tempResult_addr_2 = getelementptr inbounds [8 x i32]* %tempResult, i64 0, i64 %tmp_2_2" [vector_mult/vector_mult.cpp:9] ST_27 : Operation 154 [1/1] (2.32ns) ---> "store i32 %tmp_3_2, i32* %tempResult_addr_2, align 8" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' ST_27 : Operation 155 [1/1] (0.00ns) ---> "%tempResult_addr_3 = getelementptr inbounds [8 x i32]* %tempResult, i64 0, i64 %tmp_2_3" [vector_mult/vector_mult.cpp:9] ST_27 : Operation 156 [1/1] (2.32ns) ---> "store i32 %tmp_3_3, i32* %tempResult_addr_3, align 4" [vector_mult/vector_mult.cpp:9] ---> Core 37 'RAM' ST_27 : Operation 157 [1/1] (0.00ns) ---> "br label %burst.rd.end4.0" [vector_mult/vector_mult.cpp:8] : 8.75ns ST_28 : Operation 158 [1/1] (8.75ns) ---> "%gmem_addr_wr_req = call i1 @_ssdm_op_WriteReq.m_axi.i32P(i32* %gmem_addr, i32 8)" [vector_mult/vector_mult.cpp:10] ---> Core 9 'm_axi' ST_28 : Operation 159 [1/1] (1.76ns) ---> "br label %burst.wr.header" : 2.32ns ST_29 : Operation 160 [1/1] (0.00ns) ---> "%indvar1 = phi i4 [ %indvar_next1, %burst.wr.body ], [ 0, %burst.wr.header.preheader ]" ST_29 : Operation 161 [1/1] (1.30ns) ---> "%exitcond2 = icmp eq i4 %indvar1, -8" ---> Core 25 'Cmp' ST_29 : Operation 162 [1/1] (1.73ns) ---> "%indvar_next1 = add i4 %indvar1, 1" ---> Core 14 'AddSub' ST_29 : Operation 163 [1/1] (0.00ns) ---> "br i1 %exitcond2, label %memcpy.tail, label %burst.wr.body" ST_29 : Operation 164 [1/1] (0.00ns) ---> "%tmp_5 = zext i4 %indvar1 to i64" [vector_mult/vector_mult.cpp:10] ST_29 : Operation 165 [1/1] (0.00ns) ---> "%tempResult_addr_1 = getelementptr [8 x i32]* %tempResult, i64 0, i64 %tmp_5" [vector_mult/vector_mult.cpp:10] ST_29 : Operation 166 [2/2] (2.32ns) ---> "%tempResult_load = load i32* %tempResult_addr_1, align 4" [vector_mult/vector_mult.cpp:10] ---> Core 37 'RAM' : 2.32ns ST_30 : Operation 167 [1/2] (2.32ns) ---> "%tempResult_load = load i32* %tempResult_addr_1, align 4" [vector_mult/vector_mult.cpp:10] ---> Core 37 'RAM' : 8.75ns ST_31 : Operation 168 [1/1] (0.00ns) ---> "%empty_8 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 8, i64 8, i64 8) nounwind" ST_31 : Operation 169 [1/1] (0.00ns) ---> "%burstwrite_rbegin = call i32 (...)* @_ssdm_op_SpecRegionBegin([18 x i8]* @burstwrite_OC_region) nounwind" ST_31 : Operation 170 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecPipeline(i32 1, i32 1, i32 1, i32 0, [1 x i8]* @p_str7)" ST_31 : Operation 171 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecLoopName([29 x i8]* @memcpy_OC_result_OC_s)" ST_31 : Operation 172 [1/1] (8.75ns) ---> "call void @_ssdm_op_Write.m_axi.i32P(i32* %gmem_addr, i32 %tempResult_load, i4 -1)" [vector_mult/vector_mult.cpp:10] ---> Core 9 'm_axi' ST_31 : Operation 173 [1/1] (0.00ns) ---> "%burstwrite_rend = call i32 (...)* @_ssdm_op_SpecRegionEnd([18 x i8]* @burstwrite_OC_region, i32 %burstwrite_rbegin) nounwind" ST_31 : Operation 174 [1/1] (0.00ns) ---> "br label %burst.wr.header" : 8.75ns ST_32 : Operation 175 [5/5] (8.75ns) ---> "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %gmem_addr)" [vector_mult/vector_mult.cpp:10] ---> Core 9 'm_axi' : 8.75ns ST_33 : Operation 176 [4/5] (8.75ns) ---> "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %gmem_addr)" [vector_mult/vector_mult.cpp:10] ---> Core 9 'm_axi' : 8.75ns ST_34 : Operation 177 [3/5] (8.75ns) ---> "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %gmem_addr)" [vector_mult/vector_mult.cpp:10] ---> Core 9 'm_axi' : 8.75ns ST_35 : Operation 178 [2/5] (8.75ns) ---> "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %gmem_addr)" [vector_mult/vector_mult.cpp:10] ---> Core 9 'm_axi' : 8.75ns ST_36 : Operation 179 [1/5] (8.75ns) ---> "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %gmem_addr)" [vector_mult/vector_mult.cpp:10] ---> Core 9 'm_axi' ST_36 : Operation 180 [1/1] (0.00ns) ---> "ret void" [vector_mult/vector_mult.cpp:11] ============================================================ + Verbose Summary: Binding ============================================================ STG Binding: ---------------- STG Properties BEGIN ---------------- - Is combinational: 0 - Is one-state seq: 0 - Is datapath-only: 0 - Is pipelined: 0 - Is top level: 1 Port [ Return ] is wired: 1; IO mode=ap_ctrl_hs:ce=0 Port [ gmem]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=2; type=4; pingpong=0; private_global=0; IO mode=m_axi:ce=0 Port [ A]: wired=1; compound=0; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=0; pingpong=0; private_global=0; IO mode=ap_none:ce=0 Port [ B]: wired=1; compound=0; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=0; pingpong=0; private_global=0; IO mode=ap_none:ce=0 Port [ result]: wired=1; compound=0; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=0; pingpong=0; private_global=0; IO mode=ap_none:ce=0 ---------------- STG Properties END ------------------ ---------------- Datapath Model BEGIN ---------------- result_read (read ) [ 0000000000000000000000000000000000000] B_read (read ) [ 0000000000000000000000000000000000000] A_read (read ) [ 0000000000000000000000000000000000000] result5 (partselect ) [ 0011111110000000000000000000000000000] B3 (partselect ) [ 0011111110000000000000000000000000000] A1 (partselect ) [ 0010000000000000000000000000000000000] tempA (alloca ) [ 0011111111111111111111111111000000000] tempB (alloca ) [ 0011111111111111111111111111000000000] tempResult (alloca ) [ 0011111111111111111111111111111100000] tmp_7 (zext ) [ 0000000000000000000000000000000000000] gmem_addr_2 (getelementptr ) [ 0001111111110000000000000000000000000] tmp_4 (zext ) [ 0000000000000000000000000000000000000] gmem_addr (getelementptr ) [ 0000000001111111111111111111111111111] tmp_6 (zext ) [ 0000000000000000000000000000000000000] gmem_addr_1 (getelementptr ) [ 0000000001111111111111000000000000000] StgValue_58 (specbitsmap ) [ 0000000000000000000000000000000000000] StgValue_59 (spectopmodule ) [ 0000000000000000000000000000000000000] StgValue_60 (specinterface ) [ 0000000000000000000000000000000000000] StgValue_61 (specinterface ) [ 0000000000000000000000000000000000000] StgValue_62 (specinterface ) [ 0000000000000000000000000000000000000] StgValue_63 (specinterface ) [ 0000000000000000000000000000000000000] StgValue_64 (specinterface ) [ 0000000000000000000000000000000000000] gmem_addr_2_rd_req (readreq ) [ 0000000000000000000000000000000000000] StgValue_66 (br ) [ 0000000011110000000000000000000000000] indvar (phi ) [ 0000000001110000000000000000000000000] exitcond1 (icmp ) [ 0000000001110000000000000000000000000] indvar_next (add ) [ 0000000011110000000000000000000000000] StgValue_70 (br ) [ 0000000000000000000000000000000000000] gmem_addr_2_read (read ) [ 0000000001010000000000000000000000000] empty (speclooptripcount) [ 0000000000000000000000000000000000000] burstread_rbegin (specregionbegin ) [ 0000000000000000000000000000000000000] StgValue_74 (specpipeline ) [ 0000000000000000000000000000000000000] StgValue_75 (specloopname ) [ 0000000000000000000000000000000000000] tmp (zext ) [ 0000000000000000000000000000000000000] tempA_addr (getelementptr ) [ 0000000000000000000000000000000000000] StgValue_78 (store ) [ 0000000000000000000000000000000000000] burstread_rend (specregionend ) [ 0000000000000000000000000000000000000] StgValue_80 (br ) [ 0000000011110000000000000000000000000] gmem_addr_1_rd_req (readreq ) [ 0000000000000000000000000000000000000] StgValue_88 (br ) [ 0000000000000000001111000000000000000] indvar7 (phi ) [ 0000000000000000000111000000000000000] exitcond9 (icmp ) [ 0000000000000000000111000000000000000] indvar_next8 (add ) [ 0000000000000000001111000000000000000] StgValue_92 (br ) [ 0000000000000000000000000000000000000] gmem_addr_1_read (read ) [ 0000000000000000000101000000000000000] empty_5 (speclooptripcount) [ 0000000000000000000000000000000000000] burstread_rbegin1 (specregionbegin ) [ 0000000000000000000000000000000000000] StgValue_96 (specpipeline ) [ 0000000000000000000000000000000000000] StgValue_97 (specloopname ) [ 0000000000000000000000000000000000000] tmp_1 (zext ) [ 0000000000000000000000000000000000000] tempB_addr (getelementptr ) [ 0000000000000000000000000000000000000] StgValue_100 (store ) [ 0000000000000000000000000000000000000] burstread_rend12 (specregionend ) [ 0000000000000000000000000000000000000] StgValue_102 (br ) [ 0000000000000000001111000000000000000] StgValue_103 (br ) [ 0000000000000000000000111111000000000] i (phi ) [ 0000000000000000000000011000000000000] exitcond (icmp ) [ 0000000000000000000000011111000000000] StgValue_106 (br ) [ 0000000000000000000000000000000000000] tmp_8 (trunc ) [ 0000000000000000000000001000000000000] tmp_s (zext ) [ 0000000000000000000000011110000000000] tempA_addr_1 (getelementptr ) [ 0000000000000000000000001000000000000] tempB_addr_1 (getelementptr ) [ 0000000000000000000000001000000000000] i_1_s (or ) [ 0000000000000000000000000000000000000] tmp_2_1 (zext ) [ 0000000000000000000000011110000000000] tempA_addr_2 (getelementptr ) [ 0000000000000000000000001000000000000] tempB_addr_2 (getelementptr ) [ 0000000000000000000000001000000000000] tempA_load (load ) [ 0000000000000000000000010100000000000] tempB_load (load ) [ 0000000000000000000000010100000000000] tempA_load_1 (load ) [ 0000000000000000000000010100000000000] tempB_load_1 (load ) [ 0000000000000000000000010100000000000] i_1_1 (or ) [ 0000000000000000000000000000000000000] tmp_2_2 (zext ) [ 0000000000000000000000011111000000000] tempA_addr_3 (getelementptr ) [ 0000000000000000000000010100000000000] tempB_addr_3 (getelementptr ) [ 0000000000000000000000010100000000000] i_1_2 (or ) [ 0000000000000000000000000000000000000] tmp_2_3 (zext ) [ 0000000000000000000000011111000000000] tempA_addr_4 (getelementptr ) [ 0000000000000000000000010100000000000] tempB_addr_4 (getelementptr ) [ 0000000000000000000000010100000000000] i_1_3 (add ) [ 0000000000000000000000111111000000000] tmp_3 (mul ) [ 0000000000000000000000001010000000000] tmp_3_1 (mul ) [ 0000000000000000000000001010000000000] tempA_load_2 (load ) [ 0000000000000000000000001010000000000] tempB_load_2 (load ) [ 0000000000000000000000001010000000000] tempA_load_3 (load ) [ 0000000000000000000000001010000000000] tempB_load_3 (load ) [ 0000000000000000000000001010000000000] tempResult_addr (getelementptr ) [ 0000000000000000000000000000000000000] StgValue_143 (store ) [ 0000000000000000000000000000000000000] tempResult_addr_4 (getelementptr ) [ 0000000000000000000000000000000000000] StgValue_145 (store ) [ 0000000000000000000000000000000000000] tmp_3_2 (mul ) [ 0000000000000000000000010001000000000] tmp_3_3 (mul ) [ 0000000000000000000000010001000000000] empty_6 (speclooptripcount) [ 0000000000000000000000000000000000000] StgValue_149 (specloopname ) [ 0000000000000000000000000000000000000] tmp_2 (specregionbegin ) [ 0000000000000000000000000000000000000] StgValue_151 (specpipeline ) [ 0000000000000000000000000000000000000] empty_7 (specregionend ) [ 0000000000000000000000000000000000000] tempResult_addr_2 (getelementptr ) [ 0000000000000000000000000000000000000] StgValue_154 (store ) [ 0000000000000000000000000000000000000] tempResult_addr_3 (getelementptr ) [ 0000000000000000000000000000000000000] StgValue_156 (store ) [ 0000000000000000000000000000000000000] StgValue_157 (br ) [ 0000000000000000000000111111000000000] gmem_addr_wr_req (writereq ) [ 0000000000000000000000000000000000000] StgValue_159 (br ) [ 0000000000000000000000000000111100000] indvar1 (phi ) [ 0000000000000000000000000000010000000] exitcond2 (icmp ) [ 0000000000000000000000000000011100000] indvar_next1 (add ) [ 0000000000000000000000000000111100000] StgValue_163 (br ) [ 0000000000000000000000000000000000000] tmp_5 (zext ) [ 0000000000000000000000000000000000000] tempResult_addr_1 (getelementptr ) [ 0000000000000000000000000000011000000] tempResult_load (load ) [ 0000000000000000000000000000010100000] empty_8 (speclooptripcount) [ 0000000000000000000000000000000000000] burstwrite_rbegin (specregionbegin ) [ 0000000000000000000000000000000000000] StgValue_170 (specpipeline ) [ 0000000000000000000000000000000000000] StgValue_171 (specloopname ) [ 0000000000000000000000000000000000000] StgValue_172 (write ) [ 0000000000000000000000000000000000000] burstwrite_rend (specregionend ) [ 0000000000000000000000000000000000000] StgValue_174 (br ) [ 0000000000000000000000000000111100000] gmem_addr_wr_resp (writeresp ) [ 0000000000000000000000000000000000000] StgValue_180 (ret ) [ 0000000000000000000000000000000000000] ---------------- Datapath Model END ------------------ * FSMD analyzer results: - Output states: Port: gmem | {28 31 32 33 34 35 36 } - Input state : Port: vector_mult : gmem | {2 3 4 5 6 7 8 10 12 13 14 15 16 17 18 20 } Port: vector_mult : A | {1 } Port: vector_mult : B | {1 } Port: vector_mult : result | {1 } - Chain level: State 1 State 2 gmem_addr_2 : 1 gmem_addr_2_rd_req : 2 State 3 State 4 State 5 State 6 State 7 State 8 gmem_addr : 1 gmem_addr_1 : 1 State 9 exitcond1 : 1 indvar_next : 1 StgValue_70 : 2 State 10 State 11 tempA_addr : 1 StgValue_78 : 2 burstread_rend : 1 State 12 State 13 State 14 State 15 State 16 State 17 State 18 State 19 exitcond9 : 1 indvar_next8 : 1 StgValue_92 : 2 State 20 State 21 tempB_addr : 1 StgValue_100 : 2 burstread_rend12 : 1 State 22 State 23 exitcond : 1 StgValue_106 : 2 tmp_8 : 1 tmp_s : 1 tempA_addr_1 : 2 tempA_load : 3 tempB_addr_1 : 2 tempB_load : 3 i_1_s : 2 tmp_2_1 : 2 tempA_addr_2 : 3 tempA_load_1 : 4 tempB_addr_2 : 3 tempB_load_1 : 4 State 24 tempA_addr_3 : 1 tempA_load_2 : 2 tempB_addr_3 : 1 tempB_load_2 : 2 tempA_addr_4 : 1 tempA_load_3 : 2 tempB_addr_4 : 1 tempB_load_3 : 2 State 25 State 26 StgValue_143 : 1 StgValue_145 : 1 State 27 empty_7 : 1 StgValue_154 : 1 StgValue_156 : 1 State 28 State 29 exitcond2 : 1 indvar_next1 : 1 StgValue_163 : 2 tmp_5 : 1 tempResult_addr_1 : 2 tempResult_load : 3 State 30 State 31 burstwrite_rend : 1 State 32 State 33 State 34 State 35 State 36 ============================================================ + Verbose Summary: Datapath Resource usage ============================================================ * Functional unit list: |----------|------------------------------|---------|---------|---------| | Operation| Functional Unit | DSP48E | FF | LUT | |----------|------------------------------|---------|---------|---------| | | indvar_next_fu_467 | 0 | 0 | 13 | | add | indvar_next8_fu_484 | 0 | 0 | 13 | | | i_1_3_fu_545 | 0 | 0 | 13 | | | indvar_next1_fu_557 | 0 | 0 | 13 | |----------|------------------------------|---------|---------|---------| | mul | grp_fu_381 | 3 | 0 | 20 | | | grp_fu_387 | 3 | 0 | 20 | |----------|------------------------------|---------|---------|---------| | | exitcond1_fu_461 | 0 | 0 | 9 | | icmp | exitcond9_fu_478 | 0 | 0 | 9 | | | exitcond_fu_495 | 0 | 0 | 9 | | | exitcond2_fu_551 | 0 | 0 | 9 | |----------|------------------------------|---------|---------|---------| | | result_read_read_fu_130 | 0 | 0 | 0 | | | B_read_read_fu_136 | 0 | 0 | 0 | | read | A_read_read_fu_142 | 0 | 0 | 0 | | | gmem_addr_2_read_read_fu_155 | 0 | 0 | 0 | | | gmem_addr_1_read_read_fu_167 | 0 | 0 | 0 | |----------|------------------------------|---------|---------|---------| | readreq | grp_readreq_fu_148 | 0 | 0 | 0 | | | grp_readreq_fu_160 | 0 | 0 | 0 | |----------|------------------------------|---------|---------|---------| | writeresp| grp_writeresp_fu_172 | 0 | 0 | 0 | |----------|------------------------------|---------|---------|---------| | write | StgValue_172_write_fu_179 | 0 | 0 | 0 | |----------|------------------------------|---------|---------|---------| | | result5_fu_403 | 0 | 0 | 0 | |partselect| B3_fu_413 | 0 | 0 | 0 | | | A1_fu_423 | 0 | 0 | 0 | |----------|------------------------------|---------|---------|---------| | | tmp_7_fu_433 | 0 | 0 | 0 | | | tmp_4_fu_443 | 0 | 0 | 0 | | | tmp_6_fu_452 | 0 | 0 | 0 | | | tmp_fu_473 | 0 | 0 | 0 | | zext | tmp_1_fu_490 | 0 | 0 | 0 | | | tmp_s_fu_505 | 0 | 0 | 0 | | | tmp_2_1_fu_517 | 0 | 0 | 0 | | | tmp_2_2_fu_528 | 0 | 0 | 0 | | | tmp_2_3_fu_539 | 0 | 0 | 0 | | | tmp_5_fu_563 | 0 | 0 | 0 | |----------|------------------------------|---------|---------|---------| | trunc | tmp_8_fu_501 | 0 | 0 | 0 | |----------|------------------------------|---------|---------|---------| | | i_1_s_fu_511 | 0 | 0 | 0 | | or | i_1_1_fu_523 | 0 | 0 | 0 | | | i_1_2_fu_534 | 0 | 0 | 0 | |----------|------------------------------|---------|---------|---------| | Total | | 6 | 0 | 128 | |----------|------------------------------|---------|---------|---------| Memories: +----------+--------+--------+--------+ | | BRAM | FF | LUT | +----------+--------+--------+--------+ | tempA | 0 | 64 | 4 | | tempB | 0 | 64 | 4 | |tempResult| 2 | 0 | 0 | +----------+--------+--------+--------+ | Total | 2 | 128 | 8 | +----------+--------+--------+--------+ * Register list: +-------------------------+--------+ | | FF | +-------------------------+--------+ | A1_reg_578 | 30 | | B3_reg_573 | 30 | | exitcond1_reg_601 | 1 | | exitcond2_reg_704 | 1 | | exitcond9_reg_615 | 1 | | exitcond_reg_629 | 1 | | gmem_addr_1_read_reg_624| 32 | | gmem_addr_1_reg_595 | 32 | | gmem_addr_2_read_reg_610| 32 | | gmem_addr_2_reg_583 | 32 | | gmem_addr_reg_589 | 32 | | i_1_3_reg_699 | 4 | | i_reg_338 | 4 | | indvar1_reg_350 | 4 | | indvar7_reg_326 | 4 | | indvar_next1_reg_708 | 4 | | indvar_next8_reg_619 | 4 | | indvar_next_reg_605 | 4 | | indvar_reg_314 | 4 | | reg_361 | 32 | | reg_366 | 32 | | reg_371 | 32 | | reg_376 | 32 | | reg_393 | 32 | | reg_398 | 32 | | result5_reg_568 | 30 | | tempA_addr_1_reg_644 | 3 | | tempA_addr_2_reg_659 | 3 | | tempA_addr_3_reg_674 | 3 | | tempA_addr_4_reg_689 | 3 | | tempB_addr_1_reg_649 | 3 | | tempB_addr_2_reg_664 | 3 | | tempB_addr_3_reg_679 | 3 | | tempB_addr_4_reg_694 | 3 | |tempResult_addr_1_reg_713| 3 | | tempResult_load_reg_718 | 32 | | tmp_2_1_reg_654 | 64 | | tmp_2_2_reg_669 | 64 | | tmp_2_3_reg_684 | 64 | | tmp_8_reg_633 | 3 | | tmp_s_reg_639 | 64 | +-------------------------+--------+ | Total | 796 | +-------------------------+--------+ * Multiplexer (MUX) list: |----------------------|------|------|------|--------||---------||---------| | Comp | Pin | Size | BW | S x BW || Delay || LUT | |----------------------|------|------|------|--------||---------||---------| | grp_readreq_fu_148 | p1 | 2 | 32 | 64 || 9 | | grp_writeresp_fu_172 | p0 | 2 | 1 | 2 | | grp_access_fu_194 | p0 | 5 | 3 | 15 || 27 | | grp_access_fu_194 | p3 | 4 | 3 | 12 || 21 | | grp_access_fu_205 | p0 | 5 | 3 | 15 || 27 | | grp_access_fu_205 | p3 | 4 | 3 | 12 || 21 | | grp_access_fu_278 | p0 | 4 | 3 | 12 || 21 | | grp_access_fu_278 | p3 | 2 | 3 | 6 || 9 | | indvar_reg_314 | p0 | 2 | 4 | 8 || 9 | | indvar7_reg_326 | p0 | 2 | 4 | 8 || 9 | | i_reg_338 | p0 | 2 | 4 | 8 || 9 | | reg_361 | p0 | 2 | 32 | 64 || 9 | | reg_366 | p0 | 2 | 32 | 64 || 9 | | reg_371 | p0 | 2 | 32 | 64 || 9 | | reg_376 | p0 | 2 | 32 | 64 || 9 | |----------------------|------|------|------|--------||---------||---------| | Total | | | | 418 || 27.084 || 198 | |----------------------|------|------|------|--------||---------||---------| * Summary: +-----------+--------+--------+--------+--------+--------+ | | BRAM | DSP48E | Delay | FF | LUT | +-----------+--------+--------+--------+--------+--------+ | Function | - | 6 | - | 0 | 128 | | Memory | 2 | - | - | 128 | 8 | |Multiplexer| - | - | 27 | - | 198 | | Register | - | - | - | 796 | - | +-----------+--------+--------+--------+--------+--------+ | Total | 2 | 6 | 27 | 924 | 334 | +-----------+--------+--------+--------+--------+--------+