; ModuleID = '/home/hakta/Documents/vector_mult/solution2/.autopilot/db/a.o.2.bc'
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@vector_mult_str = internal unnamed_addr constant [12 x i8] c"vector_mult\00"
@mode5 = internal constant [10 x i8] c"s_axilite\00"
@mode3 = internal constant [10 x i8] c"s_axilite\00"
@mode = internal constant [10 x i8] c"s_axilite\00"
@memcpy_OC_tempB_OC_B = internal unnamed_addr constant [15 x i8] c"memcpy.tempB.B\00"
@memcpy_OC_tempA_OC_A = internal unnamed_addr constant [15 x i8] c"memcpy.tempA.A\00"
@memcpy_OC_result_OC_s = internal unnamed_addr constant [29 x i8] c"memcpy.result.tempResult.gep\00"
@burstwrite_OC_region = internal unnamed_addr constant [18 x i8] c"burstwrite.region\00"
@burstread_OC_region_s = internal unnamed_addr constant [17 x i8] c"burstread.region\00"
@bundle6 = internal constant [1 x i8] zeroinitializer
@bundle4 = internal constant [1 x i8] zeroinitializer
@bundle = internal constant [1 x i8] zeroinitializer
@p_str7 = internal unnamed_addr constant [1 x i8] zeroinitializer
@p_str6 = internal unnamed_addr constant [1 x i8] zeroinitializer
@p_str5 = internal unnamed_addr constant [1 x i8] zeroinitializer
@p_str4 = private unnamed_addr constant [17 x i8] c"vector_mult_loop\00", align 1
@p_str3 = private unnamed_addr constant [6 x i8] c"slave\00", align 1
@p_str2 = private unnamed_addr constant [6 x i8] c"m_axi\00", align 1
@p_str1 = private unnamed_addr constant [1 x i8] zeroinitializer, align 1
@p_str = private unnamed_addr constant [10 x i8] c"s_axilite\00", align 1

define void @vector_mult(i32* %gmem, i32 %A, i32 %B, i32 %result) {
  %result_read = call i32 @_ssdm_op_Read.s_axilite.i32(i32 %result)
  %B_read = call i32 @_ssdm_op_Read.s_axilite.i32(i32 %B)
  %A_read = call i32 @_ssdm_op_Read.s_axilite.i32(i32 %A)
  %result5 = call i30 @_ssdm_op_PartSelect.i30.i32.i32.i32(i32 %result_read, i32 2, i32 31)
  %tmp_4 = zext i30 %result5 to i64
  %gmem_addr = getelementptr i32* %gmem, i64 %tmp_4
  %B3 = call i30 @_ssdm_op_PartSelect.i30.i32.i32.i32(i32 %B_read, i32 2, i32 31)
  %tmp_6 = zext i30 %B3 to i64
  %gmem_addr_1 = getelementptr i32* %gmem, i64 %tmp_6
  %A1 = call i30 @_ssdm_op_PartSelect.i30.i32.i32.i32(i32 %A_read, i32 2, i32 31)
  %tmp_7 = zext i30 %A1 to i64
  %gmem_addr_2 = getelementptr i32* %gmem, i64 %tmp_7
  call void (...)* @_ssdm_op_SpecBitsMap(i32* %gmem), !map !11
  call void (...)* @_ssdm_op_SpecTopModule([12 x i8]* @vector_mult_str) nounwind
  %tempA = alloca [8 x i32], align 16
  %tempB = alloca [8 x i32], align 16
  %tempResult = alloca [8 x i32], align 16
  call void (...)* @_ssdm_op_SpecInterface(i32 0, [10 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1, [1 x i8]* @p_str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1) nounwind
  call void (...)* @_ssdm_op_SpecInterface(i32 %result, [10 x i8]* @mode5, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @bundle6, [6 x i8]* @p_str3, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)
  call void (...)* @_ssdm_op_SpecInterface(i32 %B, [10 x i8]* @mode3, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @bundle4, [6 x i8]* @p_str3, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)
  call void (...)* @_ssdm_op_SpecInterface(i32* %gmem, [6 x i8]* @p_str2, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @p_str1, [6 x i8]* @p_str3, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)
  call void (...)* @_ssdm_op_SpecInterface(i32 %A, [10 x i8]* @mode, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @bundle, [6 x i8]* @p_str3, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)
  %gmem_addr_2_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 8)
  br label %burst.rd.header

burst.rd.header:                                  ; preds = %burst.rd.body, %0
  %indvar = phi i4 [ 0, %0 ], [ %indvar_next, %burst.rd.body ]
  %exitcond1 = icmp eq i4 %indvar, -8
  %indvar_next = add i4 %indvar, 1
  br i1 %exitcond1, label %burst.rd.header5.preheader, label %burst.rd.body

burst.rd.header5.preheader:                       ; preds = %burst.rd.header
  %gmem_addr_1_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 8)
  br label %burst.rd.header5

burst.rd.body:                                    ; preds = %burst.rd.header
  %empty = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 8, i64 8, i64 8) nounwind
  %burstread_rbegin = call i32 (...)* @_ssdm_op_SpecRegionBegin([17 x i8]* @burstread_OC_region_s) nounwind
  call void (...)* @_ssdm_op_SpecPipeline(i32 1, i32 1, i32 1, i32 0, [1 x i8]* @p_str5)
  call void (...)* @_ssdm_op_SpecLoopName([15 x i8]* @memcpy_OC_tempA_OC_A)
  %tmp = zext i4 %indvar to i64
  %gmem_addr_2_read = call i32 @_ssdm_op_Read.m_axi.i32P(i32* %gmem_addr_2)
  %tempA_addr = getelementptr [8 x i32]* %tempA, i64 0, i64 %tmp
  store i32 %gmem_addr_2_read, i32* %tempA_addr, align 4
  %burstread_rend = call i32 (...)* @_ssdm_op_SpecRegionEnd([17 x i8]* @burstread_OC_region_s, i32 %burstread_rbegin) nounwind
  br label %burst.rd.header

burst.rd.header5:                                 ; preds = %burst.rd.header5.preheader, %burst.rd.body6
  %indvar7 = phi i4 [ %indvar_next8, %burst.rd.body6 ], [ 0, %burst.rd.header5.preheader ]
  %exitcond9 = icmp eq i4 %indvar7, -8
  %indvar_next8 = add i4 %indvar7, 1
  br i1 %exitcond9, label %burst.rd.end4.0.preheader, label %burst.rd.body6

burst.rd.end4.0.preheader:                        ; preds = %burst.rd.header5
  br label %burst.rd.end4.0

burst.rd.body6:                                   ; preds = %burst.rd.header5
  %empty_5 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 8, i64 8, i64 8) nounwind
  %burstread_rbegin1 = call i32 (...)* @_ssdm_op_SpecRegionBegin([17 x i8]* @burstread_OC_region_s) nounwind
  call void (...)* @_ssdm_op_SpecPipeline(i32 1, i32 1, i32 1, i32 0, [1 x i8]* @p_str6)
  call void (...)* @_ssdm_op_SpecLoopName([15 x i8]* @memcpy_OC_tempB_OC_B)
  %tmp_1 = zext i4 %indvar7 to i64
  %gmem_addr_1_read = call i32 @_ssdm_op_Read.m_axi.i32P(i32* %gmem_addr_1)
  %tempB_addr = getelementptr [8 x i32]* %tempB, i64 0, i64 %tmp_1
  store i32 %gmem_addr_1_read, i32* %tempB_addr, align 4
  %burstread_rend12 = call i32 (...)* @_ssdm_op_SpecRegionEnd([17 x i8]* @burstread_OC_region_s, i32 %burstread_rbegin1) nounwind
  br label %burst.rd.header5

burst.rd.end4.0:                                  ; preds = %burst.rd.end4.0.preheader, %burst.rd.end4.1
  %i = phi i4 [ %i_1_3, %burst.rd.end4.1 ], [ 0, %burst.rd.end4.0.preheader ]
  %exitcond = icmp eq i4 %i, -8
  br i1 %exitcond, label %burst.wr.header.preheader, label %burst.rd.end4.1

burst.wr.header.preheader:                        ; preds = %burst.rd.end4.0
  %gmem_addr_wr_req = call i1 @_ssdm_op_WriteReq.m_axi.i32P(i32* %gmem_addr, i32 8)
  br label %burst.wr.header

burst.rd.end4.1:                                  ; preds = %burst.rd.end4.0
  %tmp_8 = trunc i4 %i to i3
  %empty_6 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 2, i64 2, i64 2) nounwind
  call void (...)* @_ssdm_op_SpecLoopName([17 x i8]* @p_str4) nounwind
  %tmp_2 = call i32 (...)* @_ssdm_op_SpecRegionBegin([17 x i8]* @p_str4) nounwind
  call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind
  %tmp_s = zext i4 %i to i64
  %tempA_addr_1 = getelementptr inbounds [8 x i32]* %tempA, i64 0, i64 %tmp_s
  %tempA_load = load i32* %tempA_addr_1, align 16
  %tempB_addr_1 = getelementptr inbounds [8 x i32]* %tempB, i64 0, i64 %tmp_s
  %tempB_load = load i32* %tempB_addr_1, align 16
  %tmp_3 = mul nsw i32 %tempA_load, %tempB_load
  %tempResult_addr = getelementptr inbounds [8 x i32]* %tempResult, i64 0, i64 %tmp_s
  store i32 %tmp_3, i32* %tempResult_addr, align 16
  %empty_7 = call i32 (...)* @_ssdm_op_SpecRegionEnd([17 x i8]* @p_str4, i32 %tmp_2) nounwind
  %i_1_s = or i3 %tmp_8, 1
  %tmp_2_1 = zext i3 %i_1_s to i64
  %tempA_addr_2 = getelementptr inbounds [8 x i32]* %tempA, i64 0, i64 %tmp_2_1
  %tempA_load_1 = load i32* %tempA_addr_2, align 4
  %tempB_addr_2 = getelementptr inbounds [8 x i32]* %tempB, i64 0, i64 %tmp_2_1
  %tempB_load_1 = load i32* %tempB_addr_2, align 4
  %tmp_3_1 = mul nsw i32 %tempA_load_1, %tempB_load_1
  %tempResult_addr_4 = getelementptr inbounds [8 x i32]* %tempResult, i64 0, i64 %tmp_2_1
  store i32 %tmp_3_1, i32* %tempResult_addr_4, align 4
  %i_1_1 = or i3 %tmp_8, 2
  %tmp_2_2 = zext i3 %i_1_1 to i64
  %tempA_addr_3 = getelementptr inbounds [8 x i32]* %tempA, i64 0, i64 %tmp_2_2
  %tempA_load_2 = load i32* %tempA_addr_3, align 8
  %tempB_addr_3 = getelementptr inbounds [8 x i32]* %tempB, i64 0, i64 %tmp_2_2
  %tempB_load_2 = load i32* %tempB_addr_3, align 8
  %tmp_3_2 = mul nsw i32 %tempA_load_2, %tempB_load_2
  %tempResult_addr_2 = getelementptr inbounds [8 x i32]* %tempResult, i64 0, i64 %tmp_2_2
  store i32 %tmp_3_2, i32* %tempResult_addr_2, align 8
  %i_1_2 = or i3 %tmp_8, 3
  %tmp_2_3 = zext i3 %i_1_2 to i64
  %tempA_addr_4 = getelementptr inbounds [8 x i32]* %tempA, i64 0, i64 %tmp_2_3
  %tempA_load_3 = load i32* %tempA_addr_4, align 4
  %tempB_addr_4 = getelementptr inbounds [8 x i32]* %tempB, i64 0, i64 %tmp_2_3
  %tempB_load_3 = load i32* %tempB_addr_4, align 4
  %tmp_3_3 = mul nsw i32 %tempA_load_3, %tempB_load_3
  %tempResult_addr_3 = getelementptr inbounds [8 x i32]* %tempResult, i64 0, i64 %tmp_2_3
  store i32 %tmp_3_3, i32* %tempResult_addr_3, align 4
  %i_1_3 = add i4 4, %i
  br label %burst.rd.end4.0

burst.wr.header:                                  ; preds = %burst.wr.header.preheader, %burst.wr.body
  %indvar1 = phi i4 [ %indvar_next1, %burst.wr.body ], [ 0, %burst.wr.header.preheader ]
  %exitcond2 = icmp eq i4 %indvar1, -8
  %indvar_next1 = add i4 %indvar1, 1
  br i1 %exitcond2, label %memcpy.tail, label %burst.wr.body

burst.wr.body:                                    ; preds = %burst.wr.header
  %empty_8 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 8, i64 8, i64 8) nounwind
  %burstwrite_rbegin = call i32 (...)* @_ssdm_op_SpecRegionBegin([18 x i8]* @burstwrite_OC_region) nounwind
  call void (...)* @_ssdm_op_SpecPipeline(i32 1, i32 1, i32 1, i32 0, [1 x i8]* @p_str7)
  call void (...)* @_ssdm_op_SpecLoopName([29 x i8]* @memcpy_OC_result_OC_s)
  %tmp_5 = zext i4 %indvar1 to i64
  %tempResult_addr_1 = getelementptr [8 x i32]* %tempResult, i64 0, i64 %tmp_5
  %tempResult_load = load i32* %tempResult_addr_1, align 4
  call void @_ssdm_op_Write.m_axi.i32P(i32* %gmem_addr, i32 %tempResult_load, i4 -1)
  %burstwrite_rend = call i32 (...)* @_ssdm_op_SpecRegionEnd([18 x i8]* @burstwrite_OC_region, i32 %burstwrite_rbegin) nounwind
  br label %burst.wr.header

memcpy.tail:                                      ; preds = %burst.wr.header
  %gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %gmem_addr)
  ret void
}

declare i32 @llvm.part.select.i32(i32, i32, i32) nounwind readnone

declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone

declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone

define weak i1 @_ssdm_op_WriteResp.m_axi.i32P(i32*) {
entry:
  ret i1 true
}

define weak i1 @_ssdm_op_WriteReq.m_axi.i32P(i32*, i32) {
entry:
  ret i1 true
}

define weak void @_ssdm_op_Write.m_axi.i32P(i32*, i32, i4) {
entry:
  ret void
}

define weak void @_ssdm_op_SpecTopModule(...) {
entry:
  ret void
}

define weak i32 @_ssdm_op_SpecRegionEnd(...) {
entry:
  ret i32 0
}

define weak i32 @_ssdm_op_SpecRegionBegin(...) {
entry:
  ret i32 0
}

define weak void @_ssdm_op_SpecPipeline(...) nounwind {
entry:
  ret void
}

define weak i32 @_ssdm_op_SpecLoopTripCount(...) {
entry:
  ret i32 0
}

define weak void @_ssdm_op_SpecLoopName(...) nounwind {
entry:
  ret void
}

define weak void @_ssdm_op_SpecInterface(...) nounwind {
entry:
  ret void
}

define weak void @_ssdm_op_SpecBitsMap(...) {
entry:
  ret void
}

define weak i1 @_ssdm_op_ReadReq.m_axi.i32P(i32*, i32) {
entry:
  ret i1 true
}

define weak i32 @_ssdm_op_Read.s_axilite.i32(i32) {
entry:
  ret i32 %0
}

define weak i32 @_ssdm_op_Read.m_axi.i32P(i32*) {
entry:
  %empty = load i32* %0
  ret i32 %empty
}

define weak i30 @_ssdm_op_PartSelect.i30.i32.i32.i32(i32, i32, i32) nounwind readnone {
entry:
  %empty = call i32 @llvm.part.select.i32(i32 %0, i32 %1, i32 %2)
  %empty_9 = trunc i32 %empty to i30
  ret i30 %empty_9
}

declare i3 @_ssdm_op_PartSelect.i3.i4.i32.i32(i4, i32, i32) nounwind readnone

!opencl.kernels = !{!0}
!hls.encrypted.func = !{}
!llvm.map.gv = !{}
!axi4.master.portmap = !{!7}
!axi4.slave.bundlemap = !{!8, !9, !10}

!0 = metadata !{null, metadata !1, metadata !2, metadata !3, metadata !4, metadata !5, metadata !6}
!1 = metadata !{metadata !"kernel_arg_addr_space", i32 1, i32 1, i32 1}
!2 = metadata !{metadata !"kernel_arg_access_qual", metadata !"none", metadata !"none", metadata !"none"}
!3 = metadata !{metadata !"kernel_arg_type", metadata !"int*", metadata !"int*", metadata !"int*"}
!4 = metadata !{metadata !"kernel_arg_type_qual", metadata !"", metadata !"", metadata !""}
!5 = metadata !{metadata !"kernel_arg_name", metadata !"A", metadata !"B", metadata !"result"}
!6 = metadata !{metadata !"reqd_work_group_size", i32 1, i32 1, i32 1}
!7 = metadata !{metadata !"gmem", metadata !"A", metadata !"READONLY", metadata !"B", metadata !"READONLY", metadata !"result", metadata !"WRITEONLY"}
!8 = metadata !{metadata !"A", metadata !""}
!9 = metadata !{metadata !"B", metadata !""}
!10 = metadata !{metadata !"result", metadata !""}
!11 = metadata !{metadata !12}
!12 = metadata !{i32 0, i32 31, metadata !13}
!13 = metadata !{metadata !14, metadata !17, metadata !18}
!14 = metadata !{metadata !"A", metadata !15, metadata !"int", i32 0, i32 31}
!15 = metadata !{metadata !16}
!16 = metadata !{i32 0, i32 7, i32 1}
!17 = metadata !{metadata !"B", metadata !15, metadata !"int", i32 0, i32 31}
!18 = metadata !{metadata !"result", metadata !15, metadata !"int", i32 0, i32 31}