================================================================ == Vivado HLS Report for 'vector_mult' ================================================================ * Date: Mon Mar 19 11:20:05 2018 * Version: 2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017) * Project: vector_mult * Solution: solution1 * Product family: zynq * Target device: xc7z020clg484-1 ================================================================ == Performance Estimates ================================================================ + Timing (ns): * Summary: +--------+-------+----------+------------+ | Clock | Target| Estimated| Uncertainty| +--------+-------+----------+------------+ |ap_clk | 10.00| 8.75| 1.25| +--------+-------+----------+------------+ + Latency (clock cycles): * Summary: +-----+-----+-----+-----+---------+ | Latency | Interval | Pipeline| | min | max | min | max | Type | +-----+-----+-----+-----+---------+ | 32| 32| 32| 32| none | +-----+-----+-----+-----+---------+ + Detail: * Instance: N/A * Loop: +--------------------+-----+-----+----------+-----------+-----------+------+----------+ | | Latency | Iteration| Initiation Interval | Trip | | | Loop Name | min | max | Latency | achieved | target | Count| Pipelined| +--------------------+-----+-----+----------+-----------+-----------+------+----------+ |- vector_mult_loop | 25| 25| 12| 2| 1| 8| yes | +--------------------+-----+-----+----------+-----------+-----------+------+----------+ ================================================================ == Utilization Estimates ================================================================ * Summary: +-----------------+---------+-------+--------+-------+ | Name | BRAM_18K| DSP48E| FF | LUT | +-----------------+---------+-------+--------+-------+ |DSP | -| -| -| -| |Expression | -| 3| 0| 224| |FIFO | -| -| -| -| |Instance | 2| -| 662| 812| |Memory | -| -| -| -| |Multiplexer | -| -| -| 170| |Register | 0| -| 399| 32| +-----------------+---------+-------+--------+-------+ |Total | 2| 3| 1061| 1238| +-----------------+---------+-------+--------+-------+ |Available | 280| 220| 106400| 53200| +-----------------+---------+-------+--------+-------+ |Utilization (%) | ~0 | 1| ~0 | 2| +-----------------+---------+-------+--------+-------+ + Detail: * Instance: +------------------------------+----------------------------+---------+-------+-----+-----+ | Instance | Module | BRAM_18K| DSP48E| FF | LUT | +------------------------------+----------------------------+---------+-------+-----+-----+ |vector_mult_AXILiteS_s_axi_U |vector_mult_AXILiteS_s_axi | 0| 0| 150| 232| |vector_mult_gmem_m_axi_U |vector_mult_gmem_m_axi | 2| 0| 512| 580| +------------------------------+----------------------------+---------+-------+-----+-----+ |Total | | 2| 0| 662| 812| +------------------------------+----------------------------+---------+-------+-----+-----+ * DSP48: N/A * Memory: N/A * FIFO: N/A * Expression: +-----------------------------------+----------+-------+---+----+------------+------------+ | Variable Name | Operation| DSP48E| FF| LUT| Bitwidth P0| Bitwidth P1| +-----------------------------------+----------+-------+---+----+------------+------------+ |tmp_1_fu_249_p2 | * | 3| 0| 20| 32| 32| |A2_sum_fu_219_p2 | + | 0| 0| 38| 31| 31| |B4_sum_fu_224_p2 | + | 0| 0| 38| 31| 31| |i_1_fu_209_p2 | + | 0| 0| 13| 4| 1| |ap_block_pp0_stage0_01001 | and | 0| 0| 8| 1| 1| |ap_block_pp0_stage1_01001 | and | 0| 0| 8| 1| 1| |ap_block_state11_pp0_stage0_iter4 | and | 0| 0| 8| 1| 1| |ap_block_state12_pp0_stage1_iter4 | and | 0| 0| 8| 1| 1| |ap_block_state14_io | and | 0| 0| 8| 1| 1| |ap_block_state4_io | and | 0| 0| 8| 1| 1| |ap_condition_404 | and | 0| 0| 8| 1| 1| |ap_condition_415 | and | 0| 0| 8| 1| 1| |ap_condition_552 | and | 0| 0| 8| 1| 1| |exitcond_fu_203_p2 | icmp | 0| 0| 11| 4| 5| |ap_block_pp0_stage0_11001 | or | 0| 0| 8| 1| 1| |ap_block_pp0_stage1_11001 | or | 0| 0| 8| 1| 1| |ap_enable_pp0 | xor | 0| 0| 8| 1| 2| |ap_enable_reg_pp0_iter1 | xor | 0| 0| 8| 2| 1| +-----------------------------------+----------+-------+---+----+------------+------------+ |Total | | 3| 0| 224| 116| 114| +-----------------------------------+----------+-------+---+----+------------+------------+ * Multiplexer: +-----------------------------+----+-----------+-----+-----------+ | Name | LUT| Input Size| Bits| Total Bits| +-----------------------------+----+-----------+-----+-----------+ |ap_NS_fsm | 47| 10| 1| 10| |ap_enable_reg_pp0_iter1 | 9| 2| 1| 2| |ap_enable_reg_pp0_iter5 | 9| 2| 1| 2| |ap_phi_mux_i_phi_fu_150_p4 | 9| 2| 4| 8| |ap_sig_ioackin_gmem_ARREADY | 9| 2| 1| 2| |ap_sig_ioackin_gmem_AWREADY | 9| 2| 1| 2| |ap_sig_ioackin_gmem_WREADY | 9| 2| 1| 2| |gmem_ARADDR | 15| 3| 32| 96| |gmem_blk_n_AR | 9| 2| 1| 2| |gmem_blk_n_AW | 9| 2| 1| 2| |gmem_blk_n_B | 9| 2| 1| 2| |gmem_blk_n_R | 9| 2| 1| 2| |gmem_blk_n_W | 9| 2| 1| 2| |i_reg_146 | 9| 2| 4| 8| +-----------------------------+----+-----------+-----+-----------+ |Total | 170| 37| 51| 142| +-----------------------------+----+-----------+-----+-----------+ * Register: +-----------------------------+----+----+-----+-----------+ | Name | FF | LUT| Bits| Const Bits| +-----------------------------+----+----+-----+-----------+ |A2_sum_reg_293 | 31| 0| 31| 0| |B4_sum_reg_298 | 31| 0| 31| 0| |ap_CS_fsm | 9| 0| 9| 0| |ap_enable_reg_pp0_iter0 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter1 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter2 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter3 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter4 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter5 | 1| 0| 1| 0| |ap_reg_ioackin_gmem_ARREADY | 1| 0| 1| 0| |ap_reg_ioackin_gmem_AWREADY | 1| 0| 1| 0| |ap_reg_ioackin_gmem_WREADY | 1| 0| 1| 0| |exitcond_reg_284 | 1| 0| 1| 0| |gmem_addr_1_read_reg_315 | 32| 0| 32| 0| |gmem_addr_2_read_reg_320 | 32| 0| 32| 0| |i_1_reg_288 | 4| 0| 4| 0| |i_reg_146 | 4| 0| 4| 0| |result5_reg_253 | 30| 0| 30| 0| |tmp_1_reg_325 | 32| 0| 32| 0| |tmp_4_cast_reg_274 | 30| 0| 31| 1| |tmp_4_reg_263 | 30| 0| 30| 0| |tmp_5_cast_reg_279 | 30| 0| 31| 1| |tmp_reg_258 | 30| 0| 30| 0| |exitcond_reg_284 | 64| 32| 1| 0| +-----------------------------+----+----+-----+-----------+ |Total | 399| 32| 338| 2| +-----------------------------+----+----+-----+-----------+ ================================================================ == Interface ================================================================ * Summary: +------------------------+-----+-----+------------+--------------+--------------+ | RTL Ports | Dir | Bits| Protocol | Source Object| C Type | +------------------------+-----+-----+------------+--------------+--------------+ |s_axi_AXILiteS_AWVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_AWREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_AWADDR | in | 6| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WDATA | in | 32| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WSTRB | in | 4| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARADDR | in | 6| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RVALID | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RREADY | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RDATA | out | 32| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RRESP | out | 2| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BVALID | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BREADY | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BRESP | out | 2| s_axi | AXILiteS | scalar | |ap_clk | in | 1| ap_ctrl_hs | vector_mult | return value | |ap_rst_n | in | 1| ap_ctrl_hs | vector_mult | return value | |interrupt | out | 1| ap_ctrl_hs | vector_mult | return value | |m_axi_gmem_AWVALID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_AWREADY | in | 1| m_axi | gmem | pointer | |m_axi_gmem_AWADDR | out | 32| m_axi | gmem | pointer | |m_axi_gmem_AWID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_AWLEN | out | 8| m_axi | gmem | pointer | |m_axi_gmem_AWSIZE | out | 3| m_axi | gmem | pointer | |m_axi_gmem_AWBURST | out | 2| m_axi | gmem | pointer | |m_axi_gmem_AWLOCK | out | 2| m_axi | gmem | pointer | |m_axi_gmem_AWCACHE | out | 4| m_axi | gmem | pointer | |m_axi_gmem_AWPROT | out | 3| m_axi | gmem | pointer | |m_axi_gmem_AWQOS | out | 4| m_axi | gmem | pointer | |m_axi_gmem_AWREGION | out | 4| m_axi | gmem | pointer | |m_axi_gmem_AWUSER | out | 1| m_axi | gmem | pointer | |m_axi_gmem_WVALID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_WREADY | in | 1| m_axi | gmem | pointer | |m_axi_gmem_WDATA | out | 32| m_axi | gmem | pointer | |m_axi_gmem_WSTRB | out | 4| m_axi | gmem | pointer | |m_axi_gmem_WLAST | out | 1| m_axi | gmem | pointer | |m_axi_gmem_WID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_WUSER | out | 1| m_axi | gmem | pointer | |m_axi_gmem_ARVALID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_ARREADY | in | 1| m_axi | gmem | pointer | |m_axi_gmem_ARADDR | out | 32| m_axi | gmem | pointer | |m_axi_gmem_ARID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_ARLEN | out | 8| m_axi | gmem | pointer | |m_axi_gmem_ARSIZE | out | 3| m_axi | gmem | pointer | |m_axi_gmem_ARBURST | out | 2| m_axi | gmem | pointer | |m_axi_gmem_ARLOCK | out | 2| m_axi | gmem | pointer | |m_axi_gmem_ARCACHE | out | 4| m_axi | gmem | pointer | |m_axi_gmem_ARPROT | out | 3| m_axi | gmem | pointer | |m_axi_gmem_ARQOS | out | 4| m_axi | gmem | pointer | |m_axi_gmem_ARREGION | out | 4| m_axi | gmem | pointer | |m_axi_gmem_ARUSER | out | 1| m_axi | gmem | pointer | |m_axi_gmem_RVALID | in | 1| m_axi | gmem | pointer | |m_axi_gmem_RREADY | out | 1| m_axi | gmem | pointer | |m_axi_gmem_RDATA | in | 32| m_axi | gmem | pointer | |m_axi_gmem_RLAST | in | 1| m_axi | gmem | pointer | |m_axi_gmem_RID | in | 1| m_axi | gmem | pointer | |m_axi_gmem_RUSER | in | 1| m_axi | gmem | pointer | |m_axi_gmem_RRESP | in | 2| m_axi | gmem | pointer | |m_axi_gmem_BVALID | in | 1| m_axi | gmem | pointer | |m_axi_gmem_BREADY | out | 1| m_axi | gmem | pointer | |m_axi_gmem_BRESP | in | 2| m_axi | gmem | pointer | |m_axi_gmem_BID | in | 1| m_axi | gmem | pointer | |m_axi_gmem_BUSER | in | 1| m_axi | gmem | pointer | +------------------------+-----+-----+------------+--------------+--------------+