================================================================
== Vivado HLS Report for 'vector_mult'
================================================================
* Date:           Mon Mar 19 11:20:05 2018

* Version:        2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017)
* Project:        vector_mult
* Solution:       solution1
* Product family: zynq
* Target device:  xc7z020clg484-1


================================================================
== Performance Estimates
================================================================
+ Timing (ns): 
    * Summary: 
    +--------+-------+----------+------------+
    |  Clock | Target| Estimated| Uncertainty|
    +--------+-------+----------+------------+
    |ap_clk  |  10.00|      8.75|        1.25|
    +--------+-------+----------+------------+

+ Latency (clock cycles): 
    * Summary: 
    +-----+-----+-----+-----+---------+
    |  Latency  |  Interval | Pipeline|
    | min | max | min | max |   Type  |
    +-----+-----+-----+-----+---------+
    |   32|   32|   32|   32|   none  |
    +-----+-----+-----+-----+---------+

    + Detail: 
        * Instance: 
        N/A

        * Loop: 
        +--------------------+-----+-----+----------+-----------+-----------+------+----------+
        |                    |  Latency  | Iteration|  Initiation Interval  | Trip |          |
        |      Loop Name     | min | max |  Latency |  achieved |   target  | Count| Pipelined|
        +--------------------+-----+-----+----------+-----------+-----------+------+----------+
        |- vector_mult_loop  |   25|   25|        12|          2|          1|     8|    yes   |
        +--------------------+-----+-----+----------+-----------+-----------+------+----------+

============================================================
+ Verbose Summary: Synthesis Manager
============================================================
InlineROM: 1
ExposeGlobal: 0
============================================================
+ Verbose Summary: CDFG Model
============================================================
IsTopModel: 1
ResetActiveHigh: 1
IsCombinational: 0
IsDatapathOnly: 0
HasWiredReturn: 1
HasMFsm: 0
HasVarLatency: 1
IsPipeline: 0
IsRtlPipelined: 0
IsInstanceOverlapped: 0
IsDontTouch: 0
HasImplIP: 0
IsGatedGlobalClock: 0

+ Individual pipeline summary: 
  * Pipeline-0: initiation interval (II) = 2, depth = 12


============================================================
+ Verbose Summary: Schedule
============================================================
* Number of FSM states : 19
* Pipeline : 1
  Pipeline-0 : II = 2, D = 12, States = { 3 4 5 6 7 8 9 10 11 12 13 14 }
* Dataflow Pipeline: 0

* FSM state transitions: 
1 --> 
	2  / true
2 --> 
	3  / true
3 --> 
	15  / (exitcond)
	4  / (!exitcond)
4 --> 
	5  / true
5 --> 
	6  / true
6 --> 
	7  / true
7 --> 
	8  / true
8 --> 
	9  / true
9 --> 
	10  / true
10 --> 
	11  / true
11 --> 
	12  / true
12 --> 
	13  / true
13 --> 
	14  / true
14 --> 
	3  / true
15 --> 
	16  / true
16 --> 
	17  / true
17 --> 
	18  / true
18 --> 
	19  / true
19 --> 

* FSM state operations: 

 <State 1> : 1.00ns
ST_1 : Operation 20 [1/1] (1.00ns)   --->   "%result_read = call i32 @_ssdm_op_Read.s_axilite.i32(i32 %result)"   --->   Core 10 's_axilite' <Latency = 0> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write'>
ST_1 : Operation 21 [1/1] (1.00ns)   --->   "%B_read = call i32 @_ssdm_op_Read.s_axilite.i32(i32 %B)"   --->   Core 10 's_axilite' <Latency = 0> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write'>
ST_1 : Operation 22 [1/1] (1.00ns)   --->   "%A_read = call i32 @_ssdm_op_Read.s_axilite.i32(i32 %A)"   --->   Core 10 's_axilite' <Latency = 0> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write'>
ST_1 : Operation 23 [1/1] (0.00ns)   --->   "%result5 = call i30 @_ssdm_op_PartSelect.i30.i32.i32.i32(i32 %result_read, i32 2, i32 31)"
ST_1 : Operation 24 [1/1] (0.00ns)   --->   "%tmp = call i30 @_ssdm_op_PartSelect.i30.i32.i32.i32(i32 %B_read, i32 2, i32 31)"
ST_1 : Operation 25 [1/1] (0.00ns)   --->   "%tmp_4 = call i30 @_ssdm_op_PartSelect.i30.i32.i32.i32(i32 %A_read, i32 2, i32 31)"

 <State 2> : 8.75ns
ST_2 : Operation 26 [1/1] (0.00ns)   --->   "%tmp_3 = zext i30 %result5 to i64"
ST_2 : Operation 27 [1/1] (0.00ns)   --->   "%gmem_addr = getelementptr i32* %gmem, i64 %tmp_3"
ST_2 : Operation 28 [1/1] (0.00ns)   --->   "%tmp_4_cast = zext i30 %tmp to i31"
ST_2 : Operation 29 [1/1] (0.00ns)   --->   "%tmp_5_cast = zext i30 %tmp_4 to i31"
ST_2 : Operation 30 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecBitsMap(i32* %gmem), !map !11"
ST_2 : Operation 31 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecTopModule([12 x i8]* @vector_mult_str) nounwind"
ST_2 : Operation 32 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(i32 0, [10 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1, [1 x i8]* @p_str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1) nounwind" [vector_mult/vector_mult.cpp:5]
ST_2 : Operation 33 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(i32 %result, [10 x i8]* @mode5, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @bundle6, [6 x i8]* @p_str3, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)"
ST_2 : Operation 34 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(i32 %B, [10 x i8]* @mode3, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @bundle4, [6 x i8]* @p_str3, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)"
ST_2 : Operation 35 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(i32* %gmem, [6 x i8]* @p_str2, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @p_str1, [6 x i8]* @p_str3, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)"
ST_2 : Operation 36 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(i32 %A, [10 x i8]* @mode, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @bundle, [6 x i8]* @p_str3, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)"
ST_2 : Operation 37 [1/1] (8.75ns)   --->   "%gmem_addr_wr_req = call i1 @_ssdm_op_WriteReq.m_axi.i32P(i32* %gmem_addr, i32 8)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_2 : Operation 38 [1/1] (1.76ns)   --->   "br label %1" [vector_mult/vector_mult.cpp:8]

 <State 3> : 2.49ns
ST_3 : Operation 39 [1/1] (0.00ns)   --->   "%i = phi i4 [ 0, %0 ], [ %i_1, %2 ]"
ST_3 : Operation 40 [1/1] (1.30ns)   --->   "%exitcond = icmp eq i4 %i, -8" [vector_mult/vector_mult.cpp:8]   --->   Core 25 'Cmp' <Latency = 0> <II = 1> <Delay = 1.30> <FuncUnit> <Opcode : 'icmp'> <InPorts = 2> <OutPorts = 1>
ST_3 : Operation 41 [1/1] (1.73ns)   --->   "%i_1 = add i4 %i, 1" [vector_mult/vector_mult.cpp:8]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.49> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_3 : Operation 42 [1/1] (0.00ns)   --->   "br i1 %exitcond, label %3, label %2" [vector_mult/vector_mult.cpp:8]
ST_3 : Operation 43 [1/1] (0.00ns)   --->   "%tmp_cast = zext i4 %i to i31" [vector_mult/vector_mult.cpp:8]
ST_3 : Operation 44 [1/1] (2.49ns)   --->   "%A2_sum = add i31 %tmp_cast, %tmp_5_cast" [vector_mult/vector_mult.cpp:8]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.49> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_3 : Operation 45 [1/1] (2.49ns)   --->   "%B4_sum = add i31 %tmp_cast, %tmp_4_cast" [vector_mult/vector_mult.cpp:8]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.49> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>

 <State 4> : 8.75ns
ST_4 : Operation 46 [1/1] (0.00ns)   --->   "%A2_sum_cast = zext i31 %A2_sum to i64" [vector_mult/vector_mult.cpp:8]
ST_4 : Operation 47 [1/1] (0.00ns)   --->   "%gmem_addr_1 = getelementptr i32* %gmem, i64 %A2_sum_cast" [vector_mult/vector_mult.cpp:8]
ST_4 : Operation 48 [7/7] (8.75ns)   --->   "%gmem_load_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 1)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 5> : 8.75ns
ST_5 : Operation 49 [6/7] (8.75ns)   --->   "%gmem_load_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 1)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_5 : Operation 50 [1/1] (0.00ns)   --->   "%B4_sum_cast = zext i31 %B4_sum to i64" [vector_mult/vector_mult.cpp:8]
ST_5 : Operation 51 [1/1] (0.00ns)   --->   "%gmem_addr_2 = getelementptr i32* %gmem, i64 %B4_sum_cast" [vector_mult/vector_mult.cpp:8]
ST_5 : Operation 52 [7/7] (8.75ns)   --->   "%gmem_load_1_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 1)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 6> : 8.75ns
ST_6 : Operation 53 [5/7] (8.75ns)   --->   "%gmem_load_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 1)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_6 : Operation 54 [6/7] (8.75ns)   --->   "%gmem_load_1_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 1)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 7> : 8.75ns
ST_7 : Operation 55 [4/7] (8.75ns)   --->   "%gmem_load_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 1)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_7 : Operation 56 [5/7] (8.75ns)   --->   "%gmem_load_1_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 1)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 8> : 8.75ns
ST_8 : Operation 57 [3/7] (8.75ns)   --->   "%gmem_load_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 1)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_8 : Operation 58 [4/7] (8.75ns)   --->   "%gmem_load_1_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 1)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 9> : 8.75ns
ST_9 : Operation 59 [2/7] (8.75ns)   --->   "%gmem_load_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 1)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_9 : Operation 60 [3/7] (8.75ns)   --->   "%gmem_load_1_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 1)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 10> : 8.75ns
ST_10 : Operation 61 [1/7] (8.75ns)   --->   "%gmem_load_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 1)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_10 : Operation 62 [2/7] (8.75ns)   --->   "%gmem_load_1_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 1)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 11> : 8.75ns
ST_11 : Operation 63 [1/1] (8.75ns)   --->   "%gmem_addr_1_read = call i32 @_ssdm_op_Read.m_axi.i32P(i32* %gmem_addr_1)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_11 : Operation 64 [1/7] (8.75ns)   --->   "%gmem_load_1_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 1)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 12> : 8.75ns
ST_12 : Operation 65 [1/1] (8.75ns)   --->   "%gmem_addr_2_read = call i32 @_ssdm_op_Read.m_axi.i32P(i32* %gmem_addr_2)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 13> : 8.51ns
ST_13 : Operation 66 [1/1] (8.51ns)   --->   "%tmp_1 = mul nsw i32 %gmem_addr_2_read, %gmem_addr_1_read" [vector_mult/vector_mult.cpp:9]   --->   Core 16 'Mul' <Latency = 0> <II = 1> <Delay = 8.51> <FuncUnit> <Opcode : 'mul'> <InPorts = 2> <OutPorts = 1>

 <State 14> : 8.75ns
ST_14 : Operation 67 [1/1] (0.00ns)   --->   "%empty = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 8, i64 8, i64 8) nounwind"
ST_14 : Operation 68 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecLoopName([17 x i8]* @p_str4) nounwind" [vector_mult/vector_mult.cpp:9]
ST_14 : Operation 69 [1/1] (0.00ns)   --->   "%tmp_2 = call i32 (...)* @_ssdm_op_SpecRegionBegin([17 x i8]* @p_str4) nounwind" [vector_mult/vector_mult.cpp:9]
ST_14 : Operation 70 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind" [vector_mult/vector_mult.cpp:10]
ST_14 : Operation 71 [1/1] (8.75ns)   --->   "call void @_ssdm_op_Write.m_axi.i32P(i32* %gmem_addr, i32 %tmp_1, i4 -1)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_14 : Operation 72 [1/1] (0.00ns)   --->   "%empty_4 = call i32 (...)* @_ssdm_op_SpecRegionEnd([17 x i8]* @p_str4, i32 %tmp_2) nounwind" [vector_mult/vector_mult.cpp:9]
ST_14 : Operation 73 [1/1] (0.00ns)   --->   "br label %1" [vector_mult/vector_mult.cpp:8]

 <State 15> : 8.75ns
ST_15 : Operation 74 [5/5] (8.75ns)   --->   "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %gmem_addr)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 16> : 8.75ns
ST_16 : Operation 75 [4/5] (8.75ns)   --->   "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %gmem_addr)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 17> : 8.75ns
ST_17 : Operation 76 [3/5] (8.75ns)   --->   "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %gmem_addr)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 18> : 8.75ns
ST_18 : Operation 77 [2/5] (8.75ns)   --->   "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %gmem_addr)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 19> : 8.75ns
ST_19 : Operation 78 [1/5] (8.75ns)   --->   "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %gmem_addr)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_19 : Operation 79 [1/1] (0.00ns)   --->   "ret void" [vector_mult/vector_mult.cpp:12]


============================================================
+ Verbose Summary: Timing violations
============================================================
Target clock period: 10ns, clock uncertainty: 1.25ns.

 <State 1>: 1ns
The critical path consists of the following:
	s_axi read on port 'result' [5]  (1 ns)

 <State 2>: 8.75ns
The critical path consists of the following:
	'getelementptr' operation ('gmem_addr') [10]  (0 ns)
	bus request on port 'gmem' (vector_mult/vector_mult.cpp:9) [22]  (8.75 ns)

 <State 3>: 2.49ns
The critical path consists of the following:
	'phi' operation ('i') with incoming values : ('i', vector_mult/vector_mult.cpp:8) [25]  (0 ns)
	'add' operation ('A2_sum', vector_mult/vector_mult.cpp:8) [35]  (2.49 ns)

 <State 4>: 8.75ns
The critical path consists of the following:
	'getelementptr' operation ('gmem_addr_1', vector_mult/vector_mult.cpp:8) [37]  (0 ns)
	bus request on port 'gmem' (vector_mult/vector_mult.cpp:9) [38]  (8.75 ns)

 <State 5>: 8.75ns
The critical path consists of the following:
	bus request on port 'gmem' (vector_mult/vector_mult.cpp:9) [38]  (8.75 ns)

 <State 6>: 8.75ns
The critical path consists of the following:
	bus request on port 'gmem' (vector_mult/vector_mult.cpp:9) [38]  (8.75 ns)

 <State 7>: 8.75ns
The critical path consists of the following:
	bus request on port 'gmem' (vector_mult/vector_mult.cpp:9) [38]  (8.75 ns)

 <State 8>: 8.75ns
The critical path consists of the following:
	bus request on port 'gmem' (vector_mult/vector_mult.cpp:9) [38]  (8.75 ns)

 <State 9>: 8.75ns
The critical path consists of the following:
	bus request on port 'gmem' (vector_mult/vector_mult.cpp:9) [38]  (8.75 ns)

 <State 10>: 8.75ns
The critical path consists of the following:
	bus request on port 'gmem' (vector_mult/vector_mult.cpp:9) [38]  (8.75 ns)

 <State 11>: 8.75ns
The critical path consists of the following:
	bus read on port 'gmem' (vector_mult/vector_mult.cpp:9) [39]  (8.75 ns)

 <State 12>: 8.75ns
The critical path consists of the following:
	bus read on port 'gmem' (vector_mult/vector_mult.cpp:9) [44]  (8.75 ns)

 <State 13>: 8.51ns
The critical path consists of the following:
	'mul' operation ('tmp_1', vector_mult/vector_mult.cpp:9) [45]  (8.51 ns)

 <State 14>: 8.75ns
The critical path consists of the following:
	bus write on port 'gmem' (vector_mult/vector_mult.cpp:9) [46]  (8.75 ns)

 <State 15>: 8.75ns
The critical path consists of the following:
	bus access on port 'gmem' (vector_mult/vector_mult.cpp:9) [50]  (8.75 ns)

 <State 16>: 8.75ns
The critical path consists of the following:
	bus access on port 'gmem' (vector_mult/vector_mult.cpp:9) [50]  (8.75 ns)

 <State 17>: 8.75ns
The critical path consists of the following:
	bus access on port 'gmem' (vector_mult/vector_mult.cpp:9) [50]  (8.75 ns)

 <State 18>: 8.75ns
The critical path consists of the following:
	bus access on port 'gmem' (vector_mult/vector_mult.cpp:9) [50]  (8.75 ns)

 <State 19>: 8.75ns
The critical path consists of the following:
	bus access on port 'gmem' (vector_mult/vector_mult.cpp:9) [50]  (8.75 ns)


============================================================
+ Verbose Summary: Binding
============================================================
N/A
* FSMD analyzer results:
  - Output states:
 - Input state : 
  - Chain level:
	State 1
	State 2
	State 3
	State 4
	State 5
	State 6
	State 7
	State 8
	State 9
	State 10
	State 11
	State 12
	State 13
	State 14
	State 15
	State 16
	State 17
	State 18
	State 19


============================================================
+ Verbose Summary: Datapath Resource usage 
============================================================
N/A