================================================================ == Vivado HLS Report for 'vector_mult' ================================================================ * Date: Mon Mar 19 11:20:05 2018 * Version: 2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017) * Project: vector_mult * Solution: solution1 * Product family: zynq * Target device: xc7z020clg484-1 ================================================================ == Performance Estimates ================================================================ + Timing (ns): * Summary: +--------+-------+----------+------------+ | Clock | Target| Estimated| Uncertainty| +--------+-------+----------+------------+ |ap_clk | 10.00| 8.75| 1.25| +--------+-------+----------+------------+ + Latency (clock cycles): * Summary: +-----+-----+-----+-----+---------+ | Latency | Interval | Pipeline| | min | max | min | max | Type | +-----+-----+-----+-----+---------+ | 32| 32| 32| 32| none | +-----+-----+-----+-----+---------+ + Detail: * Instance: N/A * Loop: +--------------------+-----+-----+----------+-----------+-----------+------+----------+ | | Latency | Iteration| Initiation Interval | Trip | | | Loop Name | min | max | Latency | achieved | target | Count| Pipelined| +--------------------+-----+-----+----------+-----------+-----------+------+----------+ |- vector_mult_loop | 25| 25| 12| 2| 1| 8| yes | +--------------------+-----+-----+----------+-----------+-----------+------+----------+ ================================================================ == Utilization Estimates ================================================================ * Summary: +-----------------+---------+-------+--------+-------+ | Name | BRAM_18K| DSP48E| FF | LUT | +-----------------+---------+-------+--------+-------+ |DSP | -| -| -| -| |Expression | -| 3| 0| 224| |FIFO | -| -| -| -| |Instance | 2| -| 662| 812| |Memory | -| -| -| -| |Multiplexer | -| -| -| 170| |Register | 0| -| 399| 32| +-----------------+---------+-------+--------+-------+ |Total | 2| 3| 1061| 1238| +-----------------+---------+-------+--------+-------+ |Available | 280| 220| 106400| 53200| +-----------------+---------+-------+--------+-------+ |Utilization (%) | ~0 | 1| ~0 | 2| +-----------------+---------+-------+--------+-------+ + Detail: * Instance: +------------------------------+----------------------------+---------+-------+-----+-----+ | Instance | Module | BRAM_18K| DSP48E| FF | LUT | +------------------------------+----------------------------+---------+-------+-----+-----+ |vector_mult_AXILiteS_s_axi_U |vector_mult_AXILiteS_s_axi | 0| 0| 150| 232| |vector_mult_gmem_m_axi_U |vector_mult_gmem_m_axi | 2| 0| 512| 580| +------------------------------+----------------------------+---------+-------+-----+-----+ |Total | | 2| 0| 662| 812| +------------------------------+----------------------------+---------+-------+-----+-----+ * DSP48: N/A * Memory: N/A * FIFO: N/A * Expression: +-----------------------------------+----------+-------+---+----+------------+------------+ | Variable Name | Operation| DSP48E| FF| LUT| Bitwidth P0| Bitwidth P1| +-----------------------------------+----------+-------+---+----+------------+------------+ |tmp_1_fu_249_p2 | * | 3| 0| 20| 32| 32| |A2_sum_fu_219_p2 | + | 0| 0| 38| 31| 31| |B4_sum_fu_224_p2 | + | 0| 0| 38| 31| 31| |i_1_fu_209_p2 | + | 0| 0| 13| 4| 1| |ap_block_pp0_stage0_01001 | and | 0| 0| 8| 1| 1| |ap_block_pp0_stage1_01001 | and | 0| 0| 8| 1| 1| |ap_block_state11_pp0_stage0_iter4 | and | 0| 0| 8| 1| 1| |ap_block_state12_pp0_stage1_iter4 | and | 0| 0| 8| 1| 1| |ap_block_state14_io | and | 0| 0| 8| 1| 1| |ap_block_state4_io | and | 0| 0| 8| 1| 1| |ap_condition_404 | and | 0| 0| 8| 1| 1| |ap_condition_415 | and | 0| 0| 8| 1| 1| |ap_condition_552 | and | 0| 0| 8| 1| 1| |exitcond_fu_203_p2 | icmp | 0| 0| 11| 4| 5| |ap_block_pp0_stage0_11001 | or | 0| 0| 8| 1| 1| |ap_block_pp0_stage1_11001 | or | 0| 0| 8| 1| 1| |ap_enable_pp0 | xor | 0| 0| 8| 1| 2| |ap_enable_reg_pp0_iter1 | xor | 0| 0| 8| 2| 1| +-----------------------------------+----------+-------+---+----+------------+------------+ |Total | | 3| 0| 224| 116| 114| +-----------------------------------+----------+-------+---+----+------------+------------+ * Multiplexer: +-----------------------------+----+-----------+-----+-----------+ | Name | LUT| Input Size| Bits| Total Bits| +-----------------------------+----+-----------+-----+-----------+ |ap_NS_fsm | 47| 10| 1| 10| |ap_enable_reg_pp0_iter1 | 9| 2| 1| 2| |ap_enable_reg_pp0_iter5 | 9| 2| 1| 2| |ap_phi_mux_i_phi_fu_150_p4 | 9| 2| 4| 8| |ap_sig_ioackin_gmem_ARREADY | 9| 2| 1| 2| |ap_sig_ioackin_gmem_AWREADY | 9| 2| 1| 2| |ap_sig_ioackin_gmem_WREADY | 9| 2| 1| 2| |gmem_ARADDR | 15| 3| 32| 96| |gmem_blk_n_AR | 9| 2| 1| 2| |gmem_blk_n_AW | 9| 2| 1| 2| |gmem_blk_n_B | 9| 2| 1| 2| |gmem_blk_n_R | 9| 2| 1| 2| |gmem_blk_n_W | 9| 2| 1| 2| |i_reg_146 | 9| 2| 4| 8| +-----------------------------+----+-----------+-----+-----------+ |Total | 170| 37| 51| 142| +-----------------------------+----+-----------+-----+-----------+ * Register: +-----------------------------+----+----+-----+-----------+ | Name | FF | LUT| Bits| Const Bits| +-----------------------------+----+----+-----+-----------+ |A2_sum_reg_293 | 31| 0| 31| 0| |B4_sum_reg_298 | 31| 0| 31| 0| |ap_CS_fsm | 9| 0| 9| 0| |ap_enable_reg_pp0_iter0 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter1 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter2 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter3 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter4 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter5 | 1| 0| 1| 0| |ap_reg_ioackin_gmem_ARREADY | 1| 0| 1| 0| |ap_reg_ioackin_gmem_AWREADY | 1| 0| 1| 0| |ap_reg_ioackin_gmem_WREADY | 1| 0| 1| 0| |exitcond_reg_284 | 1| 0| 1| 0| |gmem_addr_1_read_reg_315 | 32| 0| 32| 0| |gmem_addr_2_read_reg_320 | 32| 0| 32| 0| |i_1_reg_288 | 4| 0| 4| 0| |i_reg_146 | 4| 0| 4| 0| |result5_reg_253 | 30| 0| 30| 0| |tmp_1_reg_325 | 32| 0| 32| 0| |tmp_4_cast_reg_274 | 30| 0| 31| 1| |tmp_4_reg_263 | 30| 0| 30| 0| |tmp_5_cast_reg_279 | 30| 0| 31| 1| |tmp_reg_258 | 30| 0| 30| 0| |exitcond_reg_284 | 64| 32| 1| 0| +-----------------------------+----+----+-----+-----------+ |Total | 399| 32| 338| 2| +-----------------------------+----+----+-----+-----------+ ================================================================ == Interface ================================================================ * Summary: +------------------------+-----+-----+------------+--------------+--------------+ | RTL Ports | Dir | Bits| Protocol | Source Object| C Type | +------------------------+-----+-----+------------+--------------+--------------+ |s_axi_AXILiteS_AWVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_AWREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_AWADDR | in | 6| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WDATA | in | 32| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WSTRB | in | 4| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARADDR | in | 6| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RVALID | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RREADY | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RDATA | out | 32| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RRESP | out | 2| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BVALID | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BREADY | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BRESP | out | 2| s_axi | AXILiteS | scalar | |ap_clk | in | 1| ap_ctrl_hs | vector_mult | return value | |ap_rst_n | in | 1| ap_ctrl_hs | vector_mult | return value | |interrupt | out | 1| ap_ctrl_hs | vector_mult | return value | |m_axi_gmem_AWVALID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_AWREADY | in | 1| m_axi | gmem | pointer | |m_axi_gmem_AWADDR | out | 32| m_axi | gmem | pointer | |m_axi_gmem_AWID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_AWLEN | out | 8| m_axi | gmem | pointer | |m_axi_gmem_AWSIZE | out | 3| m_axi | gmem | pointer | |m_axi_gmem_AWBURST | out | 2| m_axi | gmem | pointer | |m_axi_gmem_AWLOCK | out | 2| m_axi | gmem | pointer | |m_axi_gmem_AWCACHE | out | 4| m_axi | gmem | pointer | |m_axi_gmem_AWPROT | out | 3| m_axi | gmem | pointer | |m_axi_gmem_AWQOS | out | 4| m_axi | gmem | pointer | |m_axi_gmem_AWREGION | out | 4| m_axi | gmem | pointer | |m_axi_gmem_AWUSER | out | 1| m_axi | gmem | pointer | |m_axi_gmem_WVALID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_WREADY | in | 1| m_axi | gmem | pointer | |m_axi_gmem_WDATA | out | 32| m_axi | gmem | pointer | |m_axi_gmem_WSTRB | out | 4| m_axi | gmem | pointer | |m_axi_gmem_WLAST | out | 1| m_axi | gmem | pointer | |m_axi_gmem_WID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_WUSER | out | 1| m_axi | gmem | pointer | |m_axi_gmem_ARVALID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_ARREADY | in | 1| m_axi | gmem | pointer | |m_axi_gmem_ARADDR | out | 32| m_axi | gmem | pointer | |m_axi_gmem_ARID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_ARLEN | out | 8| m_axi | gmem | pointer | |m_axi_gmem_ARSIZE | out | 3| m_axi | gmem | pointer | |m_axi_gmem_ARBURST | out | 2| m_axi | gmem | pointer | |m_axi_gmem_ARLOCK | out | 2| m_axi | gmem | pointer | |m_axi_gmem_ARCACHE | out | 4| m_axi | gmem | pointer | |m_axi_gmem_ARPROT | out | 3| m_axi | gmem | pointer | |m_axi_gmem_ARQOS | out | 4| m_axi | gmem | pointer | |m_axi_gmem_ARREGION | out | 4| m_axi | gmem | pointer | |m_axi_gmem_ARUSER | out | 1| m_axi | gmem | pointer | |m_axi_gmem_RVALID | in | 1| m_axi | gmem | pointer | |m_axi_gmem_RREADY | out | 1| m_axi | gmem | pointer | |m_axi_gmem_RDATA | in | 32| m_axi | gmem | pointer | |m_axi_gmem_RLAST | in | 1| m_axi | gmem | pointer | |m_axi_gmem_RID | in | 1| m_axi | gmem | pointer | |m_axi_gmem_RUSER | in | 1| m_axi | gmem | pointer | |m_axi_gmem_RRESP | in | 2| m_axi | gmem | pointer | |m_axi_gmem_BVALID | in | 1| m_axi | gmem | pointer | |m_axi_gmem_BREADY | out | 1| m_axi | gmem | pointer | |m_axi_gmem_BRESP | in | 2| m_axi | gmem | pointer | |m_axi_gmem_BID | in | 1| m_axi | gmem | pointer | |m_axi_gmem_BUSER | in | 1| m_axi | gmem | pointer | +------------------------+-----+-----+------------+--------------+--------------+ ============================================================ + Verbose Summary: Synthesis Manager ============================================================ InlineROM: 1 ExposeGlobal: 0 ============================================================ + Verbose Summary: CDFG Model ============================================================ IsTopModel: 1 ResetActiveHigh: 1 IsCombinational: 2 IsDatapathOnly: 2 HasWiredReturn: 1 HasMFsm: 0 HasVarLatency: 1 IsPipeline: 0 IsRtlPipelined: 0 IsInstanceOverlapped: 0 IsDontTouch: 0 HasImplIP: 0 IsGatedGlobalClock: 0 + Individual pipeline summary: * Pipeline-0: initiation interval (II) = 2, depth = 12 ============================================================ + Verbose Summary: Schedule ============================================================ * Number of FSM states : 19 * Pipeline : 1 Pipeline-0 : II = 2, D = 12, States = { 3 4 5 6 7 8 9 10 11 12 13 14 } * Dataflow Pipeline: 0 * FSM state transitions: 1 --> 2 / true 2 --> 3 / true 3 --> 15 / (exitcond) 4 / (!exitcond) 4 --> 5 / true 5 --> 6 / true 6 --> 7 / true 7 --> 8 / true 8 --> 9 / true 9 --> 10 / true 10 --> 11 / true 11 --> 12 / true 12 --> 13 / true 13 --> 14 / true 14 --> 3 / true 15 --> 16 / true 16 --> 17 / true 17 --> 18 / true 18 --> 19 / true 19 --> * FSM state operations: : 1.00ns ST_1 : Operation 20 [1/1] (1.00ns) ---> "%result_read = call i32 @_ssdm_op_Read.s_axilite.i32(i32 %result)" ---> Core 10 's_axilite' ST_1 : Operation 21 [1/1] (1.00ns) ---> "%B_read = call i32 @_ssdm_op_Read.s_axilite.i32(i32 %B)" ---> Core 10 's_axilite' ST_1 : Operation 22 [1/1] (1.00ns) ---> "%A_read = call i32 @_ssdm_op_Read.s_axilite.i32(i32 %A)" ---> Core 10 's_axilite' ST_1 : Operation 23 [1/1] (0.00ns) ---> "%result5 = call i30 @_ssdm_op_PartSelect.i30.i32.i32.i32(i32 %result_read, i32 2, i32 31)" ST_1 : Operation 24 [1/1] (0.00ns) ---> "%tmp = call i30 @_ssdm_op_PartSelect.i30.i32.i32.i32(i32 %B_read, i32 2, i32 31)" ST_1 : Operation 25 [1/1] (0.00ns) ---> "%tmp_4 = call i30 @_ssdm_op_PartSelect.i30.i32.i32.i32(i32 %A_read, i32 2, i32 31)" : 8.75ns ST_2 : Operation 26 [1/1] (0.00ns) ---> "%tmp_3 = zext i30 %result5 to i64" ST_2 : Operation 27 [1/1] (0.00ns) ---> "%gmem_addr = getelementptr i32* %gmem, i64 %tmp_3" ST_2 : Operation 28 [1/1] (0.00ns) ---> "%tmp_4_cast = zext i30 %tmp to i31" ST_2 : Operation 29 [1/1] (0.00ns) ---> "%tmp_5_cast = zext i30 %tmp_4 to i31" ST_2 : Operation 30 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecBitsMap(i32* %gmem), !map !11" ST_2 : Operation 31 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecTopModule([12 x i8]* @vector_mult_str) nounwind" ST_2 : Operation 32 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32 0, [10 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1, [1 x i8]* @p_str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1) nounwind" [vector_mult/vector_mult.cpp:5] ST_2 : Operation 33 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32 %result, [10 x i8]* @mode5, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @bundle6, [6 x i8]* @p_str3, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)" ST_2 : Operation 34 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32 %B, [10 x i8]* @mode3, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @bundle4, [6 x i8]* @p_str3, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)" ST_2 : Operation 35 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32* %gmem, [6 x i8]* @p_str2, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @p_str1, [6 x i8]* @p_str3, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)" ST_2 : Operation 36 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32 %A, [10 x i8]* @mode, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @bundle, [6 x i8]* @p_str3, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)" ST_2 : Operation 37 [1/1] (8.75ns) ---> "%gmem_addr_wr_req = call i1 @_ssdm_op_WriteReq.m_axi.i32P(i32* %gmem_addr, i32 8)" [vector_mult/vector_mult.cpp:9] ---> Core 9 'm_axi' ST_2 : Operation 38 [1/1] (1.76ns) ---> "br label %1" [vector_mult/vector_mult.cpp:8] : 2.49ns ST_3 : Operation 39 [1/1] (0.00ns) ---> "%i = phi i4 [ 0, %0 ], [ %i_1, %2 ]" ST_3 : Operation 40 [1/1] (1.30ns) ---> "%exitcond = icmp eq i4 %i, -8" [vector_mult/vector_mult.cpp:8] ---> Core 25 'Cmp' ST_3 : Operation 41 [1/1] (1.73ns) ---> "%i_1 = add i4 %i, 1" [vector_mult/vector_mult.cpp:8] ---> Core 14 'AddSub' ST_3 : Operation 42 [1/1] (0.00ns) ---> "br i1 %exitcond, label %3, label %2" [vector_mult/vector_mult.cpp:8] ST_3 : Operation 43 [1/1] (0.00ns) ---> "%tmp_cast = zext i4 %i to i31" [vector_mult/vector_mult.cpp:8] ST_3 : Operation 44 [1/1] (2.49ns) ---> "%A2_sum = add i31 %tmp_cast, %tmp_5_cast" [vector_mult/vector_mult.cpp:8] ---> Core 14 'AddSub' ST_3 : Operation 45 [1/1] (2.49ns) ---> "%B4_sum = add i31 %tmp_cast, %tmp_4_cast" [vector_mult/vector_mult.cpp:8] ---> Core 14 'AddSub' : 8.75ns ST_4 : Operation 46 [1/1] (0.00ns) ---> "%A2_sum_cast = zext i31 %A2_sum to i64" [vector_mult/vector_mult.cpp:8] ST_4 : Operation 47 [1/1] (0.00ns) ---> "%gmem_addr_1 = getelementptr i32* %gmem, i64 %A2_sum_cast" [vector_mult/vector_mult.cpp:8] ST_4 : Operation 48 [7/7] (8.75ns) ---> "%gmem_load_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 1)" [vector_mult/vector_mult.cpp:9] ---> Core 9 'm_axi' : 8.75ns ST_5 : Operation 49 [6/7] (8.75ns) ---> "%gmem_load_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 1)" [vector_mult/vector_mult.cpp:9] ---> Core 9 'm_axi' ST_5 : Operation 50 [1/1] (0.00ns) ---> "%B4_sum_cast = zext i31 %B4_sum to i64" [vector_mult/vector_mult.cpp:8] ST_5 : Operation 51 [1/1] (0.00ns) ---> "%gmem_addr_2 = getelementptr i32* %gmem, i64 %B4_sum_cast" [vector_mult/vector_mult.cpp:8] ST_5 : Operation 52 [7/7] (8.75ns) ---> "%gmem_load_1_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 1)" [vector_mult/vector_mult.cpp:9] ---> Core 9 'm_axi' : 8.75ns ST_6 : Operation 53 [5/7] (8.75ns) ---> "%gmem_load_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 1)" [vector_mult/vector_mult.cpp:9] ---> Core 9 'm_axi' ST_6 : Operation 54 [6/7] (8.75ns) ---> "%gmem_load_1_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 1)" [vector_mult/vector_mult.cpp:9] ---> Core 9 'm_axi' : 8.75ns ST_7 : Operation 55 [4/7] (8.75ns) ---> "%gmem_load_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 1)" [vector_mult/vector_mult.cpp:9] ---> Core 9 'm_axi' ST_7 : Operation 56 [5/7] (8.75ns) ---> "%gmem_load_1_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 1)" [vector_mult/vector_mult.cpp:9] ---> Core 9 'm_axi' : 8.75ns ST_8 : Operation 57 [3/7] (8.75ns) ---> "%gmem_load_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 1)" [vector_mult/vector_mult.cpp:9] ---> Core 9 'm_axi' ST_8 : Operation 58 [4/7] (8.75ns) ---> "%gmem_load_1_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 1)" [vector_mult/vector_mult.cpp:9] ---> Core 9 'm_axi' : 8.75ns ST_9 : Operation 59 [2/7] (8.75ns) ---> "%gmem_load_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 1)" [vector_mult/vector_mult.cpp:9] ---> Core 9 'm_axi' ST_9 : Operation 60 [3/7] (8.75ns) ---> "%gmem_load_1_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 1)" [vector_mult/vector_mult.cpp:9] ---> Core 9 'm_axi' : 8.75ns ST_10 : Operation 61 [1/7] (8.75ns) ---> "%gmem_load_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 1)" [vector_mult/vector_mult.cpp:9] ---> Core 9 'm_axi' ST_10 : Operation 62 [2/7] (8.75ns) ---> "%gmem_load_1_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 1)" [vector_mult/vector_mult.cpp:9] ---> Core 9 'm_axi' : 8.75ns ST_11 : Operation 63 [1/1] (8.75ns) ---> "%gmem_addr_1_read = call i32 @_ssdm_op_Read.m_axi.i32P(i32* %gmem_addr_1)" [vector_mult/vector_mult.cpp:9] ---> Core 9 'm_axi' ST_11 : Operation 64 [1/7] (8.75ns) ---> "%gmem_load_1_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 1)" [vector_mult/vector_mult.cpp:9] ---> Core 9 'm_axi' : 8.75ns ST_12 : Operation 65 [1/1] (8.75ns) ---> "%gmem_addr_2_read = call i32 @_ssdm_op_Read.m_axi.i32P(i32* %gmem_addr_2)" [vector_mult/vector_mult.cpp:9] ---> Core 9 'm_axi' : 8.51ns ST_13 : Operation 66 [1/1] (8.51ns) ---> "%tmp_1 = mul nsw i32 %gmem_addr_2_read, %gmem_addr_1_read" [vector_mult/vector_mult.cpp:9] ---> Core 16 'Mul' : 8.75ns ST_14 : Operation 67 [1/1] (0.00ns) ---> "%empty = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 8, i64 8, i64 8) nounwind" ST_14 : Operation 68 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecLoopName([17 x i8]* @p_str4) nounwind" [vector_mult/vector_mult.cpp:9] ST_14 : Operation 69 [1/1] (0.00ns) ---> "%tmp_2 = call i32 (...)* @_ssdm_op_SpecRegionBegin([17 x i8]* @p_str4) nounwind" [vector_mult/vector_mult.cpp:9] ST_14 : Operation 70 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind" [vector_mult/vector_mult.cpp:10] ST_14 : Operation 71 [1/1] (8.75ns) ---> "call void @_ssdm_op_Write.m_axi.i32P(i32* %gmem_addr, i32 %tmp_1, i4 -1)" [vector_mult/vector_mult.cpp:9] ---> Core 9 'm_axi' ST_14 : Operation 72 [1/1] (0.00ns) ---> "%empty_4 = call i32 (...)* @_ssdm_op_SpecRegionEnd([17 x i8]* @p_str4, i32 %tmp_2) nounwind" [vector_mult/vector_mult.cpp:9] ST_14 : Operation 73 [1/1] (0.00ns) ---> "br label %1" [vector_mult/vector_mult.cpp:8] : 8.75ns ST_15 : Operation 74 [5/5] (8.75ns) ---> "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %gmem_addr)" [vector_mult/vector_mult.cpp:9] ---> Core 9 'm_axi' : 8.75ns ST_16 : Operation 75 [4/5] (8.75ns) ---> "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %gmem_addr)" [vector_mult/vector_mult.cpp:9] ---> Core 9 'm_axi' : 8.75ns ST_17 : Operation 76 [3/5] (8.75ns) ---> "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %gmem_addr)" [vector_mult/vector_mult.cpp:9] ---> Core 9 'm_axi' : 8.75ns ST_18 : Operation 77 [2/5] (8.75ns) ---> "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %gmem_addr)" [vector_mult/vector_mult.cpp:9] ---> Core 9 'm_axi' : 8.75ns ST_19 : Operation 78 [1/5] (8.75ns) ---> "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %gmem_addr)" [vector_mult/vector_mult.cpp:9] ---> Core 9 'm_axi' ST_19 : Operation 79 [1/1] (0.00ns) ---> "ret void" [vector_mult/vector_mult.cpp:12] ============================================================ + Verbose Summary: Binding ============================================================ STG Binding: ---------------- STG Properties BEGIN ---------------- - Is combinational: 0 - Is one-state seq: 0 - Is datapath-only: 0 - Is pipelined: 0 - Is top level: 1 Port [ Return ] is wired: 1; IO mode=ap_ctrl_hs:ce=0 Port [ gmem]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=2; type=4; pingpong=0; private_global=0; IO mode=m_axi:ce=0 Port [ A]: wired=1; compound=0; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=0; pingpong=0; private_global=0; IO mode=ap_none:ce=0 Port [ B]: wired=1; compound=0; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=0; pingpong=0; private_global=0; IO mode=ap_none:ce=0 Port [ result]: wired=1; compound=0; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=0; pingpong=0; private_global=0; IO mode=ap_none:ce=0 ---------------- STG Properties END ------------------ ---------------- Datapath Model BEGIN ---------------- result_read (read ) [ 00000000000000000000] B_read (read ) [ 00000000000000000000] A_read (read ) [ 00000000000000000000] result5 (partselect ) [ 00100000000000000000] tmp (partselect ) [ 00100000000000000000] tmp_4 (partselect ) [ 00100000000000000000] tmp_3 (zext ) [ 00000000000000000000] gmem_addr (getelementptr ) [ 00011111111111111111] tmp_4_cast (zext ) [ 00011111111111100000] tmp_5_cast (zext ) [ 00011111111111100000] StgValue_30 (specbitsmap ) [ 00000000000000000000] StgValue_31 (spectopmodule ) [ 00000000000000000000] StgValue_32 (specinterface ) [ 00000000000000000000] StgValue_33 (specinterface ) [ 00000000000000000000] StgValue_34 (specinterface ) [ 00000000000000000000] StgValue_35 (specinterface ) [ 00000000000000000000] StgValue_36 (specinterface ) [ 00000000000000000000] gmem_addr_wr_req (writereq ) [ 00000000000000000000] StgValue_38 (br ) [ 00111111111111100000] i (phi ) [ 00010000000000000000] exitcond (icmp ) [ 00011111111111100000] i_1 (add ) [ 00111111111111100000] StgValue_42 (br ) [ 00000000000000000000] tmp_cast (zext ) [ 00000000000000000000] A2_sum (add ) [ 00001000000000000000] B4_sum (add ) [ 00011100000000000000] A2_sum_cast (zext ) [ 00000000000000000000] gmem_addr_1 (getelementptr ) [ 00011111111100000000] B4_sum_cast (zext ) [ 00000000000000000000] gmem_addr_2 (getelementptr ) [ 00011011111110000000] gmem_load_req (readreq ) [ 00000000000000000000] gmem_addr_1_read (read ) [ 00011000000011000000] gmem_load_1_req (readreq ) [ 00000000000000000000] gmem_addr_2_read (read ) [ 00010000000001000000] tmp_1 (mul ) [ 00001000000000100000] empty (speclooptripcount) [ 00000000000000000000] StgValue_68 (specloopname ) [ 00000000000000000000] tmp_2 (specregionbegin ) [ 00000000000000000000] StgValue_70 (specpipeline ) [ 00000000000000000000] StgValue_71 (write ) [ 00000000000000000000] empty_4 (specregionend ) [ 00000000000000000000] StgValue_73 (br ) [ 00111111111111100000] gmem_addr_wr_resp (writeresp ) [ 00000000000000000000] StgValue_79 (ret ) [ 00000000000000000000] ---------------- Datapath Model END ------------------ * FSMD analyzer results: - Output states: Port: gmem | {2 14 15 16 17 18 19 } - Input state : Port: vector_mult : gmem | {4 5 6 7 8 9 10 11 12 } Port: vector_mult : A | {1 } Port: vector_mult : B | {1 } Port: vector_mult : result | {1 } - Chain level: State 1 State 2 gmem_addr : 1 gmem_addr_wr_req : 2 State 3 exitcond : 1 i_1 : 1 StgValue_42 : 2 tmp_cast : 1 A2_sum : 2 B4_sum : 2 State 4 gmem_addr_1 : 1 gmem_load_req : 2 State 5 gmem_addr_2 : 1 gmem_load_1_req : 2 State 6 State 7 State 8 State 9 State 10 State 11 State 12 State 13 State 14 empty_4 : 1 State 15 State 16 State 17 State 18 State 19 ============================================================ + Verbose Summary: Datapath Resource usage ============================================================ * Functional unit list: |----------|------------------------------|---------|---------|---------| | Operation| Functional Unit | DSP48E | FF | LUT | |----------|------------------------------|---------|---------|---------| | | i_1_fu_209 | 0 | 0 | 13 | | add | A2_sum_fu_219 | 0 | 0 | 37 | | | B4_sum_fu_224 | 0 | 0 | 37 | |----------|------------------------------|---------|---------|---------| | mul | tmp_1_fu_249 | 3 | 0 | 20 | |----------|------------------------------|---------|---------|---------| | icmp | exitcond_fu_203 | 0 | 0 | 9 | |----------|------------------------------|---------|---------|---------| | | result_read_read_fu_88 | 0 | 0 | 0 | | | B_read_read_fu_94 | 0 | 0 | 0 | | read | A_read_read_fu_100 | 0 | 0 | 0 | | | gmem_addr_1_read_read_fu_127 | 0 | 0 | 0 | | | gmem_addr_2_read_read_fu_132 | 0 | 0 | 0 | |----------|------------------------------|---------|---------|---------| | writeresp| grp_writeresp_fu_106 | 0 | 0 | 0 | |----------|------------------------------|---------|---------|---------| | readreq | grp_readreq_fu_113 | 0 | 0 | 0 | | | grp_readreq_fu_120 | 0 | 0 | 0 | |----------|------------------------------|---------|---------|---------| | write | StgValue_71_write_fu_137 | 0 | 0 | 0 | |----------|------------------------------|---------|---------|---------| | | result5_fu_157 | 0 | 0 | 0 | |partselect| tmp_fu_167 | 0 | 0 | 0 | | | tmp_4_fu_177 | 0 | 0 | 0 | |----------|------------------------------|---------|---------|---------| | | tmp_3_fu_187 | 0 | 0 | 0 | | | tmp_4_cast_fu_197 | 0 | 0 | 0 | | zext | tmp_5_cast_fu_200 | 0 | 0 | 0 | | | tmp_cast_fu_215 | 0 | 0 | 0 | | | A2_sum_cast_fu_229 | 0 | 0 | 0 | | | B4_sum_cast_fu_239 | 0 | 0 | 0 | |----------|------------------------------|---------|---------|---------| | Total | | 3 | 0 | 116 | |----------|------------------------------|---------|---------|---------| Memories: N/A * Register list: +------------------------+--------+ | | FF | +------------------------+--------+ | A2_sum_reg_293 | 31 | | B4_sum_reg_298 | 31 | | exitcond_reg_284 | 1 | |gmem_addr_1_read_reg_315| 32 | | gmem_addr_1_reg_303 | 32 | |gmem_addr_2_read_reg_320| 32 | | gmem_addr_2_reg_309 | 32 | | gmem_addr_reg_268 | 32 | | i_1_reg_288 | 4 | | i_reg_146 | 4 | | result5_reg_253 | 30 | | tmp_1_reg_325 | 32 | | tmp_4_cast_reg_274 | 31 | | tmp_4_reg_263 | 30 | | tmp_5_cast_reg_279 | 31 | | tmp_reg_258 | 30 | +------------------------+--------+ | Total | 415 | +------------------------+--------+ * Multiplexer (MUX) list: |----------------------|------|------|------|--------||---------||---------| | Comp | Pin | Size | BW | S x BW || Delay || LUT | |----------------------|------|------|------|--------||---------||---------| | grp_writeresp_fu_106 | p0 | 2 | 1 | 2 | | grp_writeresp_fu_106 | p1 | 2 | 32 | 64 || 9 | | grp_readreq_fu_113 | p1 | 2 | 32 | 64 || 9 | | grp_readreq_fu_120 | p1 | 2 | 32 | 64 || 9 | |----------------------|------|------|------|--------||---------||---------| | Total | | | | 194 || 7.076 || 27 | |----------------------|------|------|------|--------||---------||---------| * Summary: +-----------+--------+--------+--------+--------+ | | DSP48E | Delay | FF | LUT | +-----------+--------+--------+--------+--------+ | Function | 3 | - | 0 | 116 | | Memory | - | - | - | - | |Multiplexer| - | 7 | - | 27 | | Register | - | - | 415 | - | +-----------+--------+--------+--------+--------+ | Total | 3 | 7 | 415 | 143 | +-----------+--------+--------+--------+--------+