================================================================
== Vivado HLS Report for 'vector_mult'
================================================================
* Date:           Mon Mar 19 11:20:05 2018

* Version:        2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017)
* Project:        vector_mult
* Solution:       solution1
* Product family: zynq
* Target device:  xc7z020clg484-1


================================================================
== Performance Estimates
================================================================
+ Timing (ns): 
    * Summary: 
    +--------+-------+----------+------------+
    |  Clock | Target| Estimated| Uncertainty|
    +--------+-------+----------+------------+
    |ap_clk  |  10.00|      8.75|        1.25|
    +--------+-------+----------+------------+

+ Latency (clock cycles): 
    * Summary: 
    +-----+-----+-----+-----+---------+
    |  Latency  |  Interval | Pipeline|
    | min | max | min | max |   Type  |
    +-----+-----+-----+-----+---------+
    |   32|   32|   32|   32|   none  |
    +-----+-----+-----+-----+---------+

    + Detail: 
        * Instance: 
        N/A

        * Loop: 
        +--------------------+-----+-----+----------+-----------+-----------+------+----------+
        |                    |  Latency  | Iteration|  Initiation Interval  | Trip |          |
        |      Loop Name     | min | max |  Latency |  achieved |   target  | Count| Pipelined|
        +--------------------+-----+-----+----------+-----------+-----------+------+----------+
        |- vector_mult_loop  |   25|   25|        12|          2|          1|     8|    yes   |
        +--------------------+-----+-----+----------+-----------+-----------+------+----------+

============================================================
+ Verbose Summary: Synthesis Manager
============================================================
InlineROM: 1
ExposeGlobal: 0
============================================================
+ Verbose Summary: CDFG Model
============================================================
IsTopModel: 1
ResetActiveHigh: 1
IsCombinational: 0
IsDatapathOnly: 0
HasWiredReturn: 1
HasMFsm: 0
HasVarLatency: 1
IsPipeline: 0
IsRtlPipelined: 0
IsInstanceOverlapped: 0
IsDontTouch: 0
HasImplIP: 0
IsGatedGlobalClock: 0

+ Individual pipeline summary: 
  * Pipeline-0: initiation interval (II) = 2, depth = 12


============================================================
+ Verbose Summary: Schedule
============================================================
* Number of FSM states : 19
* Pipeline : 1
  Pipeline-0 : II = 2, D = 12, States = { 3 4 5 6 7 8 9 10 11 12 13 14 }
* Dataflow Pipeline: 0

* FSM state transitions: 
1 --> 
	2  / true
2 --> 
	3  / true
3 --> 
	15  / (exitcond)
	4  / (!exitcond)
4 --> 
	5  / true
5 --> 
	6  / true
6 --> 
	7  / true
7 --> 
	8  / true
8 --> 
	9  / true
9 --> 
	10  / true
10 --> 
	11  / true
11 --> 
	12  / true
12 --> 
	13  / true
13 --> 
	14  / true
14 --> 
	3  / true
15 --> 
	16  / true
16 --> 
	17  / true
17 --> 
	18  / true
18 --> 
	19  / true
19 --> 

* FSM state operations: 

 <State 1> : 1.00ns
ST_1 : Operation 20 [1/1] (1.00ns)   --->   "%result_read = call i32 @_ssdm_op_Read.s_axilite.i32(i32 %result)"   --->   Core 10 's_axilite' <Latency = 0> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write'>
ST_1 : Operation 21 [1/1] (1.00ns)   --->   "%B_read = call i32 @_ssdm_op_Read.s_axilite.i32(i32 %B)"   --->   Core 10 's_axilite' <Latency = 0> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write'>
ST_1 : Operation 22 [1/1] (1.00ns)   --->   "%A_read = call i32 @_ssdm_op_Read.s_axilite.i32(i32 %A)"   --->   Core 10 's_axilite' <Latency = 0> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write'>
ST_1 : Operation 23 [1/1] (0.00ns)   --->   "%result5 = call i30 @_ssdm_op_PartSelect.i30.i32.i32.i32(i32 %result_read, i32 2, i32 31)"
ST_1 : Operation 24 [1/1] (0.00ns)   --->   "%tmp = call i30 @_ssdm_op_PartSelect.i30.i32.i32.i32(i32 %B_read, i32 2, i32 31)"
ST_1 : Operation 25 [1/1] (0.00ns)   --->   "%tmp_4 = call i30 @_ssdm_op_PartSelect.i30.i32.i32.i32(i32 %A_read, i32 2, i32 31)"

 <State 2> : 8.75ns
ST_2 : Operation 26 [1/1] (0.00ns)   --->   "%tmp_3 = zext i30 %result5 to i64"
ST_2 : Operation 27 [1/1] (0.00ns)   --->   "%gmem_addr = getelementptr i32* %gmem, i64 %tmp_3"
ST_2 : Operation 28 [1/1] (0.00ns)   --->   "%tmp_4_cast = zext i30 %tmp to i31"
ST_2 : Operation 29 [1/1] (0.00ns)   --->   "%tmp_5_cast = zext i30 %tmp_4 to i31"
ST_2 : Operation 30 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecBitsMap(i32* %gmem), !map !11"
ST_2 : Operation 31 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecTopModule([12 x i8]* @vector_mult_str) nounwind"
ST_2 : Operation 32 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(i32 0, [10 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1, [1 x i8]* @p_str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1) nounwind" [vector_mult/vector_mult.cpp:5]
ST_2 : Operation 33 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(i32 %result, [10 x i8]* @mode5, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @bundle6, [6 x i8]* @p_str3, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)"
ST_2 : Operation 34 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(i32 %B, [10 x i8]* @mode3, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @bundle4, [6 x i8]* @p_str3, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)"
ST_2 : Operation 35 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(i32* %gmem, [6 x i8]* @p_str2, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @p_str1, [6 x i8]* @p_str3, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)"
ST_2 : Operation 36 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(i32 %A, [10 x i8]* @mode, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @bundle, [6 x i8]* @p_str3, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)"
ST_2 : Operation 37 [1/1] (8.75ns)   --->   "%gmem_addr_wr_req = call i1 @_ssdm_op_WriteReq.m_axi.i32P(i32* %gmem_addr, i32 8)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_2 : Operation 38 [1/1] (1.76ns)   --->   "br label %1" [vector_mult/vector_mult.cpp:8]

 <State 3> : 2.49ns
ST_3 : Operation 39 [1/1] (0.00ns)   --->   "%i = phi i4 [ 0, %0 ], [ %i_1, %2 ]"
ST_3 : Operation 40 [1/1] (1.30ns)   --->   "%exitcond = icmp eq i4 %i, -8" [vector_mult/vector_mult.cpp:8]   --->   Core 25 'Cmp' <Latency = 0> <II = 1> <Delay = 1.30> <FuncUnit> <Opcode : 'icmp'> <InPorts = 2> <OutPorts = 1>
ST_3 : Operation 41 [1/1] (1.73ns)   --->   "%i_1 = add i4 %i, 1" [vector_mult/vector_mult.cpp:8]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.49> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_3 : Operation 42 [1/1] (0.00ns)   --->   "br i1 %exitcond, label %3, label %2" [vector_mult/vector_mult.cpp:8]
ST_3 : Operation 43 [1/1] (0.00ns)   --->   "%tmp_cast = zext i4 %i to i31" [vector_mult/vector_mult.cpp:8]
ST_3 : Operation 44 [1/1] (2.49ns)   --->   "%A2_sum = add i31 %tmp_cast, %tmp_5_cast" [vector_mult/vector_mult.cpp:8]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.49> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_3 : Operation 45 [1/1] (2.49ns)   --->   "%B4_sum = add i31 %tmp_cast, %tmp_4_cast" [vector_mult/vector_mult.cpp:8]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.49> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>

 <State 4> : 8.75ns
ST_4 : Operation 46 [1/1] (0.00ns)   --->   "%A2_sum_cast = zext i31 %A2_sum to i64" [vector_mult/vector_mult.cpp:8]
ST_4 : Operation 47 [1/1] (0.00ns)   --->   "%gmem_addr_1 = getelementptr i32* %gmem, i64 %A2_sum_cast" [vector_mult/vector_mult.cpp:8]
ST_4 : Operation 48 [7/7] (8.75ns)   --->   "%gmem_load_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 1)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 5> : 8.75ns
ST_5 : Operation 49 [6/7] (8.75ns)   --->   "%gmem_load_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 1)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_5 : Operation 50 [1/1] (0.00ns)   --->   "%B4_sum_cast = zext i31 %B4_sum to i64" [vector_mult/vector_mult.cpp:8]
ST_5 : Operation 51 [1/1] (0.00ns)   --->   "%gmem_addr_2 = getelementptr i32* %gmem, i64 %B4_sum_cast" [vector_mult/vector_mult.cpp:8]
ST_5 : Operation 52 [7/7] (8.75ns)   --->   "%gmem_load_1_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 1)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 6> : 8.75ns
ST_6 : Operation 53 [5/7] (8.75ns)   --->   "%gmem_load_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 1)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_6 : Operation 54 [6/7] (8.75ns)   --->   "%gmem_load_1_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 1)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 7> : 8.75ns
ST_7 : Operation 55 [4/7] (8.75ns)   --->   "%gmem_load_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 1)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_7 : Operation 56 [5/7] (8.75ns)   --->   "%gmem_load_1_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 1)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 8> : 8.75ns
ST_8 : Operation 57 [3/7] (8.75ns)   --->   "%gmem_load_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 1)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_8 : Operation 58 [4/7] (8.75ns)   --->   "%gmem_load_1_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 1)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 9> : 8.75ns
ST_9 : Operation 59 [2/7] (8.75ns)   --->   "%gmem_load_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 1)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_9 : Operation 60 [3/7] (8.75ns)   --->   "%gmem_load_1_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 1)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 10> : 8.75ns
ST_10 : Operation 61 [1/7] (8.75ns)   --->   "%gmem_load_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_1, i32 1)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_10 : Operation 62 [2/7] (8.75ns)   --->   "%gmem_load_1_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 1)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 11> : 8.75ns
ST_11 : Operation 63 [1/1] (8.75ns)   --->   "%gmem_addr_1_read = call i32 @_ssdm_op_Read.m_axi.i32P(i32* %gmem_addr_1)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_11 : Operation 64 [1/7] (8.75ns)   --->   "%gmem_load_1_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %gmem_addr_2, i32 1)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 12> : 8.75ns
ST_12 : Operation 65 [1/1] (8.75ns)   --->   "%gmem_addr_2_read = call i32 @_ssdm_op_Read.m_axi.i32P(i32* %gmem_addr_2)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 13> : 8.51ns
ST_13 : Operation 66 [1/1] (8.51ns)   --->   "%tmp_1 = mul nsw i32 %gmem_addr_2_read, %gmem_addr_1_read" [vector_mult/vector_mult.cpp:9]   --->   Core 16 'Mul' <Latency = 0> <II = 1> <Delay = 8.51> <FuncUnit> <Opcode : 'mul'> <InPorts = 2> <OutPorts = 1>

 <State 14> : 8.75ns
ST_14 : Operation 67 [1/1] (0.00ns)   --->   "%empty = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 8, i64 8, i64 8) nounwind"
ST_14 : Operation 68 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecLoopName([17 x i8]* @p_str4) nounwind" [vector_mult/vector_mult.cpp:9]
ST_14 : Operation 69 [1/1] (0.00ns)   --->   "%tmp_2 = call i32 (...)* @_ssdm_op_SpecRegionBegin([17 x i8]* @p_str4) nounwind" [vector_mult/vector_mult.cpp:9]
ST_14 : Operation 70 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind" [vector_mult/vector_mult.cpp:10]
ST_14 : Operation 71 [1/1] (8.75ns)   --->   "call void @_ssdm_op_Write.m_axi.i32P(i32* %gmem_addr, i32 %tmp_1, i4 -1)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_14 : Operation 72 [1/1] (0.00ns)   --->   "%empty_4 = call i32 (...)* @_ssdm_op_SpecRegionEnd([17 x i8]* @p_str4, i32 %tmp_2) nounwind" [vector_mult/vector_mult.cpp:9]
ST_14 : Operation 73 [1/1] (0.00ns)   --->   "br label %1" [vector_mult/vector_mult.cpp:8]

 <State 15> : 8.75ns
ST_15 : Operation 74 [5/5] (8.75ns)   --->   "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %gmem_addr)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 16> : 8.75ns
ST_16 : Operation 75 [4/5] (8.75ns)   --->   "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %gmem_addr)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 17> : 8.75ns
ST_17 : Operation 76 [3/5] (8.75ns)   --->   "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %gmem_addr)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 18> : 8.75ns
ST_18 : Operation 77 [2/5] (8.75ns)   --->   "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %gmem_addr)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 19> : 8.75ns
ST_19 : Operation 78 [1/5] (8.75ns)   --->   "%gmem_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %gmem_addr)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_19 : Operation 79 [1/1] (0.00ns)   --->   "ret void" [vector_mult/vector_mult.cpp:12]


============================================================
+ Verbose Summary: Binding
============================================================
STG Binding: 
---------------- STG Properties BEGIN ----------------
- Is combinational: 0
- Is one-state seq: 0
- Is datapath-only: 0
- Is pipelined: 0
- Is top level: 1
Port [ Return ] is wired: 1; IO mode=ap_ctrl_hs:ce=0
Port [ gmem]:  wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=2; type=4; pingpong=0; private_global=0; IO mode=m_axi:ce=0
Port [ A]:  wired=1; compound=0; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=0; pingpong=0; private_global=0; IO mode=ap_none:ce=0
Port [ B]:  wired=1; compound=0; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=0; pingpong=0; private_global=0; IO mode=ap_none:ce=0
Port [ result]:  wired=1; compound=0; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=0; pingpong=0; private_global=0; IO mode=ap_none:ce=0
---------------- STG Properties END ------------------

---------------- Datapath Model BEGIN ----------------

<LifeTime>
<method=bitvector/>
result_read       (read             ) [ 00000000000000000000]
B_read            (read             ) [ 00000000000000000000]
A_read            (read             ) [ 00000000000000000000]
result5           (partselect       ) [ 00100000000000000000]
tmp               (partselect       ) [ 00100000000000000000]
tmp_4             (partselect       ) [ 00100000000000000000]
tmp_3             (zext             ) [ 00000000000000000000]
gmem_addr         (getelementptr    ) [ 00011111111111111111]
tmp_4_cast        (zext             ) [ 00011111111111100000]
tmp_5_cast        (zext             ) [ 00011111111111100000]
StgValue_30       (specbitsmap      ) [ 00000000000000000000]
StgValue_31       (spectopmodule    ) [ 00000000000000000000]
StgValue_32       (specinterface    ) [ 00000000000000000000]
StgValue_33       (specinterface    ) [ 00000000000000000000]
StgValue_34       (specinterface    ) [ 00000000000000000000]
StgValue_35       (specinterface    ) [ 00000000000000000000]
StgValue_36       (specinterface    ) [ 00000000000000000000]
gmem_addr_wr_req  (writereq         ) [ 00000000000000000000]
StgValue_38       (br               ) [ 00111111111111100000]
i                 (phi              ) [ 00010000000000000000]
exitcond          (icmp             ) [ 00011111111111100000]
i_1               (add              ) [ 00111111111111100000]
StgValue_42       (br               ) [ 00000000000000000000]
tmp_cast          (zext             ) [ 00000000000000000000]
A2_sum            (add              ) [ 00001000000000000000]
B4_sum            (add              ) [ 00011100000000000000]
A2_sum_cast       (zext             ) [ 00000000000000000000]
gmem_addr_1       (getelementptr    ) [ 00011111111100000000]
B4_sum_cast       (zext             ) [ 00000000000000000000]
gmem_addr_2       (getelementptr    ) [ 00011011111110000000]
gmem_load_req     (readreq          ) [ 00000000000000000000]
gmem_addr_1_read  (read             ) [ 00011000000011000000]
gmem_load_1_req   (readreq          ) [ 00000000000000000000]
gmem_addr_2_read  (read             ) [ 00010000000001000000]
tmp_1             (mul              ) [ 00001000000000100000]
empty             (speclooptripcount) [ 00000000000000000000]
StgValue_68       (specloopname     ) [ 00000000000000000000]
tmp_2             (specregionbegin  ) [ 00000000000000000000]
StgValue_70       (specpipeline     ) [ 00000000000000000000]
StgValue_71       (write            ) [ 00000000000000000000]
empty_4           (specregionend    ) [ 00000000000000000000]
StgValue_73       (br               ) [ 00111111111111100000]
gmem_addr_wr_resp (writeresp        ) [ 00000000000000000000]
StgValue_79       (ret              ) [ 00000000000000000000]
</LifeTime>

<model>

<comp_list>
<comp id="0" class="1000" name="gmem">
<pin_list>
<pin id="1" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="gmem"/></StgValue>
</bind>
</comp>

<comp id="2" class="1000" name="A">
<pin_list>
<pin id="3" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="A"/></StgValue>
</bind>
</comp>

<comp id="4" class="1000" name="B">
<pin_list>
<pin id="5" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="B"/></StgValue>
</bind>
</comp>

<comp id="6" class="1000" name="result">
<pin_list>
<pin id="7" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="result"/></StgValue>
</bind>
</comp>

<comp id="8" class="1001" name="const_8">
<pin_list>
<pin id="9" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_Read.s_axilite.i32"/></StgValue>
</bind>
</comp>

<comp id="10" class="1001" name="const_10">
<pin_list>
<pin id="11" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_PartSelect.i30.i32.i32.i32"/></StgValue>
</bind>
</comp>

<comp id="12" class="1001" name="const_12">
<pin_list>
<pin id="13" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="14" class="1001" name="const_14">
<pin_list>
<pin id="15" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="16" class="1001" name="const_16">
<pin_list>
<pin id="17" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecBitsMap"/></StgValue>
</bind>
</comp>

<comp id="18" class="1001" name="const_18">
<pin_list>
<pin id="19" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecTopModule"/></StgValue>
</bind>
</comp>

<comp id="20" class="1001" name="const_20">
<pin_list>
<pin id="21" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="vector_mult_str"/></StgValue>
</bind>
</comp>

<comp id="22" class="1001" name="const_22">
<pin_list>
<pin id="23" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecInterface"/></StgValue>
</bind>
</comp>

<comp id="24" class="1001" name="const_24">
<pin_list>
<pin id="25" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="26" class="1001" name="const_26">
<pin_list>
<pin id="27" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str"/></StgValue>
</bind>
</comp>

<comp id="28" class="1001" name="const_28">
<pin_list>
<pin id="29" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str1"/></StgValue>
</bind>
</comp>

<comp id="30" class="1001" name="const_30">
<pin_list>
<pin id="31" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="mode5"/></StgValue>
</bind>
</comp>

<comp id="32" class="1001" name="const_32">
<pin_list>
<pin id="33" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="34" class="1001" name="const_34">
<pin_list>
<pin id="35" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="bundle6"/></StgValue>
</bind>
</comp>

<comp id="36" class="1001" name="const_36">
<pin_list>
<pin id="37" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str3"/></StgValue>
</bind>
</comp>

<comp id="38" class="1001" name="const_38">
<pin_list>
<pin id="39" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="40" class="1001" name="const_40">
<pin_list>
<pin id="41" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="mode3"/></StgValue>
</bind>
</comp>

<comp id="42" class="1001" name="const_42">
<pin_list>
<pin id="43" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="bundle4"/></StgValue>
</bind>
</comp>

<comp id="44" class="1001" name="const_44">
<pin_list>
<pin id="45" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str2"/></StgValue>
</bind>
</comp>

<comp id="46" class="1001" name="const_46">
<pin_list>
<pin id="47" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="mode"/></StgValue>
</bind>
</comp>

<comp id="48" class="1001" name="const_48">
<pin_list>
<pin id="49" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="bundle"/></StgValue>
</bind>
</comp>

<comp id="50" class="1001" name="const_50">
<pin_list>
<pin id="51" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_WriteReq.m_axi.i32P"/></StgValue>
</bind>
</comp>

<comp id="52" class="1001" name="const_52">
<pin_list>
<pin id="53" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="54" class="1001" name="const_54">
<pin_list>
<pin id="55" dir="1" index="0" bw="1" slack="1"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="56" class="1001" name="const_56">
<pin_list>
<pin id="57" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="58" class="1001" name="const_58">
<pin_list>
<pin id="59" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="60" class="1001" name="const_60">
<pin_list>
<pin id="61" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_ReadReq.m_axi.i32P"/></StgValue>
</bind>
</comp>

<comp id="62" class="1001" name="const_62">
<pin_list>
<pin id="63" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="64" class="1001" name="const_64">
<pin_list>
<pin id="65" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_Read.m_axi.i32P"/></StgValue>
</bind>
</comp>

<comp id="66" class="1001" name="const_66">
<pin_list>
<pin id="67" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecLoopTripCount"/></StgValue>
</bind>
</comp>

<comp id="68" class="1001" name="const_68">
<pin_list>
<pin id="69" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="70" class="1001" name="const_70">
<pin_list>
<pin id="71" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecLoopName"/></StgValue>
</bind>
</comp>

<comp id="72" class="1001" name="const_72">
<pin_list>
<pin id="73" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str4"/></StgValue>
</bind>
</comp>

<comp id="74" class="1001" name="const_74">
<pin_list>
<pin id="75" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecRegionBegin"/></StgValue>
</bind>
</comp>

<comp id="76" class="1001" name="const_76">
<pin_list>
<pin id="77" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecPipeline"/></StgValue>
</bind>
</comp>

<comp id="78" class="1001" name="const_78">
<pin_list>
<pin id="79" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="80" class="1001" name="const_80">
<pin_list>
<pin id="81" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_Write.m_axi.i32P"/></StgValue>
</bind>
</comp>

<comp id="82" class="1001" name="const_82">
<pin_list>
<pin id="83" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="84" class="1001" name="const_84">
<pin_list>
<pin id="85" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecRegionEnd"/></StgValue>
</bind>
</comp>

<comp id="86" class="1001" name="const_86">
<pin_list>
<pin id="87" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_WriteResp.m_axi.i32P"/></StgValue>
</bind>
</comp>

<comp id="88" class="1004" name="result_read_read_fu_88">
<pin_list>
<pin id="89" dir="0" index="0" bw="32" slack="0"/>
<pin id="90" dir="0" index="1" bw="32" slack="0"/>
<pin id="91" dir="1" index="2" bw="32" slack="0"/>
</pin_list>
<bind>
<opcode="read(1150) " fcode="read"/>
<opset="result_read/1 "/>
</bind>
</comp>

<comp id="94" class="1004" name="B_read_read_fu_94">
<pin_list>
<pin id="95" dir="0" index="0" bw="32" slack="0"/>
<pin id="96" dir="0" index="1" bw="32" slack="0"/>
<pin id="97" dir="1" index="2" bw="32" slack="0"/>
</pin_list>
<bind>
<opcode="read(1150) " fcode="read"/>
<opset="B_read/1 "/>
</bind>
</comp>

<comp id="100" class="1004" name="A_read_read_fu_100">
<pin_list>
<pin id="101" dir="0" index="0" bw="32" slack="0"/>
<pin id="102" dir="0" index="1" bw="32" slack="0"/>
<pin id="103" dir="1" index="2" bw="32" slack="0"/>
</pin_list>
<bind>
<opcode="read(1150) " fcode="read"/>
<opset="A_read/1 "/>
</bind>
</comp>

<comp id="106" class="1004" name="grp_writeresp_fu_106">
<pin_list>
<pin id="107" dir="0" index="0" bw="1" slack="0"/>
<pin id="108" dir="0" index="1" bw="32" slack="0"/>
<pin id="109" dir="0" index="2" bw="5" slack="0"/>
<pin id="110" dir="1" index="3" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<opcode="writereq(1155) writeresp(1158) " fcode="writeresp"/>
<opset="gmem_addr_wr_req/2 gmem_addr_wr_resp/15 "/>
</bind>
</comp>

<comp id="113" class="1004" name="grp_readreq_fu_113">
<pin_list>
<pin id="114" dir="0" index="0" bw="1" slack="0"/>
<pin id="115" dir="0" index="1" bw="32" slack="0"/>
<pin id="116" dir="0" index="2" bw="1" slack="0"/>
<pin id="117" dir="1" index="3" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<opcode="readreq(1154) " fcode="readreq"/>
<opset="gmem_load_req/4 "/>
</bind>
</comp>

<comp id="120" class="1004" name="grp_readreq_fu_120">
<pin_list>
<pin id="121" dir="0" index="0" bw="1" slack="0"/>
<pin id="122" dir="0" index="1" bw="32" slack="0"/>
<pin id="123" dir="0" index="2" bw="1" slack="0"/>
<pin id="124" dir="1" index="3" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<opcode="readreq(1154) " fcode="readreq"/>
<opset="gmem_load_1_req/5 "/>
</bind>
</comp>

<comp id="127" class="1004" name="gmem_addr_1_read_read_fu_127">
<pin_list>
<pin id="128" dir="0" index="0" bw="32" slack="0"/>
<pin id="129" dir="0" index="1" bw="32" slack="7"/>
<pin id="130" dir="1" index="2" bw="32" slack="2"/>
</pin_list>
<bind>
<opcode="read(1150) " fcode="read"/>
<opset="gmem_addr_1_read/11 "/>
</bind>
</comp>

<comp id="132" class="1004" name="gmem_addr_2_read_read_fu_132">
<pin_list>
<pin id="133" dir="0" index="0" bw="32" slack="0"/>
<pin id="134" dir="0" index="1" bw="32" slack="7"/>
<pin id="135" dir="1" index="2" bw="32" slack="1"/>
</pin_list>
<bind>
<opcode="read(1150) " fcode="read"/>
<opset="gmem_addr_2_read/12 "/>
</bind>
</comp>

<comp id="137" class="1004" name="StgValue_71_write_fu_137">
<pin_list>
<pin id="138" dir="0" index="0" bw="0" slack="0"/>
<pin id="139" dir="0" index="1" bw="32" slack="12"/>
<pin id="140" dir="0" index="2" bw="32" slack="1"/>
<pin id="141" dir="0" index="3" bw="1" slack="0"/>
<pin id="142" dir="1" index="4" bw="0" slack="2147483647"/>
</pin_list>
<bind>
<opcode="write(1151) " fcode="write"/>
<opset="StgValue_71/14 "/>
</bind>
</comp>

<comp id="146" class="1005" name="i_reg_146">
<pin_list>
<pin id="147" dir="0" index="0" bw="4" slack="1"/>
<pin id="148" dir="1" index="1" bw="4" slack="1"/>
</pin_list>
<bind>
<opset="i (phireg) "/>
</bind>
</comp>

<comp id="150" class="1004" name="i_phi_fu_150">
<pin_list>
<pin id="151" dir="0" index="0" bw="1" slack="1"/>
<pin id="152" dir="0" index="1" bw="0" slack="2147483647"/>
<pin id="153" dir="0" index="2" bw="4" slack="0"/>
<pin id="154" dir="0" index="3" bw="0" slack="2147483647"/>
<pin id="155" dir="1" index="4" bw="4" slack="0"/>
</pin_list>
<bind>
<opcode="phi(47) " fcode="phi"/>
<opset="i/3 "/>
</bind>
</comp>

<comp id="157" class="1004" name="result5_fu_157">
<pin_list>
<pin id="158" dir="0" index="0" bw="30" slack="0"/>
<pin id="159" dir="0" index="1" bw="32" slack="0"/>
<pin id="160" dir="0" index="2" bw="3" slack="0"/>
<pin id="161" dir="0" index="3" bw="6" slack="0"/>
<pin id="162" dir="1" index="4" bw="30" slack="1"/>
</pin_list>
<bind>
<opcode="partselect(1002) " fcode="partselect"/>
<opset="result5/1 "/>
</bind>
</comp>

<comp id="167" class="1004" name="tmp_fu_167">
<pin_list>
<pin id="168" dir="0" index="0" bw="30" slack="0"/>
<pin id="169" dir="0" index="1" bw="32" slack="0"/>
<pin id="170" dir="0" index="2" bw="3" slack="0"/>
<pin id="171" dir="0" index="3" bw="6" slack="0"/>
<pin id="172" dir="1" index="4" bw="30" slack="1"/>
</pin_list>
<bind>
<opcode="partselect(1002) " fcode="partselect"/>
<opset="tmp/1 "/>
</bind>
</comp>

<comp id="177" class="1004" name="tmp_4_fu_177">
<pin_list>
<pin id="178" dir="0" index="0" bw="30" slack="0"/>
<pin id="179" dir="0" index="1" bw="32" slack="0"/>
<pin id="180" dir="0" index="2" bw="3" slack="0"/>
<pin id="181" dir="0" index="3" bw="6" slack="0"/>
<pin id="182" dir="1" index="4" bw="30" slack="1"/>
</pin_list>
<bind>
<opcode="partselect(1002) " fcode="partselect"/>
<opset="tmp_4/1 "/>
</bind>
</comp>

<comp id="187" class="1004" name="tmp_3_fu_187">
<pin_list>
<pin id="188" dir="0" index="0" bw="30" slack="1"/>
<pin id="189" dir="1" index="1" bw="64" slack="0"/>
</pin_list>
<bind>
<opcode="zext(34) " fcode="zext"/>
<opset="tmp_3/2 "/>
</bind>
</comp>

<comp id="190" class="1004" name="gmem_addr_fu_190">
<pin_list>
<pin id="191" dir="0" index="0" bw="32" slack="0"/>
<pin id="192" dir="0" index="1" bw="30" slack="0"/>
<pin id="193" dir="1" index="2" bw="32" slack="0"/>
</pin_list>
<bind>
<opcode="getelementptr(29) " fcode="getelementptr"/>
<opset="gmem_addr/2 "/>
</bind>
</comp>

<comp id="197" class="1004" name="tmp_4_cast_fu_197">
<pin_list>
<pin id="198" dir="0" index="0" bw="30" slack="1"/>
<pin id="199" dir="1" index="1" bw="31" slack="1"/>
</pin_list>
<bind>
<opcode="zext(34) " fcode="zext"/>
<opset="tmp_4_cast/2 "/>
</bind>
</comp>

<comp id="200" class="1004" name="tmp_5_cast_fu_200">
<pin_list>
<pin id="201" dir="0" index="0" bw="30" slack="1"/>
<pin id="202" dir="1" index="1" bw="31" slack="1"/>
</pin_list>
<bind>
<opcode="zext(34) " fcode="zext"/>
<opset="tmp_5_cast/2 "/>
</bind>
</comp>

<comp id="203" class="1004" name="exitcond_fu_203">
<pin_list>
<pin id="204" dir="0" index="0" bw="4" slack="0"/>
<pin id="205" dir="0" index="1" bw="4" slack="0"/>
<pin id="206" dir="1" index="2" bw="1" slack="1"/>
</pin_list>
<bind>
<opcode="icmp(45) " fcode="icmp"/>
<opset="exitcond/3 "/>
</bind>
</comp>

<comp id="209" class="1004" name="i_1_fu_209">
<pin_list>
<pin id="210" dir="0" index="0" bw="4" slack="0"/>
<pin id="211" dir="0" index="1" bw="1" slack="0"/>
<pin id="212" dir="1" index="2" bw="4" slack="0"/>
</pin_list>
<bind>
<opcode="add(8) " fcode="add"/>
<opset="i_1/3 "/>
</bind>
</comp>

<comp id="215" class="1004" name="tmp_cast_fu_215">
<pin_list>
<pin id="216" dir="0" index="0" bw="4" slack="0"/>
<pin id="217" dir="1" index="1" bw="31" slack="0"/>
</pin_list>
<bind>
<opcode="zext(34) " fcode="zext"/>
<opset="tmp_cast/3 "/>
</bind>
</comp>

<comp id="219" class="1004" name="A2_sum_fu_219">
<pin_list>
<pin id="220" dir="0" index="0" bw="4" slack="0"/>
<pin id="221" dir="0" index="1" bw="30" slack="1"/>
<pin id="222" dir="1" index="2" bw="31" slack="1"/>
</pin_list>
<bind>
<opcode="add(8) " fcode="add"/>
<opset="A2_sum/3 "/>
</bind>
</comp>

<comp id="224" class="1004" name="B4_sum_fu_224">
<pin_list>
<pin id="225" dir="0" index="0" bw="4" slack="0"/>
<pin id="226" dir="0" index="1" bw="30" slack="1"/>
<pin id="227" dir="1" index="2" bw="31" slack="2"/>
</pin_list>
<bind>
<opcode="add(8) " fcode="add"/>
<opset="B4_sum/3 "/>
</bind>
</comp>

<comp id="229" class="1004" name="A2_sum_cast_fu_229">
<pin_list>
<pin id="230" dir="0" index="0" bw="31" slack="1"/>
<pin id="231" dir="1" index="1" bw="64" slack="0"/>
</pin_list>
<bind>
<opcode="zext(34) " fcode="zext"/>
<opset="A2_sum_cast/4 "/>
</bind>
</comp>

<comp id="232" class="1004" name="gmem_addr_1_fu_232">
<pin_list>
<pin id="233" dir="0" index="0" bw="32" slack="0"/>
<pin id="234" dir="0" index="1" bw="31" slack="0"/>
<pin id="235" dir="1" index="2" bw="32" slack="0"/>
</pin_list>
<bind>
<opcode="getelementptr(29) " fcode="getelementptr"/>
<opset="gmem_addr_1/4 "/>
</bind>
</comp>

<comp id="239" class="1004" name="B4_sum_cast_fu_239">
<pin_list>
<pin id="240" dir="0" index="0" bw="31" slack="2"/>
<pin id="241" dir="1" index="1" bw="64" slack="0"/>
</pin_list>
<bind>
<opcode="zext(34) " fcode="zext"/>
<opset="B4_sum_cast/5 "/>
</bind>
</comp>

<comp id="242" class="1004" name="gmem_addr_2_fu_242">
<pin_list>
<pin id="243" dir="0" index="0" bw="32" slack="0"/>
<pin id="244" dir="0" index="1" bw="31" slack="0"/>
<pin id="245" dir="1" index="2" bw="32" slack="0"/>
</pin_list>
<bind>
<opcode="getelementptr(29) " fcode="getelementptr"/>
<opset="gmem_addr_2/5 "/>
</bind>
</comp>

<comp id="249" class="1004" name="tmp_1_fu_249">
<pin_list>
<pin id="250" dir="0" index="0" bw="32" slack="1"/>
<pin id="251" dir="0" index="1" bw="32" slack="2"/>
<pin id="252" dir="1" index="2" bw="32" slack="1"/>
</pin_list>
<bind>
<opcode="mul(12) " fcode="mul"/>
<opset="tmp_1/13 "/>
</bind>
</comp>

<comp id="253" class="1005" name="result5_reg_253">
<pin_list>
<pin id="254" dir="0" index="0" bw="30" slack="1"/>
<pin id="255" dir="1" index="1" bw="30" slack="1"/>
</pin_list>
<bind>
<opset="result5 "/>
</bind>
</comp>

<comp id="258" class="1005" name="tmp_reg_258">
<pin_list>
<pin id="259" dir="0" index="0" bw="30" slack="1"/>
<pin id="260" dir="1" index="1" bw="30" slack="1"/>
</pin_list>
<bind>
<opset="tmp "/>
</bind>
</comp>

<comp id="263" class="1005" name="tmp_4_reg_263">
<pin_list>
<pin id="264" dir="0" index="0" bw="30" slack="1"/>
<pin id="265" dir="1" index="1" bw="30" slack="1"/>
</pin_list>
<bind>
<opset="tmp_4 "/>
</bind>
</comp>

<comp id="268" class="1005" name="gmem_addr_reg_268">
<pin_list>
<pin id="269" dir="0" index="0" bw="32" slack="2"/>
<pin id="270" dir="1" index="1" bw="32" slack="2"/>
</pin_list>
<bind>
<opset="gmem_addr "/>
</bind>
</comp>

<comp id="274" class="1005" name="tmp_4_cast_reg_274">
<pin_list>
<pin id="275" dir="0" index="0" bw="31" slack="1"/>
<pin id="276" dir="1" index="1" bw="31" slack="1"/>
</pin_list>
<bind>
<opset="tmp_4_cast "/>
</bind>
</comp>

<comp id="279" class="1005" name="tmp_5_cast_reg_279">
<pin_list>
<pin id="280" dir="0" index="0" bw="31" slack="1"/>
<pin id="281" dir="1" index="1" bw="31" slack="1"/>
</pin_list>
<bind>
<opset="tmp_5_cast "/>
</bind>
</comp>

<comp id="284" class="1005" name="exitcond_reg_284">
<pin_list>
<pin id="285" dir="0" index="0" bw="1" slack="1"/>
<pin id="286" dir="1" index="1" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<opset="exitcond "/>
</bind>
</comp>

<comp id="288" class="1005" name="i_1_reg_288">
<pin_list>
<pin id="289" dir="0" index="0" bw="4" slack="0"/>
<pin id="290" dir="1" index="1" bw="4" slack="0"/>
</pin_list>
<bind>
<opset="i_1 "/>
</bind>
</comp>

<comp id="293" class="1005" name="A2_sum_reg_293">
<pin_list>
<pin id="294" dir="0" index="0" bw="31" slack="1"/>
<pin id="295" dir="1" index="1" bw="31" slack="1"/>
</pin_list>
<bind>
<opset="A2_sum "/>
</bind>
</comp>

<comp id="298" class="1005" name="B4_sum_reg_298">
<pin_list>
<pin id="299" dir="0" index="0" bw="31" slack="2"/>
<pin id="300" dir="1" index="1" bw="31" slack="2"/>
</pin_list>
<bind>
<opset="B4_sum "/>
</bind>
</comp>

<comp id="303" class="1005" name="gmem_addr_1_reg_303">
<pin_list>
<pin id="304" dir="0" index="0" bw="32" slack="1"/>
<pin id="305" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="gmem_addr_1 "/>
</bind>
</comp>

<comp id="309" class="1005" name="gmem_addr_2_reg_309">
<pin_list>
<pin id="310" dir="0" index="0" bw="32" slack="1"/>
<pin id="311" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="gmem_addr_2 "/>
</bind>
</comp>

<comp id="315" class="1005" name="gmem_addr_1_read_reg_315">
<pin_list>
<pin id="316" dir="0" index="0" bw="32" slack="2"/>
<pin id="317" dir="1" index="1" bw="32" slack="2"/>
</pin_list>
<bind>
<opset="gmem_addr_1_read "/>
</bind>
</comp>

<comp id="320" class="1005" name="gmem_addr_2_read_reg_320">
<pin_list>
<pin id="321" dir="0" index="0" bw="32" slack="1"/>
<pin id="322" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="gmem_addr_2_read "/>
</bind>
</comp>

<comp id="325" class="1005" name="tmp_1_reg_325">
<pin_list>
<pin id="326" dir="0" index="0" bw="32" slack="1"/>
<pin id="327" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="tmp_1 "/>
</bind>
</comp>

</comp_list>

<net_list>
<net id="92"><net_src comp="8" pin="0"/><net_sink comp="88" pin=0"/></net>

<net id="93"><net_src comp="6" pin="0"/><net_sink comp="88" pin=1"/></net>

<net id="98"><net_src comp="8" pin="0"/><net_sink comp="94" pin=0"/></net>

<net id="99"><net_src comp="4" pin="0"/><net_sink comp="94" pin=1"/></net>

<net id="104"><net_src comp="8" pin="0"/><net_sink comp="100" pin=0"/></net>

<net id="105"><net_src comp="2" pin="0"/><net_sink comp="100" pin=1"/></net>

<net id="111"><net_src comp="50" pin="0"/><net_sink comp="106" pin=0"/></net>

<net id="112"><net_src comp="52" pin="0"/><net_sink comp="106" pin=2"/></net>

<net id="118"><net_src comp="60" pin="0"/><net_sink comp="113" pin=0"/></net>

<net id="119"><net_src comp="62" pin="0"/><net_sink comp="113" pin=2"/></net>

<net id="125"><net_src comp="60" pin="0"/><net_sink comp="120" pin=0"/></net>

<net id="126"><net_src comp="62" pin="0"/><net_sink comp="120" pin=2"/></net>

<net id="131"><net_src comp="64" pin="0"/><net_sink comp="127" pin=0"/></net>

<net id="136"><net_src comp="64" pin="0"/><net_sink comp="132" pin=0"/></net>

<net id="143"><net_src comp="80" pin="0"/><net_sink comp="137" pin=0"/></net>

<net id="144"><net_src comp="82" pin="0"/><net_sink comp="137" pin=3"/></net>

<net id="145"><net_src comp="86" pin="0"/><net_sink comp="106" pin=0"/></net>

<net id="149"><net_src comp="54" pin="0"/><net_sink comp="146" pin=0"/></net>

<net id="156"><net_src comp="146" pin="1"/><net_sink comp="150" pin=0"/></net>

<net id="163"><net_src comp="10" pin="0"/><net_sink comp="157" pin=0"/></net>

<net id="164"><net_src comp="88" pin="2"/><net_sink comp="157" pin=1"/></net>

<net id="165"><net_src comp="12" pin="0"/><net_sink comp="157" pin=2"/></net>

<net id="166"><net_src comp="14" pin="0"/><net_sink comp="157" pin=3"/></net>

<net id="173"><net_src comp="10" pin="0"/><net_sink comp="167" pin=0"/></net>

<net id="174"><net_src comp="94" pin="2"/><net_sink comp="167" pin=1"/></net>

<net id="175"><net_src comp="12" pin="0"/><net_sink comp="167" pin=2"/></net>

<net id="176"><net_src comp="14" pin="0"/><net_sink comp="167" pin=3"/></net>

<net id="183"><net_src comp="10" pin="0"/><net_sink comp="177" pin=0"/></net>

<net id="184"><net_src comp="100" pin="2"/><net_sink comp="177" pin=1"/></net>

<net id="185"><net_src comp="12" pin="0"/><net_sink comp="177" pin=2"/></net>

<net id="186"><net_src comp="14" pin="0"/><net_sink comp="177" pin=3"/></net>

<net id="194"><net_src comp="0" pin="0"/><net_sink comp="190" pin=0"/></net>

<net id="195"><net_src comp="187" pin="1"/><net_sink comp="190" pin=1"/></net>

<net id="196"><net_src comp="190" pin="2"/><net_sink comp="106" pin=1"/></net>

<net id="207"><net_src comp="150" pin="4"/><net_sink comp="203" pin=0"/></net>

<net id="208"><net_src comp="56" pin="0"/><net_sink comp="203" pin=1"/></net>

<net id="213"><net_src comp="150" pin="4"/><net_sink comp="209" pin=0"/></net>

<net id="214"><net_src comp="58" pin="0"/><net_sink comp="209" pin=1"/></net>

<net id="218"><net_src comp="150" pin="4"/><net_sink comp="215" pin=0"/></net>

<net id="223"><net_src comp="215" pin="1"/><net_sink comp="219" pin=0"/></net>

<net id="228"><net_src comp="215" pin="1"/><net_sink comp="224" pin=0"/></net>

<net id="236"><net_src comp="0" pin="0"/><net_sink comp="232" pin=0"/></net>

<net id="237"><net_src comp="229" pin="1"/><net_sink comp="232" pin=1"/></net>

<net id="238"><net_src comp="232" pin="2"/><net_sink comp="113" pin=1"/></net>

<net id="246"><net_src comp="0" pin="0"/><net_sink comp="242" pin=0"/></net>

<net id="247"><net_src comp="239" pin="1"/><net_sink comp="242" pin=1"/></net>

<net id="248"><net_src comp="242" pin="2"/><net_sink comp="120" pin=1"/></net>

<net id="256"><net_src comp="157" pin="4"/><net_sink comp="253" pin=0"/></net>

<net id="257"><net_src comp="253" pin="1"/><net_sink comp="187" pin=0"/></net>

<net id="261"><net_src comp="167" pin="4"/><net_sink comp="258" pin=0"/></net>

<net id="262"><net_src comp="258" pin="1"/><net_sink comp="197" pin=0"/></net>

<net id="266"><net_src comp="177" pin="4"/><net_sink comp="263" pin=0"/></net>

<net id="267"><net_src comp="263" pin="1"/><net_sink comp="200" pin=0"/></net>

<net id="271"><net_src comp="190" pin="2"/><net_sink comp="268" pin=0"/></net>

<net id="272"><net_src comp="268" pin="1"/><net_sink comp="137" pin=1"/></net>

<net id="273"><net_src comp="268" pin="1"/><net_sink comp="106" pin=1"/></net>

<net id="277"><net_src comp="197" pin="1"/><net_sink comp="274" pin=0"/></net>

<net id="278"><net_src comp="274" pin="1"/><net_sink comp="224" pin=1"/></net>

<net id="282"><net_src comp="200" pin="1"/><net_sink comp="279" pin=0"/></net>

<net id="283"><net_src comp="279" pin="1"/><net_sink comp="219" pin=1"/></net>

<net id="287"><net_src comp="203" pin="2"/><net_sink comp="284" pin=0"/></net>

<net id="291"><net_src comp="209" pin="2"/><net_sink comp="288" pin=0"/></net>

<net id="292"><net_src comp="288" pin="1"/><net_sink comp="150" pin=2"/></net>

<net id="296"><net_src comp="219" pin="2"/><net_sink comp="293" pin=0"/></net>

<net id="297"><net_src comp="293" pin="1"/><net_sink comp="229" pin=0"/></net>

<net id="301"><net_src comp="224" pin="2"/><net_sink comp="298" pin=0"/></net>

<net id="302"><net_src comp="298" pin="1"/><net_sink comp="239" pin=0"/></net>

<net id="306"><net_src comp="232" pin="2"/><net_sink comp="303" pin=0"/></net>

<net id="307"><net_src comp="303" pin="1"/><net_sink comp="113" pin=1"/></net>

<net id="308"><net_src comp="303" pin="1"/><net_sink comp="127" pin=1"/></net>

<net id="312"><net_src comp="242" pin="2"/><net_sink comp="309" pin=0"/></net>

<net id="313"><net_src comp="309" pin="1"/><net_sink comp="120" pin=1"/></net>

<net id="314"><net_src comp="309" pin="1"/><net_sink comp="132" pin=1"/></net>

<net id="318"><net_src comp="127" pin="2"/><net_sink comp="315" pin=0"/></net>

<net id="319"><net_src comp="315" pin="1"/><net_sink comp="249" pin=1"/></net>

<net id="323"><net_src comp="132" pin="2"/><net_sink comp="320" pin=0"/></net>

<net id="324"><net_src comp="320" pin="1"/><net_sink comp="249" pin=0"/></net>

<net id="328"><net_src comp="249" pin="2"/><net_sink comp="325" pin=0"/></net>

<net id="329"><net_src comp="325" pin="1"/><net_sink comp="137" pin=2"/></net>

</net_list>

</model> 
---------------- Datapath Model END ------------------

* FSMD analyzer results:
  - Output states:
	Port: gmem | {2 14 15 16 17 18 19 }
 - Input state : 
	Port: vector_mult : gmem | {4 5 6 7 8 9 10 11 12 }
	Port: vector_mult : A | {1 }
	Port: vector_mult : B | {1 }
	Port: vector_mult : result | {1 }
  - Chain level:
	State 1
	State 2
		gmem_addr : 1
		gmem_addr_wr_req : 2
	State 3
		exitcond : 1
		i_1 : 1
		StgValue_42 : 2
		tmp_cast : 1
		A2_sum : 2
		B4_sum : 2
	State 4
		gmem_addr_1 : 1
		gmem_load_req : 2
	State 5
		gmem_addr_2 : 1
		gmem_load_1_req : 2
	State 6
	State 7
	State 8
	State 9
	State 10
	State 11
	State 12
	State 13
	State 14
		empty_4 : 1
	State 15
	State 16
	State 17
	State 18
	State 19


============================================================
+ Verbose Summary: Datapath Resource usage 
============================================================

* Functional unit list:
|----------|------------------------------|---------|---------|---------|
| Operation|        Functional Unit       |  DSP48E |    FF   |   LUT   |
|----------|------------------------------|---------|---------|---------|
|          |          i_1_fu_209          |    0    |    0    |    13   |
|    add   |         A2_sum_fu_219        |    0    |    0    |    37   |
|          |         B4_sum_fu_224        |    0    |    0    |    37   |
|----------|------------------------------|---------|---------|---------|
|    mul   |         tmp_1_fu_249         |    3    |    0    |    20   |
|----------|------------------------------|---------|---------|---------|
|   icmp   |        exitcond_fu_203       |    0    |    0    |    9    |
|----------|------------------------------|---------|---------|---------|
|          |    result_read_read_fu_88    |    0    |    0    |    0    |
|          |       B_read_read_fu_94      |    0    |    0    |    0    |
|   read   |      A_read_read_fu_100      |    0    |    0    |    0    |
|          | gmem_addr_1_read_read_fu_127 |    0    |    0    |    0    |
|          | gmem_addr_2_read_read_fu_132 |    0    |    0    |    0    |
|----------|------------------------------|---------|---------|---------|
| writeresp|     grp_writeresp_fu_106     |    0    |    0    |    0    |
|----------|------------------------------|---------|---------|---------|
|  readreq |      grp_readreq_fu_113      |    0    |    0    |    0    |
|          |      grp_readreq_fu_120      |    0    |    0    |    0    |
|----------|------------------------------|---------|---------|---------|
|   write  |   StgValue_71_write_fu_137   |    0    |    0    |    0    |
|----------|------------------------------|---------|---------|---------|
|          |        result5_fu_157        |    0    |    0    |    0    |
|partselect|          tmp_fu_167          |    0    |    0    |    0    |
|          |         tmp_4_fu_177         |    0    |    0    |    0    |
|----------|------------------------------|---------|---------|---------|
|          |         tmp_3_fu_187         |    0    |    0    |    0    |
|          |       tmp_4_cast_fu_197      |    0    |    0    |    0    |
|   zext   |       tmp_5_cast_fu_200      |    0    |    0    |    0    |
|          |        tmp_cast_fu_215       |    0    |    0    |    0    |
|          |      A2_sum_cast_fu_229      |    0    |    0    |    0    |
|          |      B4_sum_cast_fu_239      |    0    |    0    |    0    |
|----------|------------------------------|---------|---------|---------|
|   Total  |                              |    3    |    0    |   116   |
|----------|------------------------------|---------|---------|---------|

Memories:
N/A

* Register list:
+------------------------+--------+
|                        |   FF   |
+------------------------+--------+
|     A2_sum_reg_293     |   31   |
|     B4_sum_reg_298     |   31   |
|    exitcond_reg_284    |    1   |
|gmem_addr_1_read_reg_315|   32   |
|   gmem_addr_1_reg_303  |   32   |
|gmem_addr_2_read_reg_320|   32   |
|   gmem_addr_2_reg_309  |   32   |
|    gmem_addr_reg_268   |   32   |
|       i_1_reg_288      |    4   |
|        i_reg_146       |    4   |
|     result5_reg_253    |   30   |
|      tmp_1_reg_325     |   32   |
|   tmp_4_cast_reg_274   |   31   |
|      tmp_4_reg_263     |   30   |
|   tmp_5_cast_reg_279   |   31   |
|       tmp_reg_258      |   30   |
+------------------------+--------+
|          Total         |   415  |
+------------------------+--------+

* Multiplexer (MUX) list: 
|----------------------|------|------|------|--------||---------||---------|
|         Comp         |  Pin | Size |  BW  | S x BW ||  Delay  ||   LUT   |
|----------------------|------|------|------|--------||---------||---------|
| grp_writeresp_fu_106 |  p0  |   2  |   1  |    2   |
| grp_writeresp_fu_106 |  p1  |   2  |  32  |   64   ||    9    |
|  grp_readreq_fu_113  |  p1  |   2  |  32  |   64   ||    9    |
|  grp_readreq_fu_120  |  p1  |   2  |  32  |   64   ||    9    |
|----------------------|------|------|------|--------||---------||---------|
|         Total        |      |      |      |   194  ||  7.076  ||    27   |
|----------------------|------|------|------|--------||---------||---------|



* Summary:
+-----------+--------+--------+--------+--------+
|           | DSP48E |  Delay |   FF   |   LUT  |
+-----------+--------+--------+--------+--------+
|  Function |    3   |    -   |    0   |   116  |
|   Memory  |    -   |    -   |    -   |    -   |
|Multiplexer|    -   |    7   |    -   |   27   |
|  Register |    -   |    -   |   415  |    -   |
+-----------+--------+--------+--------+--------+
|   Total   |    3   |    7   |   415  |   143  |
+-----------+--------+--------+--------+--------+