================================================================ == Vivado HLS Report for 'vector_mult' ================================================================ * Date: Mon Mar 19 11:25:20 2018 * Version: 2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017) * Project: vector_mult * Solution: solution0 * Product family: zynq * Target device: xc7z020clg484-1 ================================================================ == Performance Estimates ================================================================ + Timing (ns): * Summary: +--------+-------+----------+------------+ | Clock | Target| Estimated| Uncertainty| +--------+-------+----------+------------+ |ap_clk | 10.00| 8.75| 1.25| +--------+-------+----------+------------+ + Latency (clock cycles): * Summary: +-----+-----+-----+-----+---------+ | Latency | Interval | Pipeline| | min | max | min | max | Type | +-----+-----+-----+-----+---------+ | 23| 23| 23| 23| none | +-----+-----+-----+-----+---------+ + Detail: * Instance: N/A * Loop: +--------------------+-----+-----+----------+-----------+-----------+------+----------+ | | Latency | Iteration| Initiation Interval | Trip | | | Loop Name | min | max | Latency | achieved | target | Count| Pipelined| +--------------------+-----+-----+----------+-----------+-----------+------+----------+ |- vector_mult_loop | 10| 10| 4| 1| 1| 8| yes | +--------------------+-----+-----+----------+-----------+-----------+------+----------+ ================================================================ == Utilization Estimates ================================================================ * Summary: +-----------------+---------+-------+--------+-------+ | Name | BRAM_18K| DSP48E| FF | LUT | +-----------------+---------+-------+--------+-------+ |DSP | -| -| -| -| |Expression | -| 3| 0| 100| |FIFO | -| -| -| -| |Instance | 6| -| 1686| 1972| |Memory | -| -| -| -| |Multiplexer | -| -| -| 188| |Register | 0| -| 277| 32| +-----------------+---------+-------+--------+-------+ |Total | 6| 3| 1963| 2292| +-----------------+---------+-------+--------+-------+ |Available | 280| 220| 106400| 53200| +-----------------+---------+-------+--------+-------+ |Utilization (%) | 2| 1| 1| 4| +-----------------+---------+-------+--------+-------+ + Detail: * Instance: +------------------------------+----------------------------+---------+-------+-----+-----+ | Instance | Module | BRAM_18K| DSP48E| FF | LUT | +------------------------------+----------------------------+---------+-------+-----+-----+ |vector_mult_AXILiteS_s_axi_U |vector_mult_AXILiteS_s_axi | 0| 0| 150| 232| |vector_mult_A_m_axi_U |vector_mult_A_m_axi | 2| 0| 512| 580| |vector_mult_B_m_axi_U |vector_mult_B_m_axi | 2| 0| 512| 580| |vector_mult_result_m_axi_U |vector_mult_result_m_axi | 2| 0| 512| 580| +------------------------------+----------------------------+---------+-------+-----+-----+ |Total | | 6| 0| 1686| 1972| +------------------------------+----------------------------+---------+-------+-----+-----+ * DSP48: N/A * Memory: N/A * FIFO: N/A * Expression: +-----------------------------------+----------+-------+---+----+------------+------------+ | Variable Name | Operation| DSP48E| FF| LUT| Bitwidth P0| Bitwidth P1| +-----------------------------------+----------+-------+---+----+------------+------------+ |tmp_1_fu_239_p2 | * | 3| 0| 20| 32| 32| |i_1_fu_233_p2 | + | 0| 0| 13| 4| 1| |ap_block_pp0_stage0_01001 | and | 0| 0| 8| 1| 1| |ap_block_state12_io | and | 0| 0| 8| 1| 1| |exitcond_fu_227_p2 | icmp | 0| 0| 11| 4| 5| |ap_block_pp0_stage0_11001 | or | 0| 0| 8| 1| 1| |ap_block_state10_pp0_stage0_iter1 | or | 0| 0| 8| 1| 1| |ap_block_state2_io | or | 0| 0| 8| 1| 1| |ap_enable_pp0 | xor | 0| 0| 8| 1| 2| |ap_enable_reg_pp0_iter1 | xor | 0| 0| 8| 2| 1| +-----------------------------------+----------+-------+---+----+------------+------------+ |Total | | 3| 0| 100| 48| 46| +-----------------------------------+----------+-------+---+----+------------+------------+ * Multiplexer: +-------------------------------+----+-----------+-----+-----------+ | Name | LUT| Input Size| Bits| Total Bits| +-------------------------------+----+-----------+-----+-----------+ |A_blk_n_AR | 9| 2| 1| 2| |A_blk_n_R | 9| 2| 1| 2| |B_blk_n_AR | 9| 2| 1| 2| |B_blk_n_R | 9| 2| 1| 2| |ap_NS_fsm | 62| 15| 1| 15| |ap_enable_reg_pp0_iter1 | 9| 2| 1| 2| |ap_enable_reg_pp0_iter3 | 9| 2| 1| 2| |ap_sig_ioackin_A_ARREADY | 9| 2| 1| 2| |ap_sig_ioackin_B_ARREADY | 9| 2| 1| 2| |ap_sig_ioackin_result_AWREADY | 9| 2| 1| 2| |ap_sig_ioackin_result_WREADY | 9| 2| 1| 2| |i_reg_156 | 9| 2| 4| 8| |result_blk_n_AW | 9| 2| 1| 2| |result_blk_n_B | 9| 2| 1| 2| |result_blk_n_W | 9| 2| 1| 2| +-------------------------------+----+-----------+-----+-----------+ |Total | 188| 43| 18| 49| +-------------------------------+----+-----------+-----+-----------+ * Register: +-------------------------------+----+----+-----+-----------+ | Name | FF | LUT| Bits| Const Bits| +-------------------------------+----+----+-----+-----------+ |A_addr_read_reg_285 | 32| 0| 32| 0| |A_offset1_reg_253 | 30| 0| 30| 0| |B_addr_read_reg_290 | 32| 0| 32| 0| |B_offset3_reg_248 | 30| 0| 30| 0| |ap_CS_fsm | 14| 0| 14| 0| |ap_enable_reg_pp0_iter0 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter1 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter2 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter3 | 1| 0| 1| 0| |ap_reg_ioackin_A_ARREADY | 1| 0| 1| 0| |ap_reg_ioackin_B_ARREADY | 1| 0| 1| 0| |ap_reg_ioackin_result_AWREADY | 1| 0| 1| 0| |ap_reg_ioackin_result_WREADY | 1| 0| 1| 0| |exitcond_reg_276 | 1| 0| 1| 0| |i_reg_156 | 4| 0| 4| 0| |result_offset5_reg_243 | 30| 0| 30| 0| |tmp_1_reg_295 | 32| 0| 32| 0| |exitcond_reg_276 | 64| 32| 1| 0| +-------------------------------+----+----+-----+-----------+ |Total | 277| 32| 214| 0| +-------------------------------+----+----+-----+-----------+ ================================================================ == Interface ================================================================ * Summary: +------------------------+-----+-----+------------+--------------+--------------+ | RTL Ports | Dir | Bits| Protocol | Source Object| C Type | +------------------------+-----+-----+------------+--------------+--------------+ |s_axi_AXILiteS_AWVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_AWREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_AWADDR | in | 6| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WDATA | in | 32| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WSTRB | in | 4| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARADDR | in | 6| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RVALID | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RREADY | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RDATA | out | 32| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RRESP | out | 2| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BVALID | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BREADY | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BRESP | out | 2| s_axi | AXILiteS | scalar | |ap_clk | in | 1| ap_ctrl_hs | vector_mult | return value | |ap_rst_n | in | 1| ap_ctrl_hs | vector_mult | return value | |interrupt | out | 1| ap_ctrl_hs | vector_mult | return value | |m_axi_A_AWVALID | out | 1| m_axi | A | pointer | |m_axi_A_AWREADY | in | 1| m_axi | A | pointer | |m_axi_A_AWADDR | out | 32| m_axi | A | pointer | |m_axi_A_AWID | out | 1| m_axi | A | pointer | |m_axi_A_AWLEN | out | 8| m_axi | A | pointer | |m_axi_A_AWSIZE | out | 3| m_axi | A | pointer | |m_axi_A_AWBURST | out | 2| m_axi | A | pointer | |m_axi_A_AWLOCK | out | 2| m_axi | A | pointer | |m_axi_A_AWCACHE | out | 4| m_axi | A | pointer | |m_axi_A_AWPROT | out | 3| m_axi | A | pointer | |m_axi_A_AWQOS | out | 4| m_axi | A | pointer | |m_axi_A_AWREGION | out | 4| m_axi | A | pointer | |m_axi_A_AWUSER | out | 1| m_axi | A | pointer | |m_axi_A_WVALID | out | 1| m_axi | A | pointer | |m_axi_A_WREADY | in | 1| m_axi | A | pointer | |m_axi_A_WDATA | out | 32| m_axi | A | pointer | |m_axi_A_WSTRB | out | 4| m_axi | A | pointer | |m_axi_A_WLAST | out | 1| m_axi | A | pointer | |m_axi_A_WID | out | 1| m_axi | A | pointer | |m_axi_A_WUSER | out | 1| m_axi | A | pointer | |m_axi_A_ARVALID | out | 1| m_axi | A | pointer | |m_axi_A_ARREADY | in | 1| m_axi | A | pointer | |m_axi_A_ARADDR | out | 32| m_axi | A | pointer | |m_axi_A_ARID | out | 1| m_axi | A | pointer | |m_axi_A_ARLEN | out | 8| m_axi | A | pointer | |m_axi_A_ARSIZE | out | 3| m_axi | A | pointer | |m_axi_A_ARBURST | out | 2| m_axi | A | pointer | |m_axi_A_ARLOCK | out | 2| m_axi | A | pointer | |m_axi_A_ARCACHE | out | 4| m_axi | A | pointer | |m_axi_A_ARPROT | out | 3| m_axi | A | pointer | |m_axi_A_ARQOS | out | 4| m_axi | A | pointer | |m_axi_A_ARREGION | out | 4| m_axi | A | pointer | |m_axi_A_ARUSER | out | 1| m_axi | A | pointer | |m_axi_A_RVALID | in | 1| m_axi | A | pointer | |m_axi_A_RREADY | out | 1| m_axi | A | pointer | |m_axi_A_RDATA | in | 32| m_axi | A | pointer | |m_axi_A_RLAST | in | 1| m_axi | A | pointer | |m_axi_A_RID | in | 1| m_axi | A | pointer | |m_axi_A_RUSER | in | 1| m_axi | A | pointer | |m_axi_A_RRESP | in | 2| m_axi | A | pointer | |m_axi_A_BVALID | in | 1| m_axi | A | pointer | |m_axi_A_BREADY | out | 1| m_axi | A | pointer | |m_axi_A_BRESP | in | 2| m_axi | A | pointer | |m_axi_A_BID | in | 1| m_axi | A | pointer | |m_axi_A_BUSER | in | 1| m_axi | A | pointer | |m_axi_B_AWVALID | out | 1| m_axi | B | pointer | |m_axi_B_AWREADY | in | 1| m_axi | B | pointer | |m_axi_B_AWADDR | out | 32| m_axi | B | pointer | |m_axi_B_AWID | out | 1| m_axi | B | pointer | |m_axi_B_AWLEN | out | 8| m_axi | B | pointer | |m_axi_B_AWSIZE | out | 3| m_axi | B | pointer | |m_axi_B_AWBURST | out | 2| m_axi | B | pointer | |m_axi_B_AWLOCK | out | 2| m_axi | B | pointer | |m_axi_B_AWCACHE | out | 4| m_axi | B | pointer | |m_axi_B_AWPROT | out | 3| m_axi | B | pointer | |m_axi_B_AWQOS | out | 4| m_axi | B | pointer | |m_axi_B_AWREGION | out | 4| m_axi | B | pointer | |m_axi_B_AWUSER | out | 1| m_axi | B | pointer | |m_axi_B_WVALID | out | 1| m_axi | B | pointer | |m_axi_B_WREADY | in | 1| m_axi | B | pointer | |m_axi_B_WDATA | out | 32| m_axi | B | pointer | |m_axi_B_WSTRB | out | 4| m_axi | B | pointer | |m_axi_B_WLAST | out | 1| m_axi | B | pointer | |m_axi_B_WID | out | 1| m_axi | B | pointer | |m_axi_B_WUSER | out | 1| m_axi | B | pointer | |m_axi_B_ARVALID | out | 1| m_axi | B | pointer | |m_axi_B_ARREADY | in | 1| m_axi | B | pointer | |m_axi_B_ARADDR | out | 32| m_axi | B | pointer | |m_axi_B_ARID | out | 1| m_axi | B | pointer | |m_axi_B_ARLEN | out | 8| m_axi | B | pointer | |m_axi_B_ARSIZE | out | 3| m_axi | B | pointer | |m_axi_B_ARBURST | out | 2| m_axi | B | pointer | |m_axi_B_ARLOCK | out | 2| m_axi | B | pointer | |m_axi_B_ARCACHE | out | 4| m_axi | B | pointer | |m_axi_B_ARPROT | out | 3| m_axi | B | pointer | |m_axi_B_ARQOS | out | 4| m_axi | B | pointer | |m_axi_B_ARREGION | out | 4| m_axi | B | pointer | |m_axi_B_ARUSER | out | 1| m_axi | B | pointer | |m_axi_B_RVALID | in | 1| m_axi | B | pointer | |m_axi_B_RREADY | out | 1| m_axi | B | pointer | |m_axi_B_RDATA | in | 32| m_axi | B | pointer | |m_axi_B_RLAST | in | 1| m_axi | B | pointer | |m_axi_B_RID | in | 1| m_axi | B | pointer | |m_axi_B_RUSER | in | 1| m_axi | B | pointer | |m_axi_B_RRESP | in | 2| m_axi | B | pointer | |m_axi_B_BVALID | in | 1| m_axi | B | pointer | |m_axi_B_BREADY | out | 1| m_axi | B | pointer | |m_axi_B_BRESP | in | 2| m_axi | B | pointer | |m_axi_B_BID | in | 1| m_axi | B | pointer | |m_axi_B_BUSER | in | 1| m_axi | B | pointer | |m_axi_result_AWVALID | out | 1| m_axi | result | pointer | |m_axi_result_AWREADY | in | 1| m_axi | result | pointer | |m_axi_result_AWADDR | out | 32| m_axi | result | pointer | |m_axi_result_AWID | out | 1| m_axi | result | pointer | |m_axi_result_AWLEN | out | 8| m_axi | result | pointer | |m_axi_result_AWSIZE | out | 3| m_axi | result | pointer | |m_axi_result_AWBURST | out | 2| m_axi | result | pointer | |m_axi_result_AWLOCK | out | 2| m_axi | result | pointer | |m_axi_result_AWCACHE | out | 4| m_axi | result | pointer | |m_axi_result_AWPROT | out | 3| m_axi | result | pointer | |m_axi_result_AWQOS | out | 4| m_axi | result | pointer | |m_axi_result_AWREGION | out | 4| m_axi | result | pointer | |m_axi_result_AWUSER | out | 1| m_axi | result | pointer | |m_axi_result_WVALID | out | 1| m_axi | result | pointer | |m_axi_result_WREADY | in | 1| m_axi | result | pointer | |m_axi_result_WDATA | out | 32| m_axi | result | pointer | |m_axi_result_WSTRB | out | 4| m_axi | result | pointer | |m_axi_result_WLAST | out | 1| m_axi | result | pointer | |m_axi_result_WID | out | 1| m_axi | result | pointer | |m_axi_result_WUSER | out | 1| m_axi | result | pointer | |m_axi_result_ARVALID | out | 1| m_axi | result | pointer | |m_axi_result_ARREADY | in | 1| m_axi | result | pointer | |m_axi_result_ARADDR | out | 32| m_axi | result | pointer | |m_axi_result_ARID | out | 1| m_axi | result | pointer | |m_axi_result_ARLEN | out | 8| m_axi | result | pointer | |m_axi_result_ARSIZE | out | 3| m_axi | result | pointer | |m_axi_result_ARBURST | out | 2| m_axi | result | pointer | |m_axi_result_ARLOCK | out | 2| m_axi | result | pointer | |m_axi_result_ARCACHE | out | 4| m_axi | result | pointer | |m_axi_result_ARPROT | out | 3| m_axi | result | pointer | |m_axi_result_ARQOS | out | 4| m_axi | result | pointer | |m_axi_result_ARREGION | out | 4| m_axi | result | pointer | |m_axi_result_ARUSER | out | 1| m_axi | result | pointer | |m_axi_result_RVALID | in | 1| m_axi | result | pointer | |m_axi_result_RREADY | out | 1| m_axi | result | pointer | |m_axi_result_RDATA | in | 32| m_axi | result | pointer | |m_axi_result_RLAST | in | 1| m_axi | result | pointer | |m_axi_result_RID | in | 1| m_axi | result | pointer | |m_axi_result_RUSER | in | 1| m_axi | result | pointer | |m_axi_result_RRESP | in | 2| m_axi | result | pointer | |m_axi_result_BVALID | in | 1| m_axi | result | pointer | |m_axi_result_BREADY | out | 1| m_axi | result | pointer | |m_axi_result_BRESP | in | 2| m_axi | result | pointer | |m_axi_result_BID | in | 1| m_axi | result | pointer | |m_axi_result_BUSER | in | 1| m_axi | result | pointer | +------------------------+-----+-----+------------+--------------+--------------+