0.6
2017.4
Dec 15 2017
20:57:24
/home/hakta/Documents/vector_mult/solution0/sim/verilog/AESL_axi_master_A.v,1521455133,systemVerilog,,,,AESL_axi_master_A,/opt/Xilinx/Vivado/2017.4/data/xsim/ip/xsim_ip.ini,axi_protocol_checker_v1_1_12;axi_protocol_checker_v1_1_13;axis_protocol_checker_v1_1_11;axis_protocol_checker_v1_1_12;ieee_proposed=./ieee_proposed;smartconnect_v1_0;unisims_ver;xil_defaultlib,,,,,,
/home/hakta/Documents/vector_mult/solution0/sim/verilog/AESL_axi_master_B.v,1521455133,systemVerilog,,,,AESL_axi_master_B,/opt/Xilinx/Vivado/2017.4/data/xsim/ip/xsim_ip.ini,axi_protocol_checker_v1_1_12;axi_protocol_checker_v1_1_13;axis_protocol_checker_v1_1_11;axis_protocol_checker_v1_1_12;ieee_proposed=./ieee_proposed;smartconnect_v1_0;unisims_ver;xil_defaultlib,,,,,,
/home/hakta/Documents/vector_mult/solution0/sim/verilog/AESL_axi_master_result.v,1521455133,systemVerilog,,,,AESL_axi_master_result,/opt/Xilinx/Vivado/2017.4/data/xsim/ip/xsim_ip.ini,axi_protocol_checker_v1_1_12;axi_protocol_checker_v1_1_13;axis_protocol_checker_v1_1_11;axis_protocol_checker_v1_1_12;ieee_proposed=./ieee_proposed;smartconnect_v1_0;unisims_ver;xil_defaultlib,,,,,,
/home/hakta/Documents/vector_mult/solution0/sim/verilog/AESL_axi_slave_AXILiteS.v,1521455133,systemVerilog,,,,AESL_axi_slave_AXILiteS,/opt/Xilinx/Vivado/2017.4/data/xsim/ip/xsim_ip.ini,axi_protocol_checker_v1_1_12;axi_protocol_checker_v1_1_13;axis_protocol_checker_v1_1_11;axis_protocol_checker_v1_1_12;ieee_proposed=./ieee_proposed;smartconnect_v1_0;unisims_ver;xil_defaultlib,,,,,,
/home/hakta/Documents/vector_mult/solution0/sim/verilog/vector_mult.autotb.v,1521455133,systemVerilog,,,,apatb_vector_mult_top,/opt/Xilinx/Vivado/2017.4/data/xsim/ip/xsim_ip.ini,axi_protocol_checker_v1_1_12;axi_protocol_checker_v1_1_13;axis_protocol_checker_v1_1_11;axis_protocol_checker_v1_1_12;ieee_proposed=./ieee_proposed;smartconnect_v1_0;unisims_ver;xil_defaultlib,,,,,,
/home/hakta/Documents/vector_mult/solution0/sim/verilog/vector_mult.v,1521455120,systemVerilog,,,,vector_mult,/opt/Xilinx/Vivado/2017.4/data/xsim/ip/xsim_ip.ini,axi_protocol_checker_v1_1_12;axi_protocol_checker_v1_1_13;axis_protocol_checker_v1_1_11;axis_protocol_checker_v1_1_12;ieee_proposed=./ieee_proposed;smartconnect_v1_0;unisims_ver;xil_defaultlib,,,,,,
/home/hakta/Documents/vector_mult/solution0/sim/verilog/vector_mult_AXILiteS_s_axi.v,1521455120,systemVerilog,,,,vector_mult_AXILiteS_s_axi,/opt/Xilinx/Vivado/2017.4/data/xsim/ip/xsim_ip.ini,axi_protocol_checker_v1_1_12;axi_protocol_checker_v1_1_13;axis_protocol_checker_v1_1_11;axis_protocol_checker_v1_1_12;ieee_proposed=./ieee_proposed;smartconnect_v1_0;unisims_ver;xil_defaultlib,,,,,,
/home/hakta/Documents/vector_mult/solution0/sim/verilog/vector_mult_A_m_axi.v,1521455120,systemVerilog,,,,vector_mult_A_m_axi;vector_mult_A_m_axi_buffer;vector_mult_A_m_axi_decoder;vector_mult_A_m_axi_fifo;vector_mult_A_m_axi_read;vector_mult_A_m_axi_reg_slice;vector_mult_A_m_axi_throttl;vector_mult_A_m_axi_write,/opt/Xilinx/Vivado/2017.4/data/xsim/ip/xsim_ip.ini,axi_protocol_checker_v1_1_12;axi_protocol_checker_v1_1_13;axis_protocol_checker_v1_1_11;axis_protocol_checker_v1_1_12;ieee_proposed=./ieee_proposed;smartconnect_v1_0;unisims_ver;xil_defaultlib,,,,,,
/home/hakta/Documents/vector_mult/solution0/sim/verilog/vector_mult_B_m_axi.v,1521455121,systemVerilog,,,,vector_mult_B_m_axi;vector_mult_B_m_axi_buffer;vector_mult_B_m_axi_decoder;vector_mult_B_m_axi_fifo;vector_mult_B_m_axi_read;vector_mult_B_m_axi_reg_slice;vector_mult_B_m_axi_throttl;vector_mult_B_m_axi_write,/opt/Xilinx/Vivado/2017.4/data/xsim/ip/xsim_ip.ini,axi_protocol_checker_v1_1_12;axi_protocol_checker_v1_1_13;axis_protocol_checker_v1_1_11;axis_protocol_checker_v1_1_12;ieee_proposed=./ieee_proposed;smartconnect_v1_0;unisims_ver;xil_defaultlib,,,,,,
/home/hakta/Documents/vector_mult/solution0/sim/verilog/vector_mult_result_m_axi.v,1521455121,systemVerilog,,,,vector_mult_result_m_axi;vector_mult_result_m_axi_buffer;vector_mult_result_m_axi_decoder;vector_mult_result_m_axi_fifo;vector_mult_result_m_axi_read;vector_mult_result_m_axi_reg_slice;vector_mult_result_m_axi_throttl;vector_mult_result_m_axi_write,/opt/Xilinx/Vivado/2017.4/data/xsim/ip/xsim_ip.ini,axi_protocol_checker_v1_1_12;axi_protocol_checker_v1_1_13;axis_protocol_checker_v1_1_11;axis_protocol_checker_v1_1_12;ieee_proposed=./ieee_proposed;smartconnect_v1_0;unisims_ver;xil_defaultlib,,,,,,