Folder Path

/MSc/HLS-FPGA/vector_mult/solution0/sim/verilog/

2 directories 29 files 518 KiB total
List Grid
Name
Size Modified
Up
.Xil/ —
xsim.dir/ —
.run_sim.tcl
9.8 KiB
.sim.status.tcl
1.3 KiB
AESL_axi_master_A.v
36 KiB
AESL_axi_master_B.v
36 KiB
AESL_axi_master_result.v
42 KiB
AESL_axi_slave_AXILiteS.v
21 KiB
check_sim.tcl
4.2 KiB
glbl.v
1.4 KiB
run_sim.tcl
2.5 KiB
run_xsim.sh
493 B
sim.sh
413 B
vector_mult.autotb.v
33 KiB
vector_mult.performance.result.transaction.xml
106 B
vector_mult.prj
444 B
vector_mult.result.lat.rb
128 B
vector_mult.tcl
30 B
vector_mult.v
41 KiB
vector_mult_A_m_axi.v
83 KiB
vector_mult_AXILiteS_s_axi.v
11 KiB
vector_mult_B_m_axi.v
83 KiB
vector_mult_result_m_axi.v
83 KiB
webtalk.jou
830 B
webtalk.log
1.2 KiB
webtalk_7770.backup.jou
830 B
webtalk_7770.backup.log
1.2 KiB
xelab.log
8.2 KiB
xelab.pb
15 KiB
xsim.jou
695 B
xsim.log
1.6 KiB