Report time       : 2018. márc. 19., hétfő, 11.28.07 CET.
Solution          : solution0.
Simulation tool   : xsim.

+----------+----------+-----------------------------------------------+-----------------------------------------------+
|          |          |                    Latency                    |                    Interval                   |
+   RTL    +  Status  +-----------------------------------------------+-----------------------------------------------+
|          |          |      min      |      avg      |      max      |      min      |      avg      |      max      |
+----------+----------+-----------------------------------------------+-----------------------------------------------+
|      VHDL|      Pass|             38|             38|             38|             NA|             NA|             NA|
|   Verilog|        NA|             79|             79|             79|             NA|             NA|             NA|
+----------+----------+-----------------------------------------------+-----------------------------------------------+