================================================================
== Vivado HLS Report for 'vector_mult'
================================================================
* Date:           Mon Mar 19 11:25:20 2018

* Version:        2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017)
* Project:        vector_mult
* Solution:       solution0
* Product family: zynq
* Target device:  xc7z020clg484-1


================================================================
== Performance Estimates
================================================================
+ Timing (ns): 
    * Summary: 
    +--------+-------+----------+------------+
    |  Clock | Target| Estimated| Uncertainty|
    +--------+-------+----------+------------+
    |ap_clk  |  10.00|      8.75|        1.25|
    +--------+-------+----------+------------+

+ Latency (clock cycles): 
    * Summary: 
    +-----+-----+-----+-----+---------+
    |  Latency  |  Interval | Pipeline|
    | min | max | min | max |   Type  |
    +-----+-----+-----+-----+---------+
    |   23|   23|   23|   23|   none  |
    +-----+-----+-----+-----+---------+

    + Detail: 
        * Instance: 
        N/A

        * Loop: 
        +--------------------+-----+-----+----------+-----------+-----------+------+----------+
        |                    |  Latency  | Iteration|  Initiation Interval  | Trip |          |
        |      Loop Name     | min | max |  Latency |  achieved |   target  | Count| Pipelined|
        +--------------------+-----+-----+----------+-----------+-----------+------+----------+
        |- vector_mult_loop  |   10|   10|         4|          1|          1|     8|    yes   |
        +--------------------+-----+-----+----------+-----------+-----------+------+----------+



================================================================
== Utilization Estimates
================================================================
* Summary: 
+-----------------+---------+-------+--------+-------+
|       Name      | BRAM_18K| DSP48E|   FF   |  LUT  |
+-----------------+---------+-------+--------+-------+
|DSP              |        -|      -|       -|      -|
|Expression       |        -|      3|       0|    100|
|FIFO             |        -|      -|       -|      -|
|Instance         |        6|      -|    1686|   1972|
|Memory           |        -|      -|       -|      -|
|Multiplexer      |        -|      -|       -|    188|
|Register         |        0|      -|     277|     32|
+-----------------+---------+-------+--------+-------+
|Total            |        6|      3|    1963|   2292|
+-----------------+---------+-------+--------+-------+
|Available        |      280|    220|  106400|  53200|
+-----------------+---------+-------+--------+-------+
|Utilization (%)  |        2|      1|       1|      4|
+-----------------+---------+-------+--------+-------+

+ Detail: 
    * Instance: 
    +------------------------------+----------------------------+---------+-------+-----+-----+
    |           Instance           |           Module           | BRAM_18K| DSP48E|  FF | LUT |
    +------------------------------+----------------------------+---------+-------+-----+-----+
    |vector_mult_AXILiteS_s_axi_U  |vector_mult_AXILiteS_s_axi  |        0|      0|  150|  232|
    |vector_mult_A_m_axi_U         |vector_mult_A_m_axi         |        2|      0|  512|  580|
    |vector_mult_B_m_axi_U         |vector_mult_B_m_axi         |        2|      0|  512|  580|
    |vector_mult_result_m_axi_U    |vector_mult_result_m_axi    |        2|      0|  512|  580|
    +------------------------------+----------------------------+---------+-------+-----+-----+
    |Total                         |                            |        6|      0| 1686| 1972|
    +------------------------------+----------------------------+---------+-------+-----+-----+

    * DSP48: 
    N/A

    * Memory: 
    N/A

    * FIFO: 
    N/A

    * Expression: 
    +-----------------------------------+----------+-------+---+----+------------+------------+
    |           Variable Name           | Operation| DSP48E| FF| LUT| Bitwidth P0| Bitwidth P1|
    +-----------------------------------+----------+-------+---+----+------------+------------+
    |tmp_1_fu_239_p2                    |     *    |      3|  0|  20|          32|          32|
    |i_1_fu_233_p2                      |     +    |      0|  0|  13|           4|           1|
    |ap_block_pp0_stage0_01001          |    and   |      0|  0|   8|           1|           1|
    |ap_block_state12_io                |    and   |      0|  0|   8|           1|           1|
    |exitcond_fu_227_p2                 |   icmp   |      0|  0|  11|           4|           5|
    |ap_block_pp0_stage0_11001          |    or    |      0|  0|   8|           1|           1|
    |ap_block_state10_pp0_stage0_iter1  |    or    |      0|  0|   8|           1|           1|
    |ap_block_state2_io                 |    or    |      0|  0|   8|           1|           1|
    |ap_enable_pp0                      |    xor   |      0|  0|   8|           1|           2|
    |ap_enable_reg_pp0_iter1            |    xor   |      0|  0|   8|           2|           1|
    +-----------------------------------+----------+-------+---+----+------------+------------+
    |Total                              |          |      3|  0| 100|          48|          46|
    +-----------------------------------+----------+-------+---+----+------------+------------+

    * Multiplexer: 
    +-------------------------------+----+-----------+-----+-----------+
    |              Name             | LUT| Input Size| Bits| Total Bits|
    +-------------------------------+----+-----------+-----+-----------+
    |A_blk_n_AR                     |   9|          2|    1|          2|
    |A_blk_n_R                      |   9|          2|    1|          2|
    |B_blk_n_AR                     |   9|          2|    1|          2|
    |B_blk_n_R                      |   9|          2|    1|          2|
    |ap_NS_fsm                      |  62|         15|    1|         15|
    |ap_enable_reg_pp0_iter1        |   9|          2|    1|          2|
    |ap_enable_reg_pp0_iter3        |   9|          2|    1|          2|
    |ap_sig_ioackin_A_ARREADY       |   9|          2|    1|          2|
    |ap_sig_ioackin_B_ARREADY       |   9|          2|    1|          2|
    |ap_sig_ioackin_result_AWREADY  |   9|          2|    1|          2|
    |ap_sig_ioackin_result_WREADY   |   9|          2|    1|          2|
    |i_reg_156                      |   9|          2|    4|          8|
    |result_blk_n_AW                |   9|          2|    1|          2|
    |result_blk_n_B                 |   9|          2|    1|          2|
    |result_blk_n_W                 |   9|          2|    1|          2|
    +-------------------------------+----+-----------+-----+-----------+
    |Total                          | 188|         43|   18|         49|
    +-------------------------------+----+-----------+-----+-----------+

    * Register: 
    +-------------------------------+----+----+-----+-----------+
    |              Name             | FF | LUT| Bits| Const Bits|
    +-------------------------------+----+----+-----+-----------+
    |A_addr_read_reg_285            |  32|   0|   32|          0|
    |A_offset1_reg_253              |  30|   0|   30|          0|
    |B_addr_read_reg_290            |  32|   0|   32|          0|
    |B_offset3_reg_248              |  30|   0|   30|          0|
    |ap_CS_fsm                      |  14|   0|   14|          0|
    |ap_enable_reg_pp0_iter0        |   1|   0|    1|          0|
    |ap_enable_reg_pp0_iter1        |   1|   0|    1|          0|
    |ap_enable_reg_pp0_iter2        |   1|   0|    1|          0|
    |ap_enable_reg_pp0_iter3        |   1|   0|    1|          0|
    |ap_reg_ioackin_A_ARREADY       |   1|   0|    1|          0|
    |ap_reg_ioackin_B_ARREADY       |   1|   0|    1|          0|
    |ap_reg_ioackin_result_AWREADY  |   1|   0|    1|          0|
    |ap_reg_ioackin_result_WREADY   |   1|   0|    1|          0|
    |exitcond_reg_276               |   1|   0|    1|          0|
    |i_reg_156                      |   4|   0|    4|          0|
    |result_offset5_reg_243         |  30|   0|   30|          0|
    |tmp_1_reg_295                  |  32|   0|   32|          0|
    |exitcond_reg_276               |  64|  32|    1|          0|
    +-------------------------------+----+----+-----+-----------+
    |Total                          | 277|  32|  214|          0|
    +-------------------------------+----+----+-----+-----------+



================================================================
== Interface
================================================================
* Summary: 
+------------------------+-----+-----+------------+--------------+--------------+
|        RTL Ports       | Dir | Bits|  Protocol  | Source Object|    C Type    |
+------------------------+-----+-----+------------+--------------+--------------+
|s_axi_AXILiteS_AWVALID  |  in |    1|    s_axi   |   AXILiteS   |    scalar    |
|s_axi_AXILiteS_AWREADY  | out |    1|    s_axi   |   AXILiteS   |    scalar    |
|s_axi_AXILiteS_AWADDR   |  in |    6|    s_axi   |   AXILiteS   |    scalar    |
|s_axi_AXILiteS_WVALID   |  in |    1|    s_axi   |   AXILiteS   |    scalar    |
|s_axi_AXILiteS_WREADY   | out |    1|    s_axi   |   AXILiteS   |    scalar    |
|s_axi_AXILiteS_WDATA    |  in |   32|    s_axi   |   AXILiteS   |    scalar    |
|s_axi_AXILiteS_WSTRB    |  in |    4|    s_axi   |   AXILiteS   |    scalar    |
|s_axi_AXILiteS_ARVALID  |  in |    1|    s_axi   |   AXILiteS   |    scalar    |
|s_axi_AXILiteS_ARREADY  | out |    1|    s_axi   |   AXILiteS   |    scalar    |
|s_axi_AXILiteS_ARADDR   |  in |    6|    s_axi   |   AXILiteS   |    scalar    |
|s_axi_AXILiteS_RVALID   | out |    1|    s_axi   |   AXILiteS   |    scalar    |
|s_axi_AXILiteS_RREADY   |  in |    1|    s_axi   |   AXILiteS   |    scalar    |
|s_axi_AXILiteS_RDATA    | out |   32|    s_axi   |   AXILiteS   |    scalar    |
|s_axi_AXILiteS_RRESP    | out |    2|    s_axi   |   AXILiteS   |    scalar    |
|s_axi_AXILiteS_BVALID   | out |    1|    s_axi   |   AXILiteS   |    scalar    |
|s_axi_AXILiteS_BREADY   |  in |    1|    s_axi   |   AXILiteS   |    scalar    |
|s_axi_AXILiteS_BRESP    | out |    2|    s_axi   |   AXILiteS   |    scalar    |
|ap_clk                  |  in |    1| ap_ctrl_hs |  vector_mult | return value |
|ap_rst_n                |  in |    1| ap_ctrl_hs |  vector_mult | return value |
|interrupt               | out |    1| ap_ctrl_hs |  vector_mult | return value |
|m_axi_A_AWVALID         | out |    1|    m_axi   |       A      |    pointer   |
|m_axi_A_AWREADY         |  in |    1|    m_axi   |       A      |    pointer   |
|m_axi_A_AWADDR          | out |   32|    m_axi   |       A      |    pointer   |
|m_axi_A_AWID            | out |    1|    m_axi   |       A      |    pointer   |
|m_axi_A_AWLEN           | out |    8|    m_axi   |       A      |    pointer   |
|m_axi_A_AWSIZE          | out |    3|    m_axi   |       A      |    pointer   |
|m_axi_A_AWBURST         | out |    2|    m_axi   |       A      |    pointer   |
|m_axi_A_AWLOCK          | out |    2|    m_axi   |       A      |    pointer   |
|m_axi_A_AWCACHE         | out |    4|    m_axi   |       A      |    pointer   |
|m_axi_A_AWPROT          | out |    3|    m_axi   |       A      |    pointer   |
|m_axi_A_AWQOS           | out |    4|    m_axi   |       A      |    pointer   |
|m_axi_A_AWREGION        | out |    4|    m_axi   |       A      |    pointer   |
|m_axi_A_AWUSER          | out |    1|    m_axi   |       A      |    pointer   |
|m_axi_A_WVALID          | out |    1|    m_axi   |       A      |    pointer   |
|m_axi_A_WREADY          |  in |    1|    m_axi   |       A      |    pointer   |
|m_axi_A_WDATA           | out |   32|    m_axi   |       A      |    pointer   |
|m_axi_A_WSTRB           | out |    4|    m_axi   |       A      |    pointer   |
|m_axi_A_WLAST           | out |    1|    m_axi   |       A      |    pointer   |
|m_axi_A_WID             | out |    1|    m_axi   |       A      |    pointer   |
|m_axi_A_WUSER           | out |    1|    m_axi   |       A      |    pointer   |
|m_axi_A_ARVALID         | out |    1|    m_axi   |       A      |    pointer   |
|m_axi_A_ARREADY         |  in |    1|    m_axi   |       A      |    pointer   |
|m_axi_A_ARADDR          | out |   32|    m_axi   |       A      |    pointer   |
|m_axi_A_ARID            | out |    1|    m_axi   |       A      |    pointer   |
|m_axi_A_ARLEN           | out |    8|    m_axi   |       A      |    pointer   |
|m_axi_A_ARSIZE          | out |    3|    m_axi   |       A      |    pointer   |
|m_axi_A_ARBURST         | out |    2|    m_axi   |       A      |    pointer   |
|m_axi_A_ARLOCK          | out |    2|    m_axi   |       A      |    pointer   |
|m_axi_A_ARCACHE         | out |    4|    m_axi   |       A      |    pointer   |
|m_axi_A_ARPROT          | out |    3|    m_axi   |       A      |    pointer   |
|m_axi_A_ARQOS           | out |    4|    m_axi   |       A      |    pointer   |
|m_axi_A_ARREGION        | out |    4|    m_axi   |       A      |    pointer   |
|m_axi_A_ARUSER          | out |    1|    m_axi   |       A      |    pointer   |
|m_axi_A_RVALID          |  in |    1|    m_axi   |       A      |    pointer   |
|m_axi_A_RREADY          | out |    1|    m_axi   |       A      |    pointer   |
|m_axi_A_RDATA           |  in |   32|    m_axi   |       A      |    pointer   |
|m_axi_A_RLAST           |  in |    1|    m_axi   |       A      |    pointer   |
|m_axi_A_RID             |  in |    1|    m_axi   |       A      |    pointer   |
|m_axi_A_RUSER           |  in |    1|    m_axi   |       A      |    pointer   |
|m_axi_A_RRESP           |  in |    2|    m_axi   |       A      |    pointer   |
|m_axi_A_BVALID          |  in |    1|    m_axi   |       A      |    pointer   |
|m_axi_A_BREADY          | out |    1|    m_axi   |       A      |    pointer   |
|m_axi_A_BRESP           |  in |    2|    m_axi   |       A      |    pointer   |
|m_axi_A_BID             |  in |    1|    m_axi   |       A      |    pointer   |
|m_axi_A_BUSER           |  in |    1|    m_axi   |       A      |    pointer   |
|m_axi_B_AWVALID         | out |    1|    m_axi   |       B      |    pointer   |
|m_axi_B_AWREADY         |  in |    1|    m_axi   |       B      |    pointer   |
|m_axi_B_AWADDR          | out |   32|    m_axi   |       B      |    pointer   |
|m_axi_B_AWID            | out |    1|    m_axi   |       B      |    pointer   |
|m_axi_B_AWLEN           | out |    8|    m_axi   |       B      |    pointer   |
|m_axi_B_AWSIZE          | out |    3|    m_axi   |       B      |    pointer   |
|m_axi_B_AWBURST         | out |    2|    m_axi   |       B      |    pointer   |
|m_axi_B_AWLOCK          | out |    2|    m_axi   |       B      |    pointer   |
|m_axi_B_AWCACHE         | out |    4|    m_axi   |       B      |    pointer   |
|m_axi_B_AWPROT          | out |    3|    m_axi   |       B      |    pointer   |
|m_axi_B_AWQOS           | out |    4|    m_axi   |       B      |    pointer   |
|m_axi_B_AWREGION        | out |    4|    m_axi   |       B      |    pointer   |
|m_axi_B_AWUSER          | out |    1|    m_axi   |       B      |    pointer   |
|m_axi_B_WVALID          | out |    1|    m_axi   |       B      |    pointer   |
|m_axi_B_WREADY          |  in |    1|    m_axi   |       B      |    pointer   |
|m_axi_B_WDATA           | out |   32|    m_axi   |       B      |    pointer   |
|m_axi_B_WSTRB           | out |    4|    m_axi   |       B      |    pointer   |
|m_axi_B_WLAST           | out |    1|    m_axi   |       B      |    pointer   |
|m_axi_B_WID             | out |    1|    m_axi   |       B      |    pointer   |
|m_axi_B_WUSER           | out |    1|    m_axi   |       B      |    pointer   |
|m_axi_B_ARVALID         | out |    1|    m_axi   |       B      |    pointer   |
|m_axi_B_ARREADY         |  in |    1|    m_axi   |       B      |    pointer   |
|m_axi_B_ARADDR          | out |   32|    m_axi   |       B      |    pointer   |
|m_axi_B_ARID            | out |    1|    m_axi   |       B      |    pointer   |
|m_axi_B_ARLEN           | out |    8|    m_axi   |       B      |    pointer   |
|m_axi_B_ARSIZE          | out |    3|    m_axi   |       B      |    pointer   |
|m_axi_B_ARBURST         | out |    2|    m_axi   |       B      |    pointer   |
|m_axi_B_ARLOCK          | out |    2|    m_axi   |       B      |    pointer   |
|m_axi_B_ARCACHE         | out |    4|    m_axi   |       B      |    pointer   |
|m_axi_B_ARPROT          | out |    3|    m_axi   |       B      |    pointer   |
|m_axi_B_ARQOS           | out |    4|    m_axi   |       B      |    pointer   |
|m_axi_B_ARREGION        | out |    4|    m_axi   |       B      |    pointer   |
|m_axi_B_ARUSER          | out |    1|    m_axi   |       B      |    pointer   |
|m_axi_B_RVALID          |  in |    1|    m_axi   |       B      |    pointer   |
|m_axi_B_RREADY          | out |    1|    m_axi   |       B      |    pointer   |
|m_axi_B_RDATA           |  in |   32|    m_axi   |       B      |    pointer   |
|m_axi_B_RLAST           |  in |    1|    m_axi   |       B      |    pointer   |
|m_axi_B_RID             |  in |    1|    m_axi   |       B      |    pointer   |
|m_axi_B_RUSER           |  in |    1|    m_axi   |       B      |    pointer   |
|m_axi_B_RRESP           |  in |    2|    m_axi   |       B      |    pointer   |
|m_axi_B_BVALID          |  in |    1|    m_axi   |       B      |    pointer   |
|m_axi_B_BREADY          | out |    1|    m_axi   |       B      |    pointer   |
|m_axi_B_BRESP           |  in |    2|    m_axi   |       B      |    pointer   |
|m_axi_B_BID             |  in |    1|    m_axi   |       B      |    pointer   |
|m_axi_B_BUSER           |  in |    1|    m_axi   |       B      |    pointer   |
|m_axi_result_AWVALID    | out |    1|    m_axi   |    result    |    pointer   |
|m_axi_result_AWREADY    |  in |    1|    m_axi   |    result    |    pointer   |
|m_axi_result_AWADDR     | out |   32|    m_axi   |    result    |    pointer   |
|m_axi_result_AWID       | out |    1|    m_axi   |    result    |    pointer   |
|m_axi_result_AWLEN      | out |    8|    m_axi   |    result    |    pointer   |
|m_axi_result_AWSIZE     | out |    3|    m_axi   |    result    |    pointer   |
|m_axi_result_AWBURST    | out |    2|    m_axi   |    result    |    pointer   |
|m_axi_result_AWLOCK     | out |    2|    m_axi   |    result    |    pointer   |
|m_axi_result_AWCACHE    | out |    4|    m_axi   |    result    |    pointer   |
|m_axi_result_AWPROT     | out |    3|    m_axi   |    result    |    pointer   |
|m_axi_result_AWQOS      | out |    4|    m_axi   |    result    |    pointer   |
|m_axi_result_AWREGION   | out |    4|    m_axi   |    result    |    pointer   |
|m_axi_result_AWUSER     | out |    1|    m_axi   |    result    |    pointer   |
|m_axi_result_WVALID     | out |    1|    m_axi   |    result    |    pointer   |
|m_axi_result_WREADY     |  in |    1|    m_axi   |    result    |    pointer   |
|m_axi_result_WDATA      | out |   32|    m_axi   |    result    |    pointer   |
|m_axi_result_WSTRB      | out |    4|    m_axi   |    result    |    pointer   |
|m_axi_result_WLAST      | out |    1|    m_axi   |    result    |    pointer   |
|m_axi_result_WID        | out |    1|    m_axi   |    result    |    pointer   |
|m_axi_result_WUSER      | out |    1|    m_axi   |    result    |    pointer   |
|m_axi_result_ARVALID    | out |    1|    m_axi   |    result    |    pointer   |
|m_axi_result_ARREADY    |  in |    1|    m_axi   |    result    |    pointer   |
|m_axi_result_ARADDR     | out |   32|    m_axi   |    result    |    pointer   |
|m_axi_result_ARID       | out |    1|    m_axi   |    result    |    pointer   |
|m_axi_result_ARLEN      | out |    8|    m_axi   |    result    |    pointer   |
|m_axi_result_ARSIZE     | out |    3|    m_axi   |    result    |    pointer   |
|m_axi_result_ARBURST    | out |    2|    m_axi   |    result    |    pointer   |
|m_axi_result_ARLOCK     | out |    2|    m_axi   |    result    |    pointer   |
|m_axi_result_ARCACHE    | out |    4|    m_axi   |    result    |    pointer   |
|m_axi_result_ARPROT     | out |    3|    m_axi   |    result    |    pointer   |
|m_axi_result_ARQOS      | out |    4|    m_axi   |    result    |    pointer   |
|m_axi_result_ARREGION   | out |    4|    m_axi   |    result    |    pointer   |
|m_axi_result_ARUSER     | out |    1|    m_axi   |    result    |    pointer   |
|m_axi_result_RVALID     |  in |    1|    m_axi   |    result    |    pointer   |
|m_axi_result_RREADY     | out |    1|    m_axi   |    result    |    pointer   |
|m_axi_result_RDATA      |  in |   32|    m_axi   |    result    |    pointer   |
|m_axi_result_RLAST      |  in |    1|    m_axi   |    result    |    pointer   |
|m_axi_result_RID        |  in |    1|    m_axi   |    result    |    pointer   |
|m_axi_result_RUSER      |  in |    1|    m_axi   |    result    |    pointer   |
|m_axi_result_RRESP      |  in |    2|    m_axi   |    result    |    pointer   |
|m_axi_result_BVALID     |  in |    1|    m_axi   |    result    |    pointer   |
|m_axi_result_BREADY     | out |    1|    m_axi   |    result    |    pointer   |
|m_axi_result_BRESP      |  in |    2|    m_axi   |    result    |    pointer   |
|m_axi_result_BID        |  in |    1|    m_axi   |    result    |    pointer   |
|m_axi_result_BUSER      |  in |    1|    m_axi   |    result    |    pointer   |
+------------------------+-----+-----+------------+--------------+--------------+

============================================================
+ Verbose Summary: Synthesis Manager
============================================================
InlineROM: 1
ExposeGlobal: 0
============================================================
+ Verbose Summary: CDFG Model
============================================================
IsTopModel: 1
ResetActiveHigh: 1
IsCombinational: 2
IsDatapathOnly: 2
HasWiredReturn: 1
HasMFsm: 0
HasVarLatency: 1
IsPipeline: 0
IsRtlPipelined: 0
IsInstanceOverlapped: 0
IsDontTouch: 0
HasImplIP: 0
IsGatedGlobalClock: 0

+ Individual pipeline summary: 
  * Pipeline-0: initiation interval (II) = 1, depth = 4


============================================================
+ Verbose Summary: Schedule
============================================================
* Number of FSM states : 17
* Pipeline : 1
  Pipeline-0 : II = 1, D = 4, States = { 9 10 11 12 }
* Dataflow Pipeline: 0

* FSM state transitions: 
1 --> 
	2  / true
2 --> 
	3  / true
3 --> 
	4  / true
4 --> 
	5  / true
5 --> 
	6  / true
6 --> 
	7  / true
7 --> 
	8  / true
8 --> 
	9  / true
9 --> 
	13  / (exitcond)
	10  / (!exitcond)
10 --> 
	11  / true
11 --> 
	12  / true
12 --> 
	9  / true
13 --> 
	14  / true
14 --> 
	15  / true
15 --> 
	16  / true
16 --> 
	17  / true
17 --> 

* FSM state operations: 

 <State 1> : 1.00ns
ST_1 : Operation 18 [1/1] (1.00ns)   --->   "%result_offset_read = call i32 @_ssdm_op_Read.s_axilite.i32(i32 %result_offset)"   --->   Core 10 's_axilite' <Latency = 0> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write'>
ST_1 : Operation 19 [1/1] (1.00ns)   --->   "%B_offset_read = call i32 @_ssdm_op_Read.s_axilite.i32(i32 %B_offset)"   --->   Core 10 's_axilite' <Latency = 0> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write'>
ST_1 : Operation 20 [1/1] (1.00ns)   --->   "%A_offset_read = call i32 @_ssdm_op_Read.s_axilite.i32(i32 %A_offset)"   --->   Core 10 's_axilite' <Latency = 0> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write'>
ST_1 : Operation 21 [1/1] (0.00ns)   --->   "%result_offset5 = call i30 @_ssdm_op_PartSelect.i30.i32.i32.i32(i32 %result_offset_read, i32 2, i32 31)"
ST_1 : Operation 22 [1/1] (0.00ns)   --->   "%B_offset3 = call i30 @_ssdm_op_PartSelect.i30.i32.i32.i32(i32 %B_offset_read, i32 2, i32 31)"
ST_1 : Operation 23 [1/1] (0.00ns)   --->   "%A_offset1 = call i30 @_ssdm_op_PartSelect.i30.i32.i32.i32(i32 %A_offset_read, i32 2, i32 31)"

 <State 2> : 8.75ns
ST_2 : Operation 24 [1/1] (0.00ns)   --->   "%tmp_4 = zext i30 %B_offset3 to i64"
ST_2 : Operation 25 [1/1] (0.00ns)   --->   "%B_addr = getelementptr i32* %B, i64 %tmp_4"
ST_2 : Operation 26 [1/1] (0.00ns)   --->   "%tmp_5 = zext i30 %A_offset1 to i64"
ST_2 : Operation 27 [1/1] (0.00ns)   --->   "%A_addr = getelementptr i32* %A, i64 %tmp_5"
ST_2 : Operation 28 [7/7] (8.75ns)   --->   "%A_addr_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %A_addr, i32 8)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_2 : Operation 29 [7/7] (8.75ns)   --->   "%B_addr_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %B_addr, i32 8)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 3> : 8.75ns
ST_3 : Operation 30 [6/7] (8.75ns)   --->   "%A_addr_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %A_addr, i32 8)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_3 : Operation 31 [6/7] (8.75ns)   --->   "%B_addr_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %B_addr, i32 8)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 4> : 8.75ns
ST_4 : Operation 32 [5/7] (8.75ns)   --->   "%A_addr_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %A_addr, i32 8)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_4 : Operation 33 [5/7] (8.75ns)   --->   "%B_addr_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %B_addr, i32 8)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 5> : 8.75ns
ST_5 : Operation 34 [4/7] (8.75ns)   --->   "%A_addr_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %A_addr, i32 8)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_5 : Operation 35 [4/7] (8.75ns)   --->   "%B_addr_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %B_addr, i32 8)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 6> : 8.75ns
ST_6 : Operation 36 [3/7] (8.75ns)   --->   "%A_addr_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %A_addr, i32 8)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_6 : Operation 37 [3/7] (8.75ns)   --->   "%B_addr_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %B_addr, i32 8)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 7> : 8.75ns
ST_7 : Operation 38 [2/7] (8.75ns)   --->   "%A_addr_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %A_addr, i32 8)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_7 : Operation 39 [2/7] (8.75ns)   --->   "%B_addr_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %B_addr, i32 8)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 8> : 8.75ns
ST_8 : Operation 40 [1/1] (0.00ns)   --->   "%tmp_3 = zext i30 %result_offset5 to i64"
ST_8 : Operation 41 [1/1] (0.00ns)   --->   "%result_addr = getelementptr i32* %result, i64 %tmp_3"
ST_8 : Operation 42 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecBitsMap(i32* %result), !map !13"
ST_8 : Operation 43 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecBitsMap(i32* %B), !map !19"
ST_8 : Operation 44 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecBitsMap(i32* %A), !map !23"
ST_8 : Operation 45 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecTopModule([12 x i8]* @vector_mult_str) nounwind"
ST_8 : Operation 46 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(i32 0, [10 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1, [1 x i8]* @p_str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1) nounwind" [vector_mult/vector_mult.cpp:5]
ST_8 : Operation 47 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(i32* %result, [6 x i8]* @p_str2, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [7 x i8]* @p_str3, [6 x i8]* @p_str4, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)"
ST_8 : Operation 48 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(i32 %result_offset, [10 x i8]* @mode5, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @bundle6, [6 x i8]* @p_str4, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)"
ST_8 : Operation 49 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(i32* %B, [6 x i8]* @p_str2, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [2 x i8]* @p_str5, [6 x i8]* @p_str4, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)"
ST_8 : Operation 50 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(i32 %B_offset, [10 x i8]* @mode3, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @bundle4, [6 x i8]* @p_str4, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)"
ST_8 : Operation 51 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(i32* %A, [6 x i8]* @p_str2, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [2 x i8]* @p_str6, [6 x i8]* @p_str4, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)"
ST_8 : Operation 52 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(i32 %A_offset, [10 x i8]* @mode, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 32, [1 x i8]* @bundle, [6 x i8]* @p_str4, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)"
ST_8 : Operation 53 [1/7] (8.75ns)   --->   "%A_addr_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %A_addr, i32 8)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_8 : Operation 54 [1/7] (8.75ns)   --->   "%B_addr_rd_req = call i1 @_ssdm_op_ReadReq.m_axi.i32P(i32* %B_addr, i32 8)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_8 : Operation 55 [1/1] (8.75ns)   --->   "%result_addr_wr_req = call i1 @_ssdm_op_WriteReq.m_axi.i32P(i32* %result_addr, i32 8)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_8 : Operation 56 [1/1] (1.76ns)   --->   "br label %1" [vector_mult/vector_mult.cpp:8]

 <State 9> : 1.74ns
ST_9 : Operation 57 [1/1] (0.00ns)   --->   "%i = phi i4 [ 0, %0 ], [ %i_1, %2 ]"
ST_9 : Operation 58 [1/1] (1.30ns)   --->   "%exitcond = icmp eq i4 %i, -8" [vector_mult/vector_mult.cpp:8]   --->   Core 25 'Cmp' <Latency = 0> <II = 1> <Delay = 1.36> <FuncUnit> <Opcode : 'icmp'> <InPorts = 2> <OutPorts = 1>
ST_9 : Operation 59 [1/1] (1.73ns)   --->   "%i_1 = add i4 %i, 1" [vector_mult/vector_mult.cpp:8]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 1.73> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_9 : Operation 60 [1/1] (0.00ns)   --->   "br i1 %exitcond, label %3, label %2" [vector_mult/vector_mult.cpp:8]

 <State 10> : 8.75ns
ST_10 : Operation 61 [1/1] (8.75ns)   --->   "%A_addr_read = call i32 @_ssdm_op_Read.m_axi.i32P(i32* %A_addr)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_10 : Operation 62 [1/1] (8.75ns)   --->   "%B_addr_read = call i32 @_ssdm_op_Read.m_axi.i32P(i32* %B_addr)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 11> : 8.51ns
ST_11 : Operation 63 [1/1] (8.51ns)   --->   "%tmp_1 = mul nsw i32 %A_addr_read, %B_addr_read" [vector_mult/vector_mult.cpp:9]   --->   Core 16 'Mul' <Latency = 0> <II = 1> <Delay = 8.51> <FuncUnit> <Opcode : 'mul'> <InPorts = 2> <OutPorts = 1>

 <State 12> : 8.75ns
ST_12 : Operation 64 [1/1] (0.00ns)   --->   "%empty = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 8, i64 8, i64 8) nounwind"
ST_12 : Operation 65 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecLoopName([17 x i8]* @p_str7) nounwind" [vector_mult/vector_mult.cpp:9]
ST_12 : Operation 66 [1/1] (0.00ns)   --->   "%tmp_2 = call i32 (...)* @_ssdm_op_SpecRegionBegin([17 x i8]* @p_str7) nounwind" [vector_mult/vector_mult.cpp:9]
ST_12 : Operation 67 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind" [vector_mult/vector_mult.cpp:10]
ST_12 : Operation 68 [1/1] (8.75ns)   --->   "call void @_ssdm_op_Write.m_axi.i32P(i32* %result_addr, i32 %tmp_1, i4 -1)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_12 : Operation 69 [1/1] (0.00ns)   --->   "%empty_4 = call i32 (...)* @_ssdm_op_SpecRegionEnd([17 x i8]* @p_str7, i32 %tmp_2) nounwind" [vector_mult/vector_mult.cpp:9]
ST_12 : Operation 70 [1/1] (0.00ns)   --->   "br label %1" [vector_mult/vector_mult.cpp:8]

 <State 13> : 8.75ns
ST_13 : Operation 71 [5/5] (8.75ns)   --->   "%result_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %result_addr)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 14> : 8.75ns
ST_14 : Operation 72 [4/5] (8.75ns)   --->   "%result_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %result_addr)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 15> : 8.75ns
ST_15 : Operation 73 [3/5] (8.75ns)   --->   "%result_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %result_addr)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 16> : 8.75ns
ST_16 : Operation 74 [2/5] (8.75ns)   --->   "%result_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %result_addr)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 17> : 8.75ns
ST_17 : Operation 75 [1/5] (8.75ns)   --->   "%result_addr_wr_resp = call i1 @_ssdm_op_WriteResp.m_axi.i32P(i32* %result_addr)" [vector_mult/vector_mult.cpp:9]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_17 : Operation 76 [1/1] (0.00ns)   --->   "ret void" [vector_mult/vector_mult.cpp:12]


============================================================
+ Verbose Summary: Binding
============================================================
STG Binding: 
---------------- STG Properties BEGIN ----------------
- Is combinational: 0
- Is one-state seq: 0
- Is datapath-only: 0
- Is pipelined: 0
- Is top level: 1
Port [ Return ] is wired: 1; IO mode=ap_ctrl_hs:ce=0
Port [ A]:  wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=4; pingpong=0; private_global=0; IO mode=m_axi:ce=0
Port [ B]:  wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=4; pingpong=0; private_global=0; IO mode=m_axi:ce=0
Port [ result]:  wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=1; type=4; pingpong=0; private_global=0; IO mode=m_axi:ce=0
Port [ A_offset]:  wired=1; compound=0; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=0; pingpong=0; private_global=0; IO mode=ap_none:ce=0
Port [ B_offset]:  wired=1; compound=0; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=0; pingpong=0; private_global=0; IO mode=ap_none:ce=0
Port [ result_offset]:  wired=1; compound=0; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=0; pingpong=0; private_global=0; IO mode=ap_none:ce=0
---------------- STG Properties END ------------------

---------------- Datapath Model BEGIN ----------------

<LifeTime>
<method=bitvector/>
result_offset_read  (read             ) [ 000000000000000000]
B_offset_read       (read             ) [ 000000000000000000]
A_offset_read       (read             ) [ 000000000000000000]
result_offset5      (partselect       ) [ 001111111000000000]
B_offset3           (partselect       ) [ 001000000000000000]
A_offset1           (partselect       ) [ 001000000000000000]
tmp_4               (zext             ) [ 000000000000000000]
B_addr              (getelementptr    ) [ 000111111111100000]
tmp_5               (zext             ) [ 000000000000000000]
A_addr              (getelementptr    ) [ 000111111111100000]
tmp_3               (zext             ) [ 000000000000000000]
result_addr         (getelementptr    ) [ 000000000111111111]
StgValue_42         (specbitsmap      ) [ 000000000000000000]
StgValue_43         (specbitsmap      ) [ 000000000000000000]
StgValue_44         (specbitsmap      ) [ 000000000000000000]
StgValue_45         (spectopmodule    ) [ 000000000000000000]
StgValue_46         (specinterface    ) [ 000000000000000000]
StgValue_47         (specinterface    ) [ 000000000000000000]
StgValue_48         (specinterface    ) [ 000000000000000000]
StgValue_49         (specinterface    ) [ 000000000000000000]
StgValue_50         (specinterface    ) [ 000000000000000000]
StgValue_51         (specinterface    ) [ 000000000000000000]
StgValue_52         (specinterface    ) [ 000000000000000000]
A_addr_rd_req       (readreq          ) [ 000000000000000000]
B_addr_rd_req       (readreq          ) [ 000000000000000000]
result_addr_wr_req  (writereq         ) [ 000000000000000000]
StgValue_56         (br               ) [ 000000001111100000]
i                   (phi              ) [ 000000000100000000]
exitcond            (icmp             ) [ 000000000111100000]
i_1                 (add              ) [ 000000001111100000]
StgValue_60         (br               ) [ 000000000000000000]
A_addr_read         (read             ) [ 000000000101000000]
B_addr_read         (read             ) [ 000000000101000000]
tmp_1               (mul              ) [ 000000000100100000]
empty               (speclooptripcount) [ 000000000000000000]
StgValue_65         (specloopname     ) [ 000000000000000000]
tmp_2               (specregionbegin  ) [ 000000000000000000]
StgValue_67         (specpipeline     ) [ 000000000000000000]
StgValue_68         (write            ) [ 000000000000000000]
empty_4             (specregionend    ) [ 000000000000000000]
StgValue_70         (br               ) [ 000000001111100000]
result_addr_wr_resp (writeresp        ) [ 000000000000000000]
StgValue_76         (ret              ) [ 000000000000000000]
</LifeTime>

<model>

<comp_list>
<comp id="0" class="1000" name="A">
<pin_list>
<pin id="1" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="A"/></StgValue>
</bind>
</comp>

<comp id="2" class="1000" name="B">
<pin_list>
<pin id="3" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="B"/></StgValue>
</bind>
</comp>

<comp id="4" class="1000" name="result">
<pin_list>
<pin id="5" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="result"/></StgValue>
</bind>
</comp>

<comp id="6" class="1000" name="A_offset">
<pin_list>
<pin id="7" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="A_offset"/></StgValue>
</bind>
</comp>

<comp id="8" class="1000" name="B_offset">
<pin_list>
<pin id="9" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="B_offset"/></StgValue>
</bind>
</comp>

<comp id="10" class="1000" name="result_offset">
<pin_list>
<pin id="11" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="result_offset"/></StgValue>
</bind>
</comp>

<comp id="12" class="1001" name="const_12">
<pin_list>
<pin id="13" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_Read.s_axilite.i32"/></StgValue>
</bind>
</comp>

<comp id="14" class="1001" name="const_14">
<pin_list>
<pin id="15" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_PartSelect.i30.i32.i32.i32"/></StgValue>
</bind>
</comp>

<comp id="16" class="1001" name="const_16">
<pin_list>
<pin id="17" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="18" class="1001" name="const_18">
<pin_list>
<pin id="19" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="20" class="1001" name="const_20">
<pin_list>
<pin id="21" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_ReadReq.m_axi.i32P"/></StgValue>
</bind>
</comp>

<comp id="22" class="1001" name="const_22">
<pin_list>
<pin id="23" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="24" class="1001" name="const_24">
<pin_list>
<pin id="25" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecBitsMap"/></StgValue>
</bind>
</comp>

<comp id="26" class="1001" name="const_26">
<pin_list>
<pin id="27" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecTopModule"/></StgValue>
</bind>
</comp>

<comp id="28" class="1001" name="const_28">
<pin_list>
<pin id="29" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="vector_mult_str"/></StgValue>
</bind>
</comp>

<comp id="30" class="1001" name="const_30">
<pin_list>
<pin id="31" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecInterface"/></StgValue>
</bind>
</comp>

<comp id="32" class="1001" name="const_32">
<pin_list>
<pin id="33" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="34" class="1001" name="const_34">
<pin_list>
<pin id="35" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str"/></StgValue>
</bind>
</comp>

<comp id="36" class="1001" name="const_36">
<pin_list>
<pin id="37" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str1"/></StgValue>
</bind>
</comp>

<comp id="38" class="1001" name="const_38">
<pin_list>
<pin id="39" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str2"/></StgValue>
</bind>
</comp>

<comp id="40" class="1001" name="const_40">
<pin_list>
<pin id="41" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="42" class="1001" name="const_42">
<pin_list>
<pin id="43" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str3"/></StgValue>
</bind>
</comp>

<comp id="44" class="1001" name="const_44">
<pin_list>
<pin id="45" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str4"/></StgValue>
</bind>
</comp>

<comp id="46" class="1001" name="const_46">
<pin_list>
<pin id="47" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="48" class="1001" name="const_48">
<pin_list>
<pin id="49" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="mode5"/></StgValue>
</bind>
</comp>

<comp id="50" class="1001" name="const_50">
<pin_list>
<pin id="51" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="bundle6"/></StgValue>
</bind>
</comp>

<comp id="52" class="1001" name="const_52">
<pin_list>
<pin id="53" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str5"/></StgValue>
</bind>
</comp>

<comp id="54" class="1001" name="const_54">
<pin_list>
<pin id="55" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="mode3"/></StgValue>
</bind>
</comp>

<comp id="56" class="1001" name="const_56">
<pin_list>
<pin id="57" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="bundle4"/></StgValue>
</bind>
</comp>

<comp id="58" class="1001" name="const_58">
<pin_list>
<pin id="59" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str6"/></StgValue>
</bind>
</comp>

<comp id="60" class="1001" name="const_60">
<pin_list>
<pin id="61" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="mode"/></StgValue>
</bind>
</comp>

<comp id="62" class="1001" name="const_62">
<pin_list>
<pin id="63" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="bundle"/></StgValue>
</bind>
</comp>

<comp id="64" class="1001" name="const_64">
<pin_list>
<pin id="65" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_WriteReq.m_axi.i32P"/></StgValue>
</bind>
</comp>

<comp id="66" class="1001" name="const_66">
<pin_list>
<pin id="67" dir="1" index="0" bw="1" slack="1"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="68" class="1001" name="const_68">
<pin_list>
<pin id="69" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="70" class="1001" name="const_70">
<pin_list>
<pin id="71" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="72" class="1001" name="const_72">
<pin_list>
<pin id="73" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_Read.m_axi.i32P"/></StgValue>
</bind>
</comp>

<comp id="74" class="1001" name="const_74">
<pin_list>
<pin id="75" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecLoopTripCount"/></StgValue>
</bind>
</comp>

<comp id="76" class="1001" name="const_76">
<pin_list>
<pin id="77" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="78" class="1001" name="const_78">
<pin_list>
<pin id="79" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecLoopName"/></StgValue>
</bind>
</comp>

<comp id="80" class="1001" name="const_80">
<pin_list>
<pin id="81" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str7"/></StgValue>
</bind>
</comp>

<comp id="82" class="1001" name="const_82">
<pin_list>
<pin id="83" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecRegionBegin"/></StgValue>
</bind>
</comp>

<comp id="84" class="1001" name="const_84">
<pin_list>
<pin id="85" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecPipeline"/></StgValue>
</bind>
</comp>

<comp id="86" class="1001" name="const_86">
<pin_list>
<pin id="87" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="88" class="1001" name="const_88">
<pin_list>
<pin id="89" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="90" class="1001" name="const_90">
<pin_list>
<pin id="91" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_Write.m_axi.i32P"/></StgValue>
</bind>
</comp>

<comp id="92" class="1001" name="const_92">
<pin_list>
<pin id="93" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="94" class="1001" name="const_94">
<pin_list>
<pin id="95" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecRegionEnd"/></StgValue>
</bind>
</comp>

<comp id="96" class="1001" name="const_96">
<pin_list>
<pin id="97" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_WriteResp.m_axi.i32P"/></StgValue>
</bind>
</comp>

<comp id="98" class="1004" name="result_offset_read_read_fu_98">
<pin_list>
<pin id="99" dir="0" index="0" bw="32" slack="0"/>
<pin id="100" dir="0" index="1" bw="32" slack="0"/>
<pin id="101" dir="1" index="2" bw="32" slack="0"/>
</pin_list>
<bind>
<opcode="read(1150) " fcode="read"/>
<opset="result_offset_read/1 "/>
</bind>
</comp>

<comp id="104" class="1004" name="B_offset_read_read_fu_104">
<pin_list>
<pin id="105" dir="0" index="0" bw="32" slack="0"/>
<pin id="106" dir="0" index="1" bw="32" slack="0"/>
<pin id="107" dir="1" index="2" bw="32" slack="0"/>
</pin_list>
<bind>
<opcode="read(1150) " fcode="read"/>
<opset="B_offset_read/1 "/>
</bind>
</comp>

<comp id="110" class="1004" name="A_offset_read_read_fu_110">
<pin_list>
<pin id="111" dir="0" index="0" bw="32" slack="0"/>
<pin id="112" dir="0" index="1" bw="32" slack="0"/>
<pin id="113" dir="1" index="2" bw="32" slack="0"/>
</pin_list>
<bind>
<opcode="read(1150) " fcode="read"/>
<opset="A_offset_read/1 "/>
</bind>
</comp>

<comp id="116" class="1004" name="grp_readreq_fu_116">
<pin_list>
<pin id="117" dir="0" index="0" bw="1" slack="0"/>
<pin id="118" dir="0" index="1" bw="32" slack="0"/>
<pin id="119" dir="0" index="2" bw="5" slack="0"/>
<pin id="120" dir="1" index="3" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<opcode="readreq(1154) " fcode="readreq"/>
<opset="A_addr_rd_req/2 "/>
</bind>
</comp>

<comp id="123" class="1004" name="grp_readreq_fu_123">
<pin_list>
<pin id="124" dir="0" index="0" bw="1" slack="0"/>
<pin id="125" dir="0" index="1" bw="32" slack="0"/>
<pin id="126" dir="0" index="2" bw="5" slack="0"/>
<pin id="127" dir="1" index="3" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<opcode="readreq(1154) " fcode="readreq"/>
<opset="B_addr_rd_req/2 "/>
</bind>
</comp>

<comp id="130" class="1004" name="grp_writeresp_fu_130">
<pin_list>
<pin id="131" dir="0" index="0" bw="1" slack="0"/>
<pin id="132" dir="0" index="1" bw="32" slack="0"/>
<pin id="133" dir="0" index="2" bw="5" slack="0"/>
<pin id="134" dir="1" index="3" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<opcode="writereq(1155) writeresp(1158) " fcode="writeresp"/>
<opset="result_addr_wr_req/8 result_addr_wr_resp/13 "/>
</bind>
</comp>

<comp id="137" class="1004" name="A_addr_read_read_fu_137">
<pin_list>
<pin id="138" dir="0" index="0" bw="32" slack="0"/>
<pin id="139" dir="0" index="1" bw="32" slack="8"/>
<pin id="140" dir="1" index="2" bw="32" slack="1"/>
</pin_list>
<bind>
<opcode="read(1150) " fcode="read"/>
<opset="A_addr_read/10 "/>
</bind>
</comp>

<comp id="142" class="1004" name="B_addr_read_read_fu_142">
<pin_list>
<pin id="143" dir="0" index="0" bw="32" slack="0"/>
<pin id="144" dir="0" index="1" bw="32" slack="8"/>
<pin id="145" dir="1" index="2" bw="32" slack="1"/>
</pin_list>
<bind>
<opcode="read(1150) " fcode="read"/>
<opset="B_addr_read/10 "/>
</bind>
</comp>

<comp id="147" class="1004" name="StgValue_68_write_fu_147">
<pin_list>
<pin id="148" dir="0" index="0" bw="0" slack="0"/>
<pin id="149" dir="0" index="1" bw="32" slack="4"/>
<pin id="150" dir="0" index="2" bw="32" slack="1"/>
<pin id="151" dir="0" index="3" bw="1" slack="0"/>
<pin id="152" dir="1" index="4" bw="0" slack="2147483647"/>
</pin_list>
<bind>
<opcode="write(1151) " fcode="write"/>
<opset="StgValue_68/12 "/>
</bind>
</comp>

<comp id="156" class="1005" name="i_reg_156">
<pin_list>
<pin id="157" dir="0" index="0" bw="4" slack="1"/>
<pin id="158" dir="1" index="1" bw="4" slack="1"/>
</pin_list>
<bind>
<opset="i (phireg) "/>
</bind>
</comp>

<comp id="160" class="1004" name="i_phi_fu_160">
<pin_list>
<pin id="161" dir="0" index="0" bw="1" slack="1"/>
<pin id="162" dir="0" index="1" bw="0" slack="2147483647"/>
<pin id="163" dir="0" index="2" bw="4" slack="0"/>
<pin id="164" dir="0" index="3" bw="0" slack="2147483647"/>
<pin id="165" dir="1" index="4" bw="4" slack="0"/>
</pin_list>
<bind>
<opcode="phi(47) " fcode="phi"/>
<opset="i/9 "/>
</bind>
</comp>

<comp id="167" class="1004" name="result_offset5_fu_167">
<pin_list>
<pin id="168" dir="0" index="0" bw="30" slack="0"/>
<pin id="169" dir="0" index="1" bw="32" slack="0"/>
<pin id="170" dir="0" index="2" bw="3" slack="0"/>
<pin id="171" dir="0" index="3" bw="6" slack="0"/>
<pin id="172" dir="1" index="4" bw="30" slack="7"/>
</pin_list>
<bind>
<opcode="partselect(1002) " fcode="partselect"/>
<opset="result_offset5/1 "/>
</bind>
</comp>

<comp id="177" class="1004" name="B_offset3_fu_177">
<pin_list>
<pin id="178" dir="0" index="0" bw="30" slack="0"/>
<pin id="179" dir="0" index="1" bw="32" slack="0"/>
<pin id="180" dir="0" index="2" bw="3" slack="0"/>
<pin id="181" dir="0" index="3" bw="6" slack="0"/>
<pin id="182" dir="1" index="4" bw="30" slack="1"/>
</pin_list>
<bind>
<opcode="partselect(1002) " fcode="partselect"/>
<opset="B_offset3/1 "/>
</bind>
</comp>

<comp id="187" class="1004" name="A_offset1_fu_187">
<pin_list>
<pin id="188" dir="0" index="0" bw="30" slack="0"/>
<pin id="189" dir="0" index="1" bw="32" slack="0"/>
<pin id="190" dir="0" index="2" bw="3" slack="0"/>
<pin id="191" dir="0" index="3" bw="6" slack="0"/>
<pin id="192" dir="1" index="4" bw="30" slack="1"/>
</pin_list>
<bind>
<opcode="partselect(1002) " fcode="partselect"/>
<opset="A_offset1/1 "/>
</bind>
</comp>

<comp id="197" class="1004" name="tmp_4_fu_197">
<pin_list>
<pin id="198" dir="0" index="0" bw="30" slack="1"/>
<pin id="199" dir="1" index="1" bw="64" slack="0"/>
</pin_list>
<bind>
<opcode="zext(34) " fcode="zext"/>
<opset="tmp_4/2 "/>
</bind>
</comp>

<comp id="200" class="1004" name="B_addr_fu_200">
<pin_list>
<pin id="201" dir="0" index="0" bw="32" slack="0"/>
<pin id="202" dir="0" index="1" bw="32" slack="0"/>
<pin id="203" dir="1" index="2" bw="32" slack="0"/>
</pin_list>
<bind>
<opcode="getelementptr(29) " fcode="getelementptr"/>
<opset="B_addr/2 "/>
</bind>
</comp>

<comp id="207" class="1004" name="tmp_5_fu_207">
<pin_list>
<pin id="208" dir="0" index="0" bw="30" slack="1"/>
<pin id="209" dir="1" index="1" bw="64" slack="0"/>
</pin_list>
<bind>
<opcode="zext(34) " fcode="zext"/>
<opset="tmp_5/2 "/>
</bind>
</comp>

<comp id="210" class="1004" name="A_addr_fu_210">
<pin_list>
<pin id="211" dir="0" index="0" bw="32" slack="0"/>
<pin id="212" dir="0" index="1" bw="32" slack="0"/>
<pin id="213" dir="1" index="2" bw="32" slack="0"/>
</pin_list>
<bind>
<opcode="getelementptr(29) " fcode="getelementptr"/>
<opset="A_addr/2 "/>
</bind>
</comp>

<comp id="217" class="1004" name="tmp_3_fu_217">
<pin_list>
<pin id="218" dir="0" index="0" bw="30" slack="7"/>
<pin id="219" dir="1" index="1" bw="64" slack="0"/>
</pin_list>
<bind>
<opcode="zext(34) " fcode="zext"/>
<opset="tmp_3/8 "/>
</bind>
</comp>

<comp id="220" class="1004" name="result_addr_fu_220">
<pin_list>
<pin id="221" dir="0" index="0" bw="32" slack="0"/>
<pin id="222" dir="0" index="1" bw="32" slack="0"/>
<pin id="223" dir="1" index="2" bw="32" slack="0"/>
</pin_list>
<bind>
<opcode="getelementptr(29) " fcode="getelementptr"/>
<opset="result_addr/8 "/>
</bind>
</comp>

<comp id="227" class="1004" name="exitcond_fu_227">
<pin_list>
<pin id="228" dir="0" index="0" bw="4" slack="0"/>
<pin id="229" dir="0" index="1" bw="4" slack="0"/>
<pin id="230" dir="1" index="2" bw="1" slack="1"/>
</pin_list>
<bind>
<opcode="icmp(45) " fcode="icmp"/>
<opset="exitcond/9 "/>
</bind>
</comp>

<comp id="233" class="1004" name="i_1_fu_233">
<pin_list>
<pin id="234" dir="0" index="0" bw="4" slack="0"/>
<pin id="235" dir="0" index="1" bw="1" slack="0"/>
<pin id="236" dir="1" index="2" bw="4" slack="0"/>
</pin_list>
<bind>
<opcode="add(8) " fcode="add"/>
<opset="i_1/9 "/>
</bind>
</comp>

<comp id="239" class="1004" name="tmp_1_fu_239">
<pin_list>
<pin id="240" dir="0" index="0" bw="32" slack="1"/>
<pin id="241" dir="0" index="1" bw="32" slack="1"/>
<pin id="242" dir="1" index="2" bw="32" slack="1"/>
</pin_list>
<bind>
<opcode="mul(12) " fcode="mul"/>
<opset="tmp_1/11 "/>
</bind>
</comp>

<comp id="243" class="1005" name="result_offset5_reg_243">
<pin_list>
<pin id="244" dir="0" index="0" bw="30" slack="7"/>
<pin id="245" dir="1" index="1" bw="30" slack="7"/>
</pin_list>
<bind>
<opset="result_offset5 "/>
</bind>
</comp>

<comp id="248" class="1005" name="B_offset3_reg_248">
<pin_list>
<pin id="249" dir="0" index="0" bw="30" slack="1"/>
<pin id="250" dir="1" index="1" bw="30" slack="1"/>
</pin_list>
<bind>
<opset="B_offset3 "/>
</bind>
</comp>

<comp id="253" class="1005" name="A_offset1_reg_253">
<pin_list>
<pin id="254" dir="0" index="0" bw="30" slack="1"/>
<pin id="255" dir="1" index="1" bw="30" slack="1"/>
</pin_list>
<bind>
<opset="A_offset1 "/>
</bind>
</comp>

<comp id="258" class="1005" name="B_addr_reg_258">
<pin_list>
<pin id="259" dir="0" index="0" bw="32" slack="1"/>
<pin id="260" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="B_addr "/>
</bind>
</comp>

<comp id="264" class="1005" name="A_addr_reg_264">
<pin_list>
<pin id="265" dir="0" index="0" bw="32" slack="1"/>
<pin id="266" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="A_addr "/>
</bind>
</comp>

<comp id="270" class="1005" name="result_addr_reg_270">
<pin_list>
<pin id="271" dir="0" index="0" bw="32" slack="2"/>
<pin id="272" dir="1" index="1" bw="32" slack="2"/>
</pin_list>
<bind>
<opset="result_addr "/>
</bind>
</comp>

<comp id="276" class="1005" name="exitcond_reg_276">
<pin_list>
<pin id="277" dir="0" index="0" bw="1" slack="1"/>
<pin id="278" dir="1" index="1" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<opset="exitcond "/>
</bind>
</comp>

<comp id="280" class="1005" name="i_1_reg_280">
<pin_list>
<pin id="281" dir="0" index="0" bw="4" slack="0"/>
<pin id="282" dir="1" index="1" bw="4" slack="0"/>
</pin_list>
<bind>
<opset="i_1 "/>
</bind>
</comp>

<comp id="285" class="1005" name="A_addr_read_reg_285">
<pin_list>
<pin id="286" dir="0" index="0" bw="32" slack="1"/>
<pin id="287" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="A_addr_read "/>
</bind>
</comp>

<comp id="290" class="1005" name="B_addr_read_reg_290">
<pin_list>
<pin id="291" dir="0" index="0" bw="32" slack="1"/>
<pin id="292" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="B_addr_read "/>
</bind>
</comp>

<comp id="295" class="1005" name="tmp_1_reg_295">
<pin_list>
<pin id="296" dir="0" index="0" bw="32" slack="1"/>
<pin id="297" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="tmp_1 "/>
</bind>
</comp>

</comp_list>

<net_list>
<net id="102"><net_src comp="12" pin="0"/><net_sink comp="98" pin=0"/></net>

<net id="103"><net_src comp="10" pin="0"/><net_sink comp="98" pin=1"/></net>

<net id="108"><net_src comp="12" pin="0"/><net_sink comp="104" pin=0"/></net>

<net id="109"><net_src comp="8" pin="0"/><net_sink comp="104" pin=1"/></net>

<net id="114"><net_src comp="12" pin="0"/><net_sink comp="110" pin=0"/></net>

<net id="115"><net_src comp="6" pin="0"/><net_sink comp="110" pin=1"/></net>

<net id="121"><net_src comp="20" pin="0"/><net_sink comp="116" pin=0"/></net>

<net id="122"><net_src comp="22" pin="0"/><net_sink comp="116" pin=2"/></net>

<net id="128"><net_src comp="20" pin="0"/><net_sink comp="123" pin=0"/></net>

<net id="129"><net_src comp="22" pin="0"/><net_sink comp="123" pin=2"/></net>

<net id="135"><net_src comp="64" pin="0"/><net_sink comp="130" pin=0"/></net>

<net id="136"><net_src comp="22" pin="0"/><net_sink comp="130" pin=2"/></net>

<net id="141"><net_src comp="72" pin="0"/><net_sink comp="137" pin=0"/></net>

<net id="146"><net_src comp="72" pin="0"/><net_sink comp="142" pin=0"/></net>

<net id="153"><net_src comp="90" pin="0"/><net_sink comp="147" pin=0"/></net>

<net id="154"><net_src comp="92" pin="0"/><net_sink comp="147" pin=3"/></net>

<net id="155"><net_src comp="96" pin="0"/><net_sink comp="130" pin=0"/></net>

<net id="159"><net_src comp="66" pin="0"/><net_sink comp="156" pin=0"/></net>

<net id="166"><net_src comp="156" pin="1"/><net_sink comp="160" pin=0"/></net>

<net id="173"><net_src comp="14" pin="0"/><net_sink comp="167" pin=0"/></net>

<net id="174"><net_src comp="98" pin="2"/><net_sink comp="167" pin=1"/></net>

<net id="175"><net_src comp="16" pin="0"/><net_sink comp="167" pin=2"/></net>

<net id="176"><net_src comp="18" pin="0"/><net_sink comp="167" pin=3"/></net>

<net id="183"><net_src comp="14" pin="0"/><net_sink comp="177" pin=0"/></net>

<net id="184"><net_src comp="104" pin="2"/><net_sink comp="177" pin=1"/></net>

<net id="185"><net_src comp="16" pin="0"/><net_sink comp="177" pin=2"/></net>

<net id="186"><net_src comp="18" pin="0"/><net_sink comp="177" pin=3"/></net>

<net id="193"><net_src comp="14" pin="0"/><net_sink comp="187" pin=0"/></net>

<net id="194"><net_src comp="110" pin="2"/><net_sink comp="187" pin=1"/></net>

<net id="195"><net_src comp="16" pin="0"/><net_sink comp="187" pin=2"/></net>

<net id="196"><net_src comp="18" pin="0"/><net_sink comp="187" pin=3"/></net>

<net id="204"><net_src comp="2" pin="0"/><net_sink comp="200" pin=0"/></net>

<net id="205"><net_src comp="197" pin="1"/><net_sink comp="200" pin=1"/></net>

<net id="206"><net_src comp="200" pin="2"/><net_sink comp="123" pin=1"/></net>

<net id="214"><net_src comp="0" pin="0"/><net_sink comp="210" pin=0"/></net>

<net id="215"><net_src comp="207" pin="1"/><net_sink comp="210" pin=1"/></net>

<net id="216"><net_src comp="210" pin="2"/><net_sink comp="116" pin=1"/></net>

<net id="224"><net_src comp="4" pin="0"/><net_sink comp="220" pin=0"/></net>

<net id="225"><net_src comp="217" pin="1"/><net_sink comp="220" pin=1"/></net>

<net id="226"><net_src comp="220" pin="2"/><net_sink comp="130" pin=1"/></net>

<net id="231"><net_src comp="160" pin="4"/><net_sink comp="227" pin=0"/></net>

<net id="232"><net_src comp="68" pin="0"/><net_sink comp="227" pin=1"/></net>

<net id="237"><net_src comp="160" pin="4"/><net_sink comp="233" pin=0"/></net>

<net id="238"><net_src comp="70" pin="0"/><net_sink comp="233" pin=1"/></net>

<net id="246"><net_src comp="167" pin="4"/><net_sink comp="243" pin=0"/></net>

<net id="247"><net_src comp="243" pin="1"/><net_sink comp="217" pin=0"/></net>

<net id="251"><net_src comp="177" pin="4"/><net_sink comp="248" pin=0"/></net>

<net id="252"><net_src comp="248" pin="1"/><net_sink comp="197" pin=0"/></net>

<net id="256"><net_src comp="187" pin="4"/><net_sink comp="253" pin=0"/></net>

<net id="257"><net_src comp="253" pin="1"/><net_sink comp="207" pin=0"/></net>

<net id="261"><net_src comp="200" pin="2"/><net_sink comp="258" pin=0"/></net>

<net id="262"><net_src comp="258" pin="1"/><net_sink comp="123" pin=1"/></net>

<net id="263"><net_src comp="258" pin="1"/><net_sink comp="142" pin=1"/></net>

<net id="267"><net_src comp="210" pin="2"/><net_sink comp="264" pin=0"/></net>

<net id="268"><net_src comp="264" pin="1"/><net_sink comp="116" pin=1"/></net>

<net id="269"><net_src comp="264" pin="1"/><net_sink comp="137" pin=1"/></net>

<net id="273"><net_src comp="220" pin="2"/><net_sink comp="270" pin=0"/></net>

<net id="274"><net_src comp="270" pin="1"/><net_sink comp="147" pin=1"/></net>

<net id="275"><net_src comp="270" pin="1"/><net_sink comp="130" pin=1"/></net>

<net id="279"><net_src comp="227" pin="2"/><net_sink comp="276" pin=0"/></net>

<net id="283"><net_src comp="233" pin="2"/><net_sink comp="280" pin=0"/></net>

<net id="284"><net_src comp="280" pin="1"/><net_sink comp="160" pin=2"/></net>

<net id="288"><net_src comp="137" pin="2"/><net_sink comp="285" pin=0"/></net>

<net id="289"><net_src comp="285" pin="1"/><net_sink comp="239" pin=0"/></net>

<net id="293"><net_src comp="142" pin="2"/><net_sink comp="290" pin=0"/></net>

<net id="294"><net_src comp="290" pin="1"/><net_sink comp="239" pin=1"/></net>

<net id="298"><net_src comp="239" pin="2"/><net_sink comp="295" pin=0"/></net>

<net id="299"><net_src comp="295" pin="1"/><net_sink comp="147" pin=2"/></net>

</net_list>

</model> 
---------------- Datapath Model END ------------------

* FSMD analyzer results:
  - Output states:
	Port: result | {8 12 13 14 15 16 17 }
 - Input state : 
	Port: vector_mult : A | {2 3 4 5 6 7 8 10 }
	Port: vector_mult : B | {2 3 4 5 6 7 8 10 }
	Port: vector_mult : A_offset | {1 }
	Port: vector_mult : B_offset | {1 }
	Port: vector_mult : result_offset | {1 }
  - Chain level:
	State 1
	State 2
		B_addr : 1
		A_addr : 1
		A_addr_rd_req : 2
		B_addr_rd_req : 2
	State 3
	State 4
	State 5
	State 6
	State 7
	State 8
		result_addr : 1
		result_addr_wr_req : 2
	State 9
		exitcond : 1
		i_1 : 1
		StgValue_60 : 2
	State 10
	State 11
	State 12
		empty_4 : 1
	State 13
	State 14
	State 15
	State 16
	State 17


============================================================
+ Verbose Summary: Datapath Resource usage 
============================================================

* Functional unit list:
|----------|-------------------------------|---------|---------|---------|
| Operation|        Functional Unit        |  DSP48E |    FF   |   LUT   |
|----------|-------------------------------|---------|---------|---------|
|    mul   |          tmp_1_fu_239         |    3    |    0    |    20   |
|----------|-------------------------------|---------|---------|---------|
|    add   |           i_1_fu_233          |    0    |    0    |    13   |
|----------|-------------------------------|---------|---------|---------|
|   icmp   |        exitcond_fu_227        |    0    |    0    |    9    |
|----------|-------------------------------|---------|---------|---------|
|          | result_offset_read_read_fu_98 |    0    |    0    |    0    |
|          |   B_offset_read_read_fu_104   |    0    |    0    |    0    |
|   read   |   A_offset_read_read_fu_110   |    0    |    0    |    0    |
|          |    A_addr_read_read_fu_137    |    0    |    0    |    0    |
|          |    B_addr_read_read_fu_142    |    0    |    0    |    0    |
|----------|-------------------------------|---------|---------|---------|
|  readreq |       grp_readreq_fu_116      |    0    |    0    |    0    |
|          |       grp_readreq_fu_123      |    0    |    0    |    0    |
|----------|-------------------------------|---------|---------|---------|
| writeresp|      grp_writeresp_fu_130     |    0    |    0    |    0    |
|----------|-------------------------------|---------|---------|---------|
|   write  |    StgValue_68_write_fu_147   |    0    |    0    |    0    |
|----------|-------------------------------|---------|---------|---------|
|          |     result_offset5_fu_167     |    0    |    0    |    0    |
|partselect|        B_offset3_fu_177       |    0    |    0    |    0    |
|          |        A_offset1_fu_187       |    0    |    0    |    0    |
|----------|-------------------------------|---------|---------|---------|
|          |          tmp_4_fu_197         |    0    |    0    |    0    |
|   zext   |          tmp_5_fu_207         |    0    |    0    |    0    |
|          |          tmp_3_fu_217         |    0    |    0    |    0    |
|----------|-------------------------------|---------|---------|---------|
|   Total  |                               |    3    |    0    |    42   |
|----------|-------------------------------|---------|---------|---------|

Memories:
N/A

* Register list:
+----------------------+--------+
|                      |   FF   |
+----------------------+--------+
|  A_addr_read_reg_285 |   32   |
|    A_addr_reg_264    |   32   |
|   A_offset1_reg_253  |   30   |
|  B_addr_read_reg_290 |   32   |
|    B_addr_reg_258    |   32   |
|   B_offset3_reg_248  |   30   |
|   exitcond_reg_276   |    1   |
|      i_1_reg_280     |    4   |
|       i_reg_156      |    4   |
|  result_addr_reg_270 |   32   |
|result_offset5_reg_243|   30   |
|     tmp_1_reg_295    |   32   |
+----------------------+--------+
|         Total        |   291  |
+----------------------+--------+

* Multiplexer (MUX) list: 
|----------------------|------|------|------|--------||---------||---------|
|         Comp         |  Pin | Size |  BW  | S x BW ||  Delay  ||   LUT   |
|----------------------|------|------|------|--------||---------||---------|
|  grp_readreq_fu_116  |  p1  |   2  |  32  |   64   ||    9    |
|  grp_readreq_fu_123  |  p1  |   2  |  32  |   64   ||    9    |
| grp_writeresp_fu_130 |  p0  |   2  |   1  |    2   |
| grp_writeresp_fu_130 |  p1  |   2  |  32  |   64   ||    9    |
|----------------------|------|------|------|--------||---------||---------|
|         Total        |      |      |      |   194  ||  7.076  ||    27   |
|----------------------|------|------|------|--------||---------||---------|



* Summary:
+-----------+--------+--------+--------+--------+
|           | DSP48E |  Delay |   FF   |   LUT  |
+-----------+--------+--------+--------+--------+
|  Function |    3   |    -   |    0   |   42   |
|   Memory  |    -   |    -   |    -   |    -   |
|Multiplexer|    -   |    7   |    -   |   27   |
|  Register |    -   |    -   |   291  |    -   |
+-----------+--------+--------+--------+--------+
|   Total   |    3   |    7   |   291  |   69   |
+-----------+--------+--------+--------+--------+