Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

software_version_and_target_device
betaFALSE build_version2086221
date_generatedFri Feb 16 17:37:38 2018 os_platformLIN64
product_versionVivado v2017.4 (64-bit) project_idd80cfb1634044e00b4a9c0bf6f097819
project_iteration1 random_idf33f10d84655559c98e51326816ad42b
registration_id174113044_1777490152_210651568_722 route_designTRUE
target_devicexc7z020 target_familyzynq
target_packageclg484 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i5-4310M CPU @ 2.70GHz cpu_speed2693.881 MHz
os_nameUbuntu os_releaseUbuntu 14.04.5 LTS
system_ram16.000 GB total_processors1

vivado_usage
gui_handlers
addresstreetablepanel_address_tree_table=2 applyrsbmultiautomationdialog_checkbox_tree=11 basedialog_cancel=3 basedialog_ok=18
cmdmsgdialog_ok=1 coretreetablepanel_core_tree_table=11 createnewdiagramdialog_design_name=1 filesetpanel_file_set_panel_tree=5
flownavigatortreepanel_flow_navigator_tree=7 gensettingtreetablepanel_gen_setting_tree_table=2 gettingstartedview_create_new_project=1 gictreetablepanel_gic_tree_table=7
instancemenu_floorplanning=1 instancetreeview_show_tree_view=1 mainmenumgr_floorplanning=2 mainmenumgr_flow=4
mainmenumgr_help=2 mainmenumgr_io_planning=2 mainmenumgr_open_block_design=1 mainmenumgr_settings=1
mainmenumgr_timing=1 mainmenumgr_tools=14 mainmenumgr_view=3 mainmenumgr_window=8
mainwinmenumgr_layout=8 netlisttreeview_netlist_tree=5 pacommandnames_create_top_hdl=2 pacommandnames_customize_rsb_bloc=3
pacommandnames_fed_toggle_routing_resources=1 pacommandnames_goto_netlist_design=1 pacommandnames_regenerate_layout=1 pacommandnames_save_rsb_design=1
pacommandnames_schematic=1 pacommandnames_show_hierarchy=1 pacommandnames_simulation_run=2 pacommandnames_zoom_fit=1
pacommandnames_zoom_in=2 pacommandnames_zoom_out=1 partchooser_boards=4 paviews_schematic=1
primitivesmenu_cycle_colors=1 primitivesmenu_highlight_leaf_cells=1 projectnamechooser_project_name=2 rdicommands_custom_commands=1
rdicommands_settings=1 rsbapplyautomationbar_run_block_automation=1 rsbapplyautomationbar_run_connection_automation=2 selectmenu_highlight=1
systembuilderview_add_ip=3 taskbanner_close=3 utilizationhierviewtreetablepanel_show_percentage=2
java_command_handlers
createblockdesign=1 createtophdl=2 customizersbblock=3 fedtoggleroutingresourcescmdhandler=1
newproject=1 regeneratersblayout=1 reportutilization=2 runbitgen=2
runimplementation=1 runschematic=1 runsynthesis=1 saversbdesign=1
showhierarchy=1 toolssettings=1 viewtaskimplementation=1 viewtasksynthesis=1
zoomfit=1 zoomin=2 zoomout=1
other_data
guimode=1
project_data
constraintsetcount=0 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=0 export_simulation_ies=0
export_simulation_modelsim=0 export_simulation_questa=0 export_simulation_riviera=0 export_simulation_vcs=0
export_simulation_xsim=0 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=2 synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDL target_simulator=XSim totalimplruns=7 totalsynthesisruns=7

unisim_transformation
post_unisim_transformation
bibuf=130 bufg=1 carry4=18 fdre=964
fdse=78 gnd=44 ibuf=13 lut1=130
lut2=61 lut3=279 lut4=166 lut5=154
lut6=180 obuf=8 ps7=1 srl16e=19
srlc32e=47 vcc=50
pre_unisim_transformation
bibuf=130 bufg=1 carry4=18 fdre=964
fdse=78 gnd=44 ibuf=13 lut1=130
lut2=61 lut3=279 lut4=166 lut5=154
lut6=180 obuf=8 ps7=1 srl16e=19
srlc32e=47 vcc=50

ip_statistics
IP_Integrator/1
bdsource=USER core_container=NA da_axi4_cnt=2 da_board_cnt=3
da_ps7_cnt=1 iptotal=1 maxhierdepth=0 numblks=10
numhdlrefblks=0 numhierblks=4 numhlsblks=0 numnonxlnxblks=0
numpkgbdblks=0 numreposblks=6 numsysgenblks=0 synth_mode=OOC_per_IP
x_iplanguage=VHDL x_iplibrary=BlockDiagram x_ipname=design_1 x_ipvendor=xilinx.com
x_ipversion=1.00.a
axi_crossbar_v2_1_16_axi_crossbar/1
c_axi_addr_width=32 c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_buser_width=1
c_axi_data_width=32 c_axi_id_width=1 c_axi_protocol=2 c_axi_ruser_width=1
c_axi_supports_user_signals=0 c_axi_wuser_width=1 c_connectivity_mode=0 c_family=zynq
c_m_axi_addr_width=0x0000001000000010 c_m_axi_base_addr=0x00000000412100000000000041200000 c_m_axi_read_connectivity=0xFFFFFFFFFFFFFFFF c_m_axi_read_issuing=0x0000000100000001
c_m_axi_secure=0x00000000 c_m_axi_write_connectivity=0xFFFFFFFFFFFFFFFF c_m_axi_write_issuing=0x0000000100000001 c_num_addr_ranges=1
c_num_master_slots=2 c_num_slave_slots=1 c_r_register=1 c_s_axi_arb_priority=0x00000000
c_s_axi_base_id=0x00000000 c_s_axi_read_acceptance=0x00000001 c_s_axi_single_thread=0x00000001 c_s_axi_thread_id_width=0x00000000
c_s_axi_write_acceptance=0x00000001 core_container=NA iptotal=1 x_ipcorerevision=16
x_iplanguage=VHDL x_iplibrary=ip x_ipname=axi_crossbar x_ipproduct=Vivado 2017.4
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=2.1
axi_gpio/1
c_all_inputs=0 c_all_inputs_2=0 c_all_outputs=1 c_all_outputs_2=0
c_dout_default=0x00000000 c_dout_default_2=0x00000000 c_family=zynq c_gpio2_width=32
c_gpio_width=8 c_interrupt_present=0 c_is_dual=0 c_s_axi_addr_width=9
c_s_axi_data_width=32 c_tri_default=0xFFFFFFFF c_tri_default_2=0xFFFFFFFF core_container=NA
iptotal=1 x_ipcorerevision=17 x_iplanguage=VHDL x_iplibrary=ip
x_ipname=axi_gpio x_ipproduct=Vivado 2017.4 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=2.0
axi_gpio/2
c_all_inputs=1 c_all_inputs_2=1 c_all_outputs=0 c_all_outputs_2=0
c_dout_default=0x00000000 c_dout_default_2=0x00000000 c_family=zynq c_gpio2_width=5
c_gpio_width=8 c_interrupt_present=1 c_is_dual=1 c_s_axi_addr_width=9
c_s_axi_data_width=32 c_tri_default=0xFFFFFFFF c_tri_default_2=0xFFFFFFFF core_container=NA
iptotal=1 x_ipcorerevision=17 x_iplanguage=VHDL x_iplibrary=ip
x_ipname=axi_gpio x_ipproduct=Vivado 2017.4 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=2.0
axi_protocol_converter_v2_1_15_axi_protocol_converter/1
c_axi_addr_width=32 c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_buser_width=1
c_axi_data_width=32 c_axi_id_width=12 c_axi_ruser_width=1 c_axi_supports_read=1
c_axi_supports_user_signals=0 c_axi_supports_write=1 c_axi_wuser_width=1 c_family=zynq
c_ignore_id=0 c_m_axi_protocol=2 c_s_axi_protocol=1 c_translation_mode=2
core_container=NA iptotal=1 x_ipcorerevision=15 x_iplanguage=VHDL
x_iplibrary=ip x_ipname=axi_protocol_converter x_ipproduct=Vivado 2017.4 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=2.1
proc_sys_reset/1
c_aux_reset_high=0 c_aux_rst_width=4 c_ext_reset_high=0 c_ext_rst_width=4
c_family=zynq c_num_bus_rst=1 c_num_interconnect_aresetn=1 c_num_perp_aresetn=1
c_num_perp_rst=1 core_container=NA iptotal=1 x_ipcorerevision=12
x_iplanguage=VHDL x_iplibrary=ip x_ipname=proc_sys_reset x_ipproduct=Vivado 2017.4
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=5.0
processing_system7_v5.5_user_configuration/1
core_container=NA iptotal=1 pcw_apu_clk_ratio_enable=6:2:1 pcw_apu_peripheral_freqmhz=666.666667
pcw_armpll_ctrl_fbdiv=40 pcw_can0_grp_clk_enable=0 pcw_can0_peripheral_clksrc=External pcw_can0_peripheral_enable=0
pcw_can0_peripheral_freqmhz=-1 pcw_can1_grp_clk_enable=0 pcw_can1_peripheral_clksrc=External pcw_can1_peripheral_enable=0
pcw_can1_peripheral_freqmhz=-1 pcw_can_peripheral_clksrc=IO PLL pcw_can_peripheral_freqmhz=100 pcw_cpu_cpu_pll_freqmhz=1333.333
pcw_cpu_peripheral_clksrc=ARM PLL pcw_crystal_peripheral_freqmhz=33.333333 pcw_dci_peripheral_clksrc=DDR PLL pcw_dci_peripheral_freqmhz=10.159
pcw_ddr_ddr_pll_freqmhz=1066.667 pcw_ddr_hpr_to_critical_priority_level=15 pcw_ddr_hprlpr_queue_partition=HPR(0)/LPR(32) pcw_ddr_lpr_to_critical_priority_level=2
pcw_ddr_peripheral_clksrc=DDR PLL pcw_ddr_port0_hpr_enable=0 pcw_ddr_port1_hpr_enable=0 pcw_ddr_port2_hpr_enable=0
pcw_ddr_port3_hpr_enable=0 pcw_ddr_write_to_critical_priority_level=2 pcw_ddrpll_ctrl_fbdiv=32 pcw_enet0_enet0_io=MIO 16 .. 27
pcw_enet0_grp_mdio_enable=1 pcw_enet0_peripheral_clksrc=IO PLL pcw_enet0_peripheral_enable=1 pcw_enet0_peripheral_freqmhz=1000 Mbps
pcw_enet0_reset_enable=0 pcw_enet1_grp_mdio_enable=0 pcw_enet1_peripheral_clksrc=IO PLL pcw_enet1_peripheral_enable=0
pcw_enet1_peripheral_freqmhz=1000 Mbps pcw_enet1_reset_enable=0 pcw_enet_reset_polarity=Active Low pcw_fclk0_peripheral_clksrc=IO PLL
pcw_fclk1_peripheral_clksrc=IO PLL pcw_fclk2_peripheral_clksrc=IO PLL pcw_fclk3_peripheral_clksrc=IO PLL pcw_fpga0_peripheral_freqmhz=100.000000
pcw_fpga1_peripheral_freqmhz=150.000000 pcw_fpga2_peripheral_freqmhz=50.000000 pcw_fpga3_peripheral_freqmhz=50 pcw_fpga_fclk0_enable=1
pcw_fpga_fclk1_enable=0 pcw_fpga_fclk2_enable=0 pcw_fpga_fclk3_enable=0 pcw_ftm_cti_in0=DISABLED
pcw_ftm_cti_in1=DISABLED pcw_ftm_cti_in2=DISABLED pcw_ftm_cti_in3=DISABLED pcw_ftm_cti_out0=DISABLED
pcw_ftm_cti_out1=DISABLED pcw_ftm_cti_out2=DISABLED pcw_ftm_cti_out3=DISABLED pcw_gpio_emio_gpio_enable=0
pcw_gpio_mio_gpio_enable=1 pcw_gpio_mio_gpio_io=MIO pcw_gpio_peripheral_enable=0 pcw_i2c0_grp_int_enable=0
pcw_i2c0_peripheral_enable=0 pcw_i2c0_reset_enable=0 pcw_i2c1_grp_int_enable=0 pcw_i2c1_peripheral_enable=0
pcw_i2c1_reset_enable=0 pcw_i2c_reset_polarity=Active Low pcw_io_io_pll_freqmhz=1000.000 pcw_iopll_ctrl_fbdiv=30
pcw_irq_f2p_mode=DIRECT pcw_m_axi_gp0_freqmhz=100 pcw_m_axi_gp1_freqmhz=10 pcw_nand_cycles_t_ar=1
pcw_nand_cycles_t_clr=1 pcw_nand_cycles_t_rc=11 pcw_nand_cycles_t_rea=1 pcw_nand_cycles_t_rr=1
pcw_nand_cycles_t_wc=11 pcw_nand_cycles_t_wp=1 pcw_nand_grp_d8_enable=0 pcw_nand_peripheral_enable=0
pcw_nor_cs0_t_ceoe=1 pcw_nor_cs0_t_pc=1 pcw_nor_cs0_t_rc=11 pcw_nor_cs0_t_tr=1
pcw_nor_cs0_t_wc=11 pcw_nor_cs0_t_wp=1 pcw_nor_cs0_we_time=0 pcw_nor_cs1_t_ceoe=1
pcw_nor_cs1_t_pc=1 pcw_nor_cs1_t_rc=11 pcw_nor_cs1_t_tr=1 pcw_nor_cs1_t_wc=11
pcw_nor_cs1_t_wp=1 pcw_nor_cs1_we_time=0 pcw_nor_grp_a25_enable=0 pcw_nor_grp_cs0_enable=0
pcw_nor_grp_cs1_enable=0 pcw_nor_grp_sram_cs0_enable=0 pcw_nor_grp_sram_cs1_enable=0 pcw_nor_grp_sram_int_enable=0
pcw_nor_peripheral_enable=0 pcw_nor_sram_cs0_t_ceoe=1 pcw_nor_sram_cs0_t_pc=1 pcw_nor_sram_cs0_t_rc=11
pcw_nor_sram_cs0_t_tr=1 pcw_nor_sram_cs0_t_wc=11 pcw_nor_sram_cs0_t_wp=1 pcw_nor_sram_cs0_we_time=0
pcw_nor_sram_cs1_t_ceoe=1 pcw_nor_sram_cs1_t_pc=1 pcw_nor_sram_cs1_t_rc=11 pcw_nor_sram_cs1_t_tr=1
pcw_nor_sram_cs1_t_wc=11 pcw_nor_sram_cs1_t_wp=1 pcw_nor_sram_cs1_we_time=0 pcw_override_basic_clock=0
pcw_pcap_peripheral_clksrc=IO PLL pcw_pcap_peripheral_freqmhz=200 pcw_pjtag_peripheral_enable=0 pcw_preset_bank0_voltage=LVCMOS 3.3V
pcw_preset_bank1_voltage=LVCMOS 1.8V pcw_qspi_grp_fbclk_enable=0 pcw_qspi_grp_io1_enable=0 pcw_qspi_grp_single_ss_enable=1
pcw_qspi_grp_single_ss_io=MIO 1 .. 6 pcw_qspi_grp_ss1_enable=0 pcw_qspi_internal_highaddress=0xFCFFFFFF pcw_qspi_peripheral_clksrc=IO PLL
pcw_qspi_peripheral_enable=1 pcw_qspi_peripheral_freqmhz=200.000000 pcw_qspi_qspi_io=MIO 1 .. 6 pcw_s_axi_acp_freqmhz=10
pcw_s_axi_gp0_freqmhz=10 pcw_s_axi_gp1_freqmhz=10 pcw_s_axi_hp0_data_width=64 pcw_s_axi_hp0_freqmhz=10
pcw_s_axi_hp1_data_width=64 pcw_s_axi_hp1_freqmhz=10 pcw_s_axi_hp2_data_width=64 pcw_s_axi_hp2_freqmhz=10
pcw_s_axi_hp3_data_width=64 pcw_s_axi_hp3_freqmhz=10 pcw_sd0_grp_cd_enable=1 pcw_sd0_grp_cd_io=MIO 47
pcw_sd0_grp_pow_enable=0 pcw_sd0_grp_wp_enable=1 pcw_sd0_grp_wp_io=MIO 46 pcw_sd0_peripheral_enable=1
pcw_sd0_sd0_io=MIO 40 .. 45 pcw_sd1_grp_cd_enable=0 pcw_sd1_grp_pow_enable=0 pcw_sd1_grp_wp_enable=0
pcw_sd1_peripheral_enable=0 pcw_sdio_peripheral_clksrc=IO PLL pcw_sdio_peripheral_freqmhz=50 pcw_single_qspi_data_mode=x4
pcw_smc_peripheral_clksrc=IO PLL pcw_smc_peripheral_freqmhz=100 pcw_spi0_grp_ss0_enable=0 pcw_spi0_grp_ss1_enable=0
pcw_spi0_grp_ss2_enable=0 pcw_spi0_peripheral_enable=0 pcw_spi1_grp_ss0_enable=0 pcw_spi1_grp_ss1_enable=0
pcw_spi1_grp_ss2_enable=0 pcw_spi1_peripheral_enable=0 pcw_spi_peripheral_clksrc=IO PLL pcw_spi_peripheral_freqmhz=166.666666
pcw_tpiu_peripheral_clksrc=External pcw_tpiu_peripheral_freqmhz=200 pcw_trace_grp_16bit_enable=0 pcw_trace_grp_2bit_enable=0
pcw_trace_grp_32bit_enable=0 pcw_trace_grp_4bit_enable=0 pcw_trace_grp_8bit_enable=0 pcw_trace_peripheral_enable=0
pcw_ttc0_clk0_peripheral_clksrc=CPU_1X pcw_ttc0_clk0_peripheral_freqmhz=133.333333 pcw_ttc0_clk1_peripheral_clksrc=CPU_1X pcw_ttc0_clk1_peripheral_freqmhz=133.333333
pcw_ttc0_clk2_peripheral_clksrc=CPU_1X pcw_ttc0_clk2_peripheral_freqmhz=133.333333 pcw_ttc0_peripheral_enable=1 pcw_ttc0_ttc0_io=EMIO
pcw_ttc1_clk0_peripheral_clksrc=CPU_1X pcw_ttc1_clk0_peripheral_freqmhz=133.333333 pcw_ttc1_clk1_peripheral_clksrc=CPU_1X pcw_ttc1_clk1_peripheral_freqmhz=133.333333
pcw_ttc1_clk2_peripheral_clksrc=CPU_1X pcw_ttc1_clk2_peripheral_freqmhz=133.333333 pcw_ttc1_peripheral_enable=0 pcw_ttc_peripheral_freqmhz=50
pcw_uart0_baud_rate=115200 pcw_uart0_grp_full_enable=0 pcw_uart0_peripheral_enable=0 pcw_uart1_baud_rate=115200
pcw_uart1_grp_full_enable=0 pcw_uart1_peripheral_enable=1 pcw_uart1_uart1_io=MIO 48 .. 49 pcw_uart_peripheral_clksrc=IO PLL
pcw_uart_peripheral_freqmhz=50 pcw_uiparam_ddr_adv_enable=0 pcw_uiparam_ddr_al=0 pcw_uiparam_ddr_bank_addr_count=3
pcw_uiparam_ddr_bl=8 pcw_uiparam_ddr_board_delay0=0.41 pcw_uiparam_ddr_board_delay1=0.411 pcw_uiparam_ddr_board_delay2=0.341
pcw_uiparam_ddr_board_delay3=0.358 pcw_uiparam_ddr_bus_width=32 Bit pcw_uiparam_ddr_cl=7 pcw_uiparam_ddr_clock_0_length_mm=0
pcw_uiparam_ddr_clock_0_package_length=61.0905 pcw_uiparam_ddr_clock_0_propogation_delay=160 pcw_uiparam_ddr_clock_1_length_mm=0 pcw_uiparam_ddr_clock_1_package_length=61.0905
pcw_uiparam_ddr_clock_1_propogation_delay=160 pcw_uiparam_ddr_clock_2_length_mm=0 pcw_uiparam_ddr_clock_2_package_length=61.0905 pcw_uiparam_ddr_clock_2_propogation_delay=160
pcw_uiparam_ddr_clock_3_length_mm=0 pcw_uiparam_ddr_clock_3_package_length=61.0905 pcw_uiparam_ddr_clock_3_propogation_delay=160 pcw_uiparam_ddr_clock_stop_en=0
pcw_uiparam_ddr_col_addr_count=10 pcw_uiparam_ddr_cwl=6 pcw_uiparam_ddr_device_capacity=2048 MBits pcw_uiparam_ddr_dq_0_length_mm=0
pcw_uiparam_ddr_dq_0_package_length=64.1705 pcw_uiparam_ddr_dq_0_propogation_delay=160 pcw_uiparam_ddr_dq_1_length_mm=0 pcw_uiparam_ddr_dq_1_package_length=63.686
pcw_uiparam_ddr_dq_1_propogation_delay=160 pcw_uiparam_ddr_dq_2_length_mm=0 pcw_uiparam_ddr_dq_2_package_length=68.46 pcw_uiparam_ddr_dq_2_propogation_delay=160
pcw_uiparam_ddr_dq_3_length_mm=0 pcw_uiparam_ddr_dq_3_package_length=105.4895 pcw_uiparam_ddr_dq_3_propogation_delay=160 pcw_uiparam_ddr_dqs_0_length_mm=0
pcw_uiparam_ddr_dqs_0_package_length=68.4725 pcw_uiparam_ddr_dqs_0_propogation_delay=160 pcw_uiparam_ddr_dqs_1_length_mm=0 pcw_uiparam_ddr_dqs_1_package_length=71.086
pcw_uiparam_ddr_dqs_1_propogation_delay=160 pcw_uiparam_ddr_dqs_2_length_mm=0 pcw_uiparam_ddr_dqs_2_package_length=66.794 pcw_uiparam_ddr_dqs_2_propogation_delay=160
pcw_uiparam_ddr_dqs_3_length_mm=0 pcw_uiparam_ddr_dqs_3_package_length=108.7385 pcw_uiparam_ddr_dqs_3_propogation_delay=160 pcw_uiparam_ddr_dqs_to_clk_delay_0=0.025
pcw_uiparam_ddr_dqs_to_clk_delay_1=0.028 pcw_uiparam_ddr_dqs_to_clk_delay_2=-0.009 pcw_uiparam_ddr_dqs_to_clk_delay_3=-0.061 pcw_uiparam_ddr_dram_width=16 Bits
pcw_uiparam_ddr_ecc=Disabled pcw_uiparam_ddr_enable=1 pcw_uiparam_ddr_freq_mhz=533.333313 pcw_uiparam_ddr_high_temp=Normal (0-85)
pcw_uiparam_ddr_memory_type=DDR 3 pcw_uiparam_ddr_partno=MT41J128M16 HA-15E pcw_uiparam_ddr_row_addr_count=14 pcw_uiparam_ddr_speed_bin=DDR3_1066F
pcw_uiparam_ddr_t_faw=45.0 pcw_uiparam_ddr_t_ras_min=36.0 pcw_uiparam_ddr_t_rc=49.5 pcw_uiparam_ddr_t_rcd=7
pcw_uiparam_ddr_t_rp=7 pcw_uiparam_ddr_train_data_eye=1 pcw_uiparam_ddr_train_read_gate=1 pcw_uiparam_ddr_train_write_level=1
pcw_uiparam_ddr_use_internal_vref=1 pcw_usb0_peripheral_enable=1 pcw_usb0_peripheral_freqmhz=60 pcw_usb0_reset_enable=0
pcw_usb0_usb0_io=MIO 28 .. 39 pcw_usb1_peripheral_enable=0 pcw_usb1_peripheral_freqmhz=60 pcw_usb1_reset_enable=0
pcw_usb_reset_polarity=Active Low pcw_use_cross_trigger=0 pcw_use_m_axi_gp0=1 pcw_use_m_axi_gp1=0
pcw_use_s_axi_acp=0 pcw_use_s_axi_gp0=0 pcw_use_s_axi_gp1=0 pcw_use_s_axi_hp0=0
pcw_use_s_axi_hp1=0 pcw_use_s_axi_hp2=0 pcw_use_s_axi_hp3=0 pcw_wdt_peripheral_clksrc=CPU_1X
pcw_wdt_peripheral_enable=0 pcw_wdt_peripheral_freqmhz=133.333333
processing_system7_v5_5_processing_system7/1
c_dm_width=4 c_dq_width=32 c_dqs_width=4 c_emio_gpio_width=64
c_en_emio_enet0=0 c_en_emio_enet1=0 c_en_emio_pjtag=0 c_en_emio_trace=0
c_fclk_clk0_buf=TRUE c_fclk_clk1_buf=FALSE c_fclk_clk2_buf=FALSE c_fclk_clk3_buf=FALSE
c_gp0_en_modifiable_txn=1 c_gp1_en_modifiable_txn=1 c_include_acp_trans_check=0 c_include_trace_buffer=0
c_irq_f2p_mode=DIRECT c_m_axi_gp0_enable_static_remap=0 c_m_axi_gp0_id_width=12 c_m_axi_gp0_thread_id_width=12
c_m_axi_gp1_enable_static_remap=0 c_m_axi_gp1_id_width=12 c_m_axi_gp1_thread_id_width=12 c_mio_primitive=54
c_num_f2p_intr_inputs=1 c_package_name=clg484 c_ps7_si_rev=PRODUCTION c_s_axi_acp_aruser_val=31
c_s_axi_acp_awuser_val=31 c_s_axi_acp_id_width=3 c_s_axi_gp0_id_width=6 c_s_axi_gp1_id_width=6
c_s_axi_hp0_data_width=64 c_s_axi_hp0_id_width=6 c_s_axi_hp1_data_width=64 c_s_axi_hp1_id_width=6
c_s_axi_hp2_data_width=64 c_s_axi_hp2_id_width=6 c_s_axi_hp3_data_width=64 c_s_axi_hp3_id_width=6
c_trace_buffer_clock_delay=12 c_trace_buffer_fifo_size=128 c_trace_internal_width=2 c_trace_pipeline_width=8
c_use_axi_nonsecure=0 c_use_default_acp_user_val=0 c_use_m_axi_gp0=1 c_use_m_axi_gp1=0
c_use_s_axi_acp=0 c_use_s_axi_gp0=0 c_use_s_axi_gp1=0 c_use_s_axi_hp0=0
c_use_s_axi_hp1=0 c_use_s_axi_hp2=0 c_use_s_axi_hp3=0 core_container=NA
iptotal=1 use_trace_data_edge_detector=0 x_ipcorerevision=6 x_iplanguage=VHDL
x_iplibrary=ip x_ipname=processing_system7 x_ipproduct=Vivado 2017.4 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=5.5

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-ruledecks=default::[not_specified] -upgrade_cw=default::[not_specified] -waived=default::[not_specified]

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=1 bufgctrl_util_percentage=3.13
bufhce_available=72 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=16 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=8 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=16 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=4 mmcme2_adv_fixed=0 mmcme2_adv_used=0 mmcme2_adv_util_percentage=0.00
plle2_adv_available=4 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=220 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=1 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=1 lvcmos25=1 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=1 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=140 block_ram_tile_fixed=0 block_ram_tile_used=0 block_ram_tile_util_percentage=0.00
ramb18_available=280 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=140 ramb36_fifo_fixed=0 ramb36_fifo_used=0 ramb36_fifo_util_percentage=0.00
primitives
bibuf_functional_category=IO bibuf_used=130 bufg_functional_category=Clock bufg_used=1
carry4_functional_category=CarryLogic carry4_used=18 fdre_functional_category=Flop & Latch fdre_used=916
fdse_functional_category=Flop & Latch fdse_used=70 ibuf_functional_category=IO ibuf_used=13
lut1_functional_category=LUT lut1_used=14 lut2_functional_category=LUT lut2_used=62
lut3_functional_category=LUT lut3_used=256 lut4_functional_category=LUT lut4_used=153
lut5_functional_category=LUT lut5_used=151 lut6_functional_category=LUT lut6_used=168
obuf_functional_category=IO obuf_used=8 ps7_functional_category=Specialized Resource ps7_used=1
srl16e_functional_category=Distributed Memory srl16e_used=19 srlc32e_functional_category=Distributed Memory srlc32e_used=47
slice_logic
f7_muxes_available=26600 f7_muxes_fixed=0 f7_muxes_used=0 f7_muxes_util_percentage=0.00
f8_muxes_available=13300 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0 lut_as_logic_available=53200 lut_as_logic_fixed=0
lut_as_logic_used=626 lut_as_logic_util_percentage=1.18 lut_as_memory_available=17400 lut_as_memory_fixed=0
lut_as_memory_used=62 lut_as_memory_util_percentage=0.36 lut_as_shift_register_fixed=0 lut_as_shift_register_used=62
register_as_flip_flop_available=106400 register_as_flip_flop_fixed=0 register_as_flip_flop_used=986 register_as_flip_flop_util_percentage=0.93
register_as_latch_available=106400 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=53200 slice_luts_fixed=0 slice_luts_used=688 slice_luts_util_percentage=1.29
slice_registers_available=106400 slice_registers_fixed=0 slice_registers_used=986 slice_registers_util_percentage=0.93
fully_used_lut_ff_pairs_fixed=0.93 fully_used_lut_ff_pairs_used=121 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0
lut_as_logic_available=53200 lut_as_logic_fixed=0 lut_as_logic_used=626 lut_as_logic_util_percentage=1.18
lut_as_memory_available=17400 lut_as_memory_fixed=0 lut_as_memory_used=62 lut_as_memory_util_percentage=0.36
lut_as_shift_register_fixed=0 lut_as_shift_register_used=62 lut_ff_pairs_with_one_unused_flip_flop_fixed=62 lut_ff_pairs_with_one_unused_flip_flop_used=290
lut_ff_pairs_with_one_unused_lut_output_fixed=290 lut_ff_pairs_with_one_unused_lut_output_used=297 lut_flip_flop_pairs_available=53200 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=444 lut_flip_flop_pairs_util_percentage=0.83 slice_available=13300 slice_fixed=0
slice_used=299 slice_util_percentage=2.25 slicel_fixed=0 slicel_used=183
slicem_fixed=0 slicem_used=116 unique_control_sets_used=46 using_o5_and_o6_fixed=46
using_o5_and_o6_used=4 using_o5_output_only_fixed=4 using_o5_output_only_used=0 using_o6_output_only_fixed=0
using_o6_output_only_used=58
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

router
usage
actual_expansions=959927 bogomips=5387 bram18=0 bram36=0
bufg=0 bufr=0 congestion_level=0 ctrls=46
dsp=0 effort=2 estimated_expansions=1409232 ff=986
global_clocks=1 high_fanout_nets=2 iob=21 lut=742
movable_instances=2111 nets=3320 pins=13654 pll=0
router_runtime=0.000000 router_timing_driven=1 threads=4 timing_constraints_exist=1

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7z020clg484-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=design_1_wrapper -verilog_define=default::[not_specified]
usage
elapsed=00:00:38s hls_ip=0 memory_gain=464.766MB memory_peak=1672.957MB