================================================================ == Vivado HLS Report for 'matrix_mult' ================================================================ * Date: Mon Mar 19 10:00:10 2018 * Version: 2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017) * Project: matrix_mult * Solution: solution3 * Product family: zynq * Target device: xc7z020clg484-1 ================================================================ == Performance Estimates ================================================================ + Timing (ns): * Summary: +--------+-------+----------+------------+ | Clock | Target| Estimated| Uncertainty| +--------+-------+----------+------------+ |ap_clk | 10.00| 8.75| 1.25| +--------+-------+----------+------------+ + Latency (clock cycles): * Summary: +-----+-----+-----+-----+---------+ | Latency | Interval | Pipeline| | min | max | min | max | Type | +-----+-----+-----+-----+---------+ | 256| 256| 256| 256| none | +-----+-----+-----+-----+---------+ + Detail: * Instance: N/A * Loop: +--------------------------------+-----+-----+----------+-----------+-----------+------+----------+ | | Latency | Iteration| Initiation Interval | Trip | | | Loop Name | min | max | Latency | achieved | target | Count| Pipelined| +--------------------------------+-----+-----+----------+-----------+-----------+------+----------+ |- memcpy.tempA.A | 65| 65| 3| 1| 1| 64| yes | |- memcpy.tempB.B | 65| 65| 3| 1| 1| 64| yes | |- matrix_mult__outer_loop | 20| 20| 9| 4| 1| 4| yes | |- memcpy.result.tempResult.gep | 65| 65| 3| 1| 1| 64| yes | +--------------------------------+-----+-----+----------+-----------+-----------+------+----------+ ================================================================ == Utilization Estimates ================================================================ * Summary: +-----------------+---------+-------+--------+-------+ | Name | BRAM_18K| DSP48E| FF | LUT | +-----------------+---------+-------+--------+-------+ |DSP | -| -| -| -| |Expression | -| 192| 0| 3554| |FIFO | -| -| -| -| |Instance | 2| -| 662| 812| |Memory | 12| -| 0| 0| |Multiplexer | -| -| -| 1089| |Register | -| -| 5147| -| +-----------------+---------+-------+--------+-------+ |Total | 14| 192| 5809| 5455| +-----------------+---------+-------+--------+-------+ |Available | 280| 220| 106400| 53200| +-----------------+---------+-------+--------+-------+ |Utilization (%) | 5| 87| 5| 10| +-----------------+---------+-------+--------+-------+ + Detail: * Instance: +------------------------------+----------------------------+---------+-------+-----+-----+ | Instance | Module | BRAM_18K| DSP48E| FF | LUT | +------------------------------+----------------------------+---------+-------+-----+-----+ |matrix_mult_AXILiteS_s_axi_U |matrix_mult_AXILiteS_s_axi | 0| 0| 150| 232| |matrix_mult_gmem_m_axi_U |matrix_mult_gmem_m_axi | 2| 0| 512| 580| +------------------------------+----------------------------+---------+-------+-----+-----+ |Total | | 2| 0| 662| 812| +------------------------------+----------------------------+---------+-------+-----+-----+ * DSP48: N/A * Memory: +----------------+----------------------+---------+---+----+------+-----+------+-------------+ | Memory | Module | BRAM_18K| FF| LUT| Words| Bits| Banks| W*Bits*Banks| +----------------+----------------------+---------+---+----+------+-----+------+-------------+ |tempA_0_U |matrix_mult_tempA_0 | 2| 0| 0| 32| 32| 1| 1024| |tempA_1_U |matrix_mult_tempA_0 | 2| 0| 0| 32| 32| 1| 1024| |tempB_0_U |matrix_mult_tempA_0 | 2| 0| 0| 32| 32| 1| 1024| |tempB_1_U |matrix_mult_tempA_0 | 2| 0| 0| 32| 32| 1| 1024| |tempResult_0_U |matrix_mult_tempRbkb | 2| 0| 0| 32| 32| 1| 1024| |tempResult_1_U |matrix_mult_tempRbkb | 2| 0| 0| 32| 32| 1| 1024| +----------------+----------------------+---------+---+----+------+-----+------+-------------+ |Total | | 12| 0| 0| 192| 192| 6| 6144| +----------------+----------------------+---------+---+----+------+-----+------+-------------+ * FIFO: N/A * Expression: +--------------------------------+----------+-------+---+----+------------+------------+ | Variable Name | Operation| DSP48E| FF| LUT| Bitwidth P0| Bitwidth P1| +--------------------------------+----------+-------+---+----+------------+------------+ |grp_fu_1163_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1168_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1173_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1178_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1183_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1188_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1193_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1198_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1203_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1208_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1213_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1218_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1223_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1228_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1233_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1238_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1243_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1248_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1253_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1258_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1263_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1268_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1273_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1278_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1283_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1288_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1293_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1298_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1303_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1308_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1313_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1318_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1323_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1328_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1333_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1338_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1343_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1348_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1353_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1358_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1363_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1368_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1373_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1378_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1383_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1388_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1393_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1398_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1403_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1408_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1413_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1418_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1423_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1428_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1433_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1438_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1443_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1448_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1453_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1458_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1463_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1468_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1473_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1478_p2 | * | 3| 0| 20| 32| 32| |grp_fu_1739_p2 | + | 0| 0| 39| 32| 32| |grp_fu_1745_p2 | + | 0| 0| 32| 32| 32| |grp_fu_1751_p2 | + | 0| 0| 32| 32| 32| |grp_fu_1757_p2 | + | 0| 0| 39| 32| 32| |grp_fu_1763_p2 | + | 0| 0| 32| 32| 32| |grp_fu_1769_p2 | + | 0| 0| 32| 32| 32| |grp_fu_1775_p2 | + | 0| 0| 39| 32| 32| |grp_fu_1781_p2 | + | 0| 0| 32| 32| 32| |grp_fu_1787_p2 | + | 0| 0| 32| 32| 32| |grp_fu_1793_p2 | + | 0| 0| 39| 32| 32| |grp_fu_1799_p2 | + | 0| 0| 32| 32| 32| |grp_fu_1805_p2 | + | 0| 0| 32| 32| 32| |grp_fu_1811_p2 | + | 0| 0| 39| 32| 32| |grp_fu_1817_p2 | + | 0| 0| 32| 32| 32| |grp_fu_1823_p2 | + | 0| 0| 32| 32| 32| |grp_fu_1829_p2 | + | 0| 0| 39| 32| 32| |grp_fu_1835_p2 | + | 0| 0| 32| 32| 32| |grp_fu_1841_p2 | + | 0| 0| 32| 32| 32| |grp_fu_1847_p2 | + | 0| 0| 39| 32| 32| |grp_fu_1853_p2 | + | 0| 0| 32| 32| 32| |grp_fu_1859_p2 | + | 0| 0| 32| 32| 32| |grp_fu_1865_p2 | + | 0| 0| 39| 32| 32| |grp_fu_1871_p2 | + | 0| 0| 32| 32| 32| |grp_fu_1877_p2 | + | 0| 0| 32| 32| 32| |grp_fu_1883_p2 | + | 0| 0| 39| 32| 32| |grp_fu_1889_p2 | + | 0| 0| 39| 32| 32| |grp_fu_1895_p2 | + | 0| 0| 32| 32| 32| |grp_fu_1901_p2 | + | 0| 0| 39| 32| 32| |grp_fu_1907_p2 | + | 0| 0| 39| 32| 32| |grp_fu_1913_p2 | + | 0| 0| 32| 32| 32| |grp_fu_1919_p2 | + | 0| 0| 39| 32| 32| |grp_fu_1925_p2 | + | 0| 0| 39| 32| 32| |grp_fu_1931_p2 | + | 0| 0| 32| 32| 32| |grp_fu_1937_p2 | + | 0| 0| 39| 32| 32| |grp_fu_1943_p2 | + | 0| 0| 39| 32| 32| |grp_fu_1949_p2 | + | 0| 0| 32| 32| 32| |grp_fu_1955_p2 | + | 0| 0| 39| 32| 32| |grp_fu_1961_p2 | + | 0| 0| 39| 32| 32| |grp_fu_1967_p2 | + | 0| 0| 32| 32| 32| |grp_fu_1973_p2 | + | 0| 0| 39| 32| 32| |grp_fu_1979_p2 | + | 0| 0| 39| 32| 32| |grp_fu_1985_p2 | + | 0| 0| 32| 32| 32| |grp_fu_1991_p2 | + | 0| 0| 39| 32| 32| |grp_fu_1997_p2 | + | 0| 0| 39| 32| 32| |grp_fu_2003_p2 | + | 0| 0| 32| 32| 32| |grp_fu_2009_p2 | + | 0| 0| 39| 32| 32| |grp_fu_2015_p2 | + | 0| 0| 39| 32| 32| |grp_fu_2021_p2 | + | 0| 0| 32| 32| 32| |grp_fu_2059_p2 | + | 0| 0| 32| 32| 32| |grp_fu_2065_p2 | + | 0| 0| 32| 32| 32| |grp_fu_2071_p2 | + | 0| 0| 32| 32| 32| |grp_fu_2077_p2 | + | 0| 0| 32| 32| 32| |grp_fu_2083_p2 | + | 0| 0| 32| 32| 32| |grp_fu_2089_p2 | + | 0| 0| 32| 32| 32| |grp_fu_2095_p2 | + | 0| 0| 32| 32| 32| |grp_fu_2101_p2 | + | 0| 0| 32| 32| 32| |i_1_1_fu_2369_p2 | + | 0| 0| 13| 2| 4| |indvar_next1_fu_2242_p2 | + | 0| 0| 15| 7| 1| |indvar_next2_fu_2381_p2 | + | 0| 0| 15| 7| 1| |indvar_next_fu_2211_p2 | + | 0| 0| 15| 7| 1| |ap_block_pp0_stage0_11001 | and | 0| 0| 8| 1| 1| |ap_block_pp1_stage0_11001 | and | 0| 0| 8| 1| 1| |ap_block_pp3_stage0_11001 | and | 0| 0| 8| 1| 1| |ap_block_state51_io | and | 0| 0| 8| 1| 1| |exitcond2_fu_2267_p2 | icmp | 0| 0| 11| 4| 5| |exitcond3_fu_2205_p2 | icmp | 0| 0| 11| 7| 8| |exitcond4_fu_2236_p2 | icmp | 0| 0| 11| 7| 8| |exitcond5_fu_2375_p2 | icmp | 0| 0| 11| 7| 8| |newIndex11_fu_2325_p2 | or | 0| 0| 12| 5| 3| |newIndex13_fu_2336_p2 | or | 0| 0| 12| 5| 3| |newIndex15_fu_2347_p2 | or | 0| 0| 12| 5| 3| |newIndex17_fu_2358_p2 | or | 0| 0| 12| 5| 3| |newIndex4_fu_2314_p2 | or | 0| 0| 12| 5| 2| |newIndex6_fu_2291_p2 | or | 0| 0| 12| 5| 1| |newIndex8_fu_2303_p2 | or | 0| 0| 12| 5| 2| |tempResult_load_phi_fu_2407_p3 | select | 0| 0| 32| 1| 32| |ap_enable_pp0 | xor | 0| 0| 8| 1| 2| |ap_enable_pp1 | xor | 0| 0| 8| 1| 2| |ap_enable_pp2 | xor | 0| 0| 8| 1| 2| |ap_enable_pp3 | xor | 0| 0| 8| 1| 2| |ap_enable_reg_pp0_iter1 | xor | 0| 0| 8| 2| 1| |ap_enable_reg_pp1_iter1 | xor | 0| 0| 8| 2| 1| |ap_enable_reg_pp2_iter1 | xor | 0| 0| 8| 2| 1| |ap_enable_reg_pp3_iter1 | xor | 0| 0| 8| 2| 1| +--------------------------------+----------+-------+---+----+------------+------------+ |Total | | 192| 0|3554| 3940| 3941| +--------------------------------+----------+-------+---+----+------------+------------+ * Multiplexer: +-----------------------------+-----+-----------+-----+-----------+ | Name | LUT | Input Size| Bits| Total Bits| +-----------------------------+-----+-----------+-----+-----------+ |ap_NS_fsm | 201| 46| 1| 46| |ap_enable_reg_pp0_iter1 | 9| 2| 1| 2| |ap_enable_reg_pp0_iter2 | 9| 2| 1| 2| |ap_enable_reg_pp1_iter1 | 9| 2| 1| 2| |ap_enable_reg_pp1_iter2 | 9| 2| 1| 2| |ap_enable_reg_pp2_iter1 | 9| 2| 1| 2| |ap_enable_reg_pp2_iter2 | 9| 2| 1| 2| |ap_enable_reg_pp3_iter1 | 9| 2| 1| 2| |ap_enable_reg_pp3_iter2 | 9| 2| 1| 2| |ap_phi_mux_i_phi_fu_1124_p4 | 9| 2| 4| 8| |ap_sig_ioackin_gmem_ARREADY | 9| 2| 1| 2| |ap_sig_ioackin_gmem_AWREADY | 9| 2| 1| 2| |ap_sig_ioackin_gmem_WREADY | 9| 2| 1| 2| |gmem_ARADDR | 15| 3| 32| 96| |gmem_blk_n_AR | 9| 2| 1| 2| |gmem_blk_n_AW | 9| 2| 1| 2| |gmem_blk_n_B | 9| 2| 1| 2| |gmem_blk_n_R | 9| 2| 1| 2| |gmem_blk_n_W | 9| 2| 1| 2| |i_reg_1120 | 9| 2| 4| 8| |indvar1_reg_1132 | 9| 2| 7| 14| |indvar9_reg_1109 | 9| 2| 7| 14| |indvar_reg_1098 | 9| 2| 7| 14| |reg_1143 | 9| 2| 32| 64| |reg_1148 | 9| 2| 32| 64| |reg_1153 | 9| 2| 32| 64| |reg_1158 | 9| 2| 32| 64| |tempA_0_address0 | 33| 6| 5| 30| |tempA_0_address1 | 27| 5| 5| 25| |tempA_1_address0 | 33| 6| 5| 30| |tempA_1_address1 | 27| 5| 5| 25| |tempB_0_address0 | 89| 18| 5| 90| |tempB_0_address1 | 85| 17| 5| 85| |tempB_1_address0 | 89| 18| 5| 90| |tempB_1_address1 | 85| 17| 5| 85| |tempResult_0_address0 | 33| 6| 5| 30| |tempResult_0_address1 | 27| 5| 5| 25| |tempResult_0_d0 | 15| 3| 32| 96| |tempResult_0_d1 | 15| 3| 32| 96| |tempResult_1_address0 | 33| 6| 5| 30| |tempResult_1_address1 | 27| 5| 5| 25| |tempResult_1_d0 | 15| 3| 32| 96| |tempResult_1_d1 | 15| 3| 32| 96| +-----------------------------+-----+-----------+-----+-----------+ |Total | 1089| 225| 394| 1442| +-----------------------------+-----+-----------+-----+-----------+ * Register: +--------------------------------------+----+----+-----+-----------+ | Name | FF | LUT| Bits| Const Bits| +--------------------------------------+----+----+-----+-----------+ |A1_reg_2424 | 30| 0| 30| 0| |B3_reg_2419 | 30| 0| 30| 0| |ap_CS_fsm | 45| 0| 45| 0| |ap_enable_reg_pp0_iter0 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter1 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter2 | 1| 0| 1| 0| |ap_enable_reg_pp1_iter0 | 1| 0| 1| 0| |ap_enable_reg_pp1_iter1 | 1| 0| 1| 0| |ap_enable_reg_pp1_iter2 | 1| 0| 1| 0| |ap_enable_reg_pp2_iter0 | 1| 0| 1| 0| |ap_enable_reg_pp2_iter1 | 1| 0| 1| 0| |ap_enable_reg_pp2_iter2 | 1| 0| 1| 0| |ap_enable_reg_pp3_iter0 | 1| 0| 1| 0| |ap_enable_reg_pp3_iter1 | 1| 0| 1| 0| |ap_enable_reg_pp3_iter2 | 1| 0| 1| 0| |ap_reg_ioackin_gmem_ARREADY | 1| 0| 1| 0| |ap_reg_ioackin_gmem_AWREADY | 1| 0| 1| 0| |ap_reg_ioackin_gmem_WREADY | 1| 0| 1| 0| |ap_reg_pp0_iter1_newIndex_reg_2460 | 6| 0| 6| 0| |ap_reg_pp0_iter1_tmp_reg_2456 | 1| 0| 1| 0| |ap_reg_pp1_iter1_newIndex2_reg_2484 | 6| 0| 6| 0| |ap_reg_pp1_iter1_tmp_1_reg_2480 | 1| 0| 1| 0| |ap_reg_pp2_iter1_exitcond2_reg_3135 | 1| 0| 1| 0| |ap_reg_pp2_iter1_newIndex10_reg_3197 | 3| 0| 64| 61| |ap_reg_pp2_iter1_newIndex12_reg_3213 | 2| 0| 64| 62| |ap_reg_pp2_iter1_newIndex14_reg_3229 | 2| 0| 64| 62| |ap_reg_pp2_iter1_newIndex16_reg_3245 | 2| 0| 64| 62| |ap_reg_pp2_iter1_newIndex18_reg_3261 | 2| 0| 64| 62| |ap_reg_pp2_iter1_newIndex5_reg_3149 | 3| 0| 64| 61| |ap_reg_pp2_iter1_newIndex7_reg_3165 | 3| 0| 64| 61| |ap_reg_pp2_iter1_newIndex9_reg_3181 | 3| 0| 64| 61| |ap_reg_pp3_iter1_exitcond5_reg_3282 | 1| 0| 1| 0| |exitcond2_reg_3135 | 1| 0| 1| 0| |exitcond5_reg_3282 | 1| 0| 1| 0| |gmem_addr_1_read_reg_2489 | 32| 0| 32| 0| |gmem_addr_1_reg_2441 | 30| 0| 32| 2| |gmem_addr_2_read_reg_2465 | 32| 0| 32| 0| |gmem_addr_reg_2435 | 30| 0| 32| 2| |i_1_1_reg_3277 | 4| 0| 4| 0| |i_reg_1120 | 4| 0| 4| 0| |indvar1_reg_1132 | 7| 0| 7| 0| |indvar9_reg_1109 | 7| 0| 7| 0| |indvar_reg_1098 | 7| 0| 7| 0| |newIndex10_reg_3197 | 3| 0| 64| 61| |newIndex12_reg_3213 | 2| 0| 64| 62| |newIndex14_reg_3229 | 2| 0| 64| 62| |newIndex16_reg_3245 | 2| 0| 64| 62| |newIndex18_reg_3261 | 2| 0| 64| 62| |newIndex2_reg_2484 | 6| 0| 6| 0| |newIndex5_reg_3149 | 3| 0| 64| 61| |newIndex7_reg_3165 | 3| 0| 64| 61| |newIndex9_reg_3181 | 3| 0| 64| 61| |newIndex_reg_2460 | 6| 0| 6| 0| |reg_1143 | 32| 0| 32| 0| |reg_1148 | 32| 0| 32| 0| |reg_1153 | 32| 0| 32| 0| |reg_1158 | 32| 0| 32| 0| |reg_1483 | 32| 0| 32| 0| |reg_1487 | 32| 0| 32| 0| |reg_1491 | 32| 0| 32| 0| |reg_1495 | 32| 0| 32| 0| |reg_1499 | 32| 0| 32| 0| |reg_1503 | 32| 0| 32| 0| |reg_1507 | 32| 0| 32| 0| |reg_1511 | 32| 0| 32| 0| |reg_1515 | 32| 0| 32| 0| |reg_1519 | 32| 0| 32| 0| |reg_1523 | 32| 0| 32| 0| |reg_1527 | 32| 0| 32| 0| |reg_1531 | 32| 0| 32| 0| |reg_1535 | 32| 0| 32| 0| |reg_1539 | 32| 0| 32| 0| |reg_1543 | 32| 0| 32| 0| |reg_1547 | 32| 0| 32| 0| |reg_1551 | 32| 0| 32| 0| |reg_1555 | 32| 0| 32| 0| |reg_1559 | 32| 0| 32| 0| |reg_1563 | 32| 0| 32| 0| |reg_1567 | 32| 0| 32| 0| |reg_1571 | 32| 0| 32| 0| |reg_1575 | 32| 0| 32| 0| |reg_1579 | 32| 0| 32| 0| |reg_1583 | 32| 0| 32| 0| |reg_1587 | 32| 0| 32| 0| |reg_1591 | 32| 0| 32| 0| |reg_1595 | 32| 0| 32| 0| |reg_1599 | 32| 0| 32| 0| |reg_1603 | 32| 0| 32| 0| |reg_1607 | 32| 0| 32| 0| |reg_1611 | 32| 0| 32| 0| |reg_1615 | 32| 0| 32| 0| |reg_1619 | 32| 0| 32| 0| |reg_1623 | 32| 0| 32| 0| |reg_1627 | 32| 0| 32| 0| |reg_1631 | 32| 0| 32| 0| |reg_1635 | 32| 0| 32| 0| |reg_1639 | 32| 0| 32| 0| |reg_1643 | 32| 0| 32| 0| |reg_1647 | 32| 0| 32| 0| |reg_1651 | 32| 0| 32| 0| |reg_1655 | 32| 0| 32| 0| |reg_1659 | 32| 0| 32| 0| |reg_1663 | 32| 0| 32| 0| |reg_1667 | 32| 0| 32| 0| |reg_1671 | 32| 0| 32| 0| |reg_1675 | 32| 0| 32| 0| |reg_1679 | 32| 0| 32| 0| |reg_1683 | 32| 0| 32| 0| |reg_1687 | 32| 0| 32| 0| |reg_1691 | 32| 0| 32| 0| |reg_1695 | 32| 0| 32| 0| |reg_1699 | 32| 0| 32| 0| |reg_1703 | 32| 0| 32| 0| |reg_1707 | 32| 0| 32| 0| |reg_1711 | 32| 0| 32| 0| |reg_1715 | 32| 0| 32| 0| |reg_1719 | 32| 0| 32| 0| |reg_1723 | 32| 0| 32| 0| |reg_1727 | 32| 0| 32| 0| |reg_1731 | 32| 0| 32| 0| |reg_1735 | 32| 0| 32| 0| |reg_2027 | 32| 0| 32| 0| |reg_2031 | 32| 0| 32| 0| |reg_2035 | 32| 0| 32| 0| |reg_2039 | 32| 0| 32| 0| |reg_2043 | 32| 0| 32| 0| |reg_2047 | 32| 0| 32| 0| |reg_2051 | 32| 0| 32| 0| |reg_2055 | 32| 0| 32| 0| |reg_2107 | 32| 0| 32| 0| |reg_2112 | 32| 0| 32| 0| |reg_2117 | 32| 0| 32| 0| |reg_2122 | 32| 0| 32| 0| |reg_2127 | 32| 0| 32| 0| |reg_2132 | 32| 0| 32| 0| |reg_2137 | 32| 0| 32| 0| |reg_2142 | 32| 0| 32| 0| |result5_reg_2414 | 30| 0| 30| 0| |tempB_0_load_10_reg_2715 | 32| 0| 32| 0| |tempB_0_load_11_reg_2720 | 32| 0| 32| 0| |tempB_0_load_12_reg_2755 | 32| 0| 32| 0| |tempB_0_load_13_reg_2760 | 32| 0| 32| 0| |tempB_0_load_14_reg_2795 | 32| 0| 32| 0| |tempB_0_load_15_reg_2800 | 32| 0| 32| 0| |tempB_0_load_16_reg_2835 | 32| 0| 32| 0| |tempB_0_load_17_reg_2840 | 32| 0| 32| 0| |tempB_0_load_18_reg_2875 | 32| 0| 32| 0| |tempB_0_load_19_reg_2880 | 32| 0| 32| 0| |tempB_0_load_1_reg_2520 | 32| 0| 32| 0| |tempB_0_load_20_reg_2915 | 32| 0| 32| 0| |tempB_0_load_21_reg_2920 | 32| 0| 32| 0| |tempB_0_load_22_reg_2955 | 32| 0| 32| 0| |tempB_0_load_23_reg_2960 | 32| 0| 32| 0| |tempB_0_load_24_reg_2995 | 32| 0| 32| 0| |tempB_0_load_25_reg_3000 | 32| 0| 32| 0| |tempB_0_load_26_reg_3035 | 32| 0| 32| 0| |tempB_0_load_27_reg_3040 | 32| 0| 32| 0| |tempB_0_load_28_reg_3075 | 32| 0| 32| 0| |tempB_0_load_29_reg_3080 | 32| 0| 32| 0| |tempB_0_load_2_reg_2555 | 32| 0| 32| 0| |tempB_0_load_30_reg_3115 | 32| 0| 32| 0| |tempB_0_load_31_reg_3120 | 32| 0| 32| 0| |tempB_0_load_3_reg_2560 | 32| 0| 32| 0| |tempB_0_load_4_reg_2595 | 32| 0| 32| 0| |tempB_0_load_5_reg_2600 | 32| 0| 32| 0| |tempB_0_load_6_reg_2635 | 32| 0| 32| 0| |tempB_0_load_7_reg_2640 | 32| 0| 32| 0| |tempB_0_load_8_reg_2675 | 32| 0| 32| 0| |tempB_0_load_9_reg_2680 | 32| 0| 32| 0| |tempB_0_load_reg_2515 | 32| 0| 32| 0| |tempB_1_load_10_reg_2735 | 32| 0| 32| 0| |tempB_1_load_11_reg_2740 | 32| 0| 32| 0| |tempB_1_load_12_reg_2775 | 32| 0| 32| 0| |tempB_1_load_13_reg_2780 | 32| 0| 32| 0| |tempB_1_load_14_reg_2805 | 32| 0| 32| 0| |tempB_1_load_15_reg_2810 | 32| 0| 32| 0| |tempB_1_load_16_reg_2855 | 32| 0| 32| 0| |tempB_1_load_17_reg_2860 | 32| 0| 32| 0| |tempB_1_load_18_reg_2895 | 32| 0| 32| 0| |tempB_1_load_19_reg_2900 | 32| 0| 32| 0| |tempB_1_load_1_reg_2540 | 32| 0| 32| 0| |tempB_1_load_20_reg_2935 | 32| 0| 32| 0| |tempB_1_load_21_reg_2940 | 32| 0| 32| 0| |tempB_1_load_22_reg_2965 | 32| 0| 32| 0| |tempB_1_load_23_reg_2970 | 32| 0| 32| 0| |tempB_1_load_24_reg_3015 | 32| 0| 32| 0| |tempB_1_load_25_reg_3020 | 32| 0| 32| 0| |tempB_1_load_26_reg_3055 | 32| 0| 32| 0| |tempB_1_load_27_reg_3060 | 32| 0| 32| 0| |tempB_1_load_28_reg_3095 | 32| 0| 32| 0| |tempB_1_load_29_reg_3100 | 32| 0| 32| 0| |tempB_1_load_2_reg_2575 | 32| 0| 32| 0| |tempB_1_load_30_reg_3125 | 32| 0| 32| 0| |tempB_1_load_31_reg_3130 | 32| 0| 32| 0| |tempB_1_load_3_reg_2580 | 32| 0| 32| 0| |tempB_1_load_4_reg_2615 | 32| 0| 32| 0| |tempB_1_load_5_reg_2620 | 32| 0| 32| 0| |tempB_1_load_6_reg_2645 | 32| 0| 32| 0| |tempB_1_load_7_reg_2650 | 32| 0| 32| 0| |tempB_1_load_8_reg_2695 | 32| 0| 32| 0| |tempB_1_load_9_reg_2700 | 32| 0| 32| 0| |tempB_1_load_reg_2535 | 32| 0| 32| 0| |tempResult_load_phi_reg_3306 | 32| 0| 32| 0| |tmp_1_reg_2480 | 1| 0| 1| 0| |tmp_4_reg_3139 | 3| 0| 5| 2| |tmp_97_reg_3291 | 1| 0| 1| 0| |tmp_reg_2456 | 1| 0| 1| 0| +--------------------------------------+----+----+-----+-----------+ |Total |5147| 0| 6137| 990| +--------------------------------------+----+----+-----+-----------+ ================================================================ == Interface ================================================================ * Summary: +------------------------+-----+-----+------------+--------------+--------------+ | RTL Ports | Dir | Bits| Protocol | Source Object| C Type | +------------------------+-----+-----+------------+--------------+--------------+ |s_axi_AXILiteS_AWVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_AWREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_AWADDR | in | 6| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WDATA | in | 32| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WSTRB | in | 4| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARADDR | in | 6| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RVALID | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RREADY | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RDATA | out | 32| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RRESP | out | 2| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BVALID | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BREADY | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BRESP | out | 2| s_axi | AXILiteS | scalar | |ap_clk | in | 1| ap_ctrl_hs | matrix_mult | return value | |ap_rst_n | in | 1| ap_ctrl_hs | matrix_mult | return value | |interrupt | out | 1| ap_ctrl_hs | matrix_mult | return value | |m_axi_gmem_AWVALID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_AWREADY | in | 1| m_axi | gmem | pointer | |m_axi_gmem_AWADDR | out | 32| m_axi | gmem | pointer | |m_axi_gmem_AWID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_AWLEN | out | 8| m_axi | gmem | pointer | |m_axi_gmem_AWSIZE | out | 3| m_axi | gmem | pointer | |m_axi_gmem_AWBURST | out | 2| m_axi | gmem | pointer | |m_axi_gmem_AWLOCK | out | 2| m_axi | gmem | pointer | |m_axi_gmem_AWCACHE | out | 4| m_axi | gmem | pointer | |m_axi_gmem_AWPROT | out | 3| m_axi | gmem | pointer | |m_axi_gmem_AWQOS | out | 4| m_axi | gmem | pointer | |m_axi_gmem_AWREGION | out | 4| m_axi | gmem | pointer | |m_axi_gmem_AWUSER | out | 1| m_axi | gmem | pointer | |m_axi_gmem_WVALID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_WREADY | in | 1| m_axi | gmem | pointer | |m_axi_gmem_WDATA | out | 32| m_axi | gmem | pointer | |m_axi_gmem_WSTRB | out | 4| m_axi | gmem | pointer | |m_axi_gmem_WLAST | out | 1| m_axi | gmem | pointer | |m_axi_gmem_WID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_WUSER | out | 1| m_axi | gmem | pointer | |m_axi_gmem_ARVALID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_ARREADY | in | 1| m_axi | gmem | pointer | |m_axi_gmem_ARADDR | out | 32| m_axi | gmem | pointer | |m_axi_gmem_ARID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_ARLEN | out | 8| m_axi | gmem | pointer | |m_axi_gmem_ARSIZE | out | 3| m_axi | gmem | pointer | |m_axi_gmem_ARBURST | out | 2| m_axi | gmem | pointer | |m_axi_gmem_ARLOCK | out | 2| m_axi | gmem | pointer | |m_axi_gmem_ARCACHE | out | 4| m_axi | gmem | pointer | |m_axi_gmem_ARPROT | out | 3| m_axi | gmem | pointer | |m_axi_gmem_ARQOS | out | 4| m_axi | gmem | pointer | |m_axi_gmem_ARREGION | out | 4| m_axi | gmem | pointer | |m_axi_gmem_ARUSER | out | 1| m_axi | gmem | pointer | |m_axi_gmem_RVALID | in | 1| m_axi | gmem | pointer | |m_axi_gmem_RREADY | out | 1| m_axi | gmem | pointer | |m_axi_gmem_RDATA | in | 32| m_axi | gmem | pointer | |m_axi_gmem_RLAST | in | 1| m_axi | gmem | pointer | |m_axi_gmem_RID | in | 1| m_axi | gmem | pointer | |m_axi_gmem_RUSER | in | 1| m_axi | gmem | pointer | |m_axi_gmem_RRESP | in | 2| m_axi | gmem | pointer | |m_axi_gmem_BVALID | in | 1| m_axi | gmem | pointer | |m_axi_gmem_BREADY | out | 1| m_axi | gmem | pointer | |m_axi_gmem_BRESP | in | 2| m_axi | gmem | pointer | |m_axi_gmem_BID | in | 1| m_axi | gmem | pointer | |m_axi_gmem_BUSER | in | 1| m_axi | gmem | pointer | +------------------------+-----+-----+------------+--------------+--------------+