; ModuleID = '/home/hakta/Documents/matrix_mult/solution3/.autopilot/db/a.o.2.bc'
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@memcpy_OC_tempB_OC_B.str = internal unnamed_addr constant [15 x i8] c"memcpy.tempB.B\00" ; [#uses=1 type=[15 x i8]*]
@memcpy_OC_tempA_OC_A.str = internal unnamed_addr constant [15 x i8] c"memcpy.tempA.A\00" ; [#uses=1 type=[15 x i8]*]
@memcpy_OC_result_OC_tempResult_OC_gep.str = internal unnamed_addr constant [29 x i8] c"memcpy.result.tempResult.gep\00" ; [#uses=1 type=[29 x i8]*]
@matrix_mult.str = internal unnamed_addr constant [12 x i8] c"matrix_mult\00" ; [#uses=1 type=[12 x i8]*]
@burstwrite_OC_region.str = internal unnamed_addr constant [18 x i8] c"burstwrite.region\00" ; [#uses=2 type=[18 x i8]*]
@burstread_OC_region.str = internal unnamed_addr constant [17 x i8] c"burstread.region\00" ; [#uses=4 type=[17 x i8]*]
@.str9 = internal unnamed_addr constant [1 x i8] zeroinitializer ; [#uses=1 type=[1 x i8]*]
@.str8 = internal unnamed_addr constant [1 x i8] zeroinitializer ; [#uses=1 type=[1 x i8]*]
@.str5 = private unnamed_addr constant [24 x i8] c"matrix_mult__outer_loop\00", align 1 ; [#uses=3 type=[24 x i8]*]
@.str3 = private unnamed_addr constant [10 x i8] c"s_axilite\00", align 1 ; [#uses=1 type=[10 x i8]*]
@.str2 = private unnamed_addr constant [6 x i8] c"slave\00", align 1 ; [#uses=3 type=[6 x i8]*]
@.str10 = internal unnamed_addr constant [1 x i8] zeroinitializer ; [#uses=1 type=[1 x i8]*]
@.str1 = private unnamed_addr constant [1 x i8] zeroinitializer, align 1 ; [#uses=22 type=[1 x i8]*]
@.str = private unnamed_addr constant [6 x i8] c"m_axi\00", align 1 ; [#uses=3 type=[6 x i8]*]

; [#uses=0]
define void @matrix_mult([64 x i32]* %A, [64 x i32]* %B, [64 x i32]* %result) nounwind uwtable {
  call void (...)* @_ssdm_op_SpecBitsMap([64 x i32]* %A) nounwind, !map !20
  call void (...)* @_ssdm_op_SpecBitsMap([64 x i32]* %B) nounwind, !map !26
  call void (...)* @_ssdm_op_SpecBitsMap([64 x i32]* %result) nounwind, !map !30
  call void (...)* @_ssdm_op_SpecTopModule([12 x i8]* @matrix_mult.str) nounwind
  %"tempA[0]" = alloca [32 x i32], align 4        ; [#uses=9 type=[32 x i32]*]
  %"tempA[1]" = alloca [32 x i32], align 4        ; [#uses=9 type=[32 x i32]*]
  %"tempB[0]" = alloca [32 x i32], align 4        ; [#uses=33 type=[32 x i32]*]
  %"tempB[1]" = alloca [32 x i32], align 4        ; [#uses=33 type=[32 x i32]*]
  %"tempResult[0]" = alloca [32 x i32], align 4   ; [#uses=9 type=[32 x i32]*]
  %"tempResult[1]" = alloca [32 x i32], align 4   ; [#uses=9 type=[32 x i32]*]
  call void @llvm.dbg.value(metadata !{[64 x i32]* %A}, i64 0, metadata !34), !dbg !38 ; [debug line = 4:22] [debug variable = A]
  call void @llvm.dbg.value(metadata !{[64 x i32]* %B}, i64 0, metadata !39), !dbg !40 ; [debug line = 4:34] [debug variable = B]
  call void @llvm.dbg.value(metadata !{[64 x i32]* %result}, i64 0, metadata !41), !dbg !42 ; [debug line = 4:46] [debug variable = result]
  call void (...)* @_ssdm_op_SpecInterface([64 x i32]* %result, [6 x i8]* @.str, i32 0, i32 0, [1 x i8]* @.str1, i32 0, i32 32, [1 x i8]* @.str1, [6 x i8]* @.str2, [1 x i8]* @.str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @.str1, [1 x i8]* @.str1) nounwind
  call void (...)* @_ssdm_op_SpecInterface([64 x i32]* %B, [6 x i8]* @.str, i32 0, i32 0, [1 x i8]* @.str1, i32 0, i32 32, [1 x i8]* @.str1, [6 x i8]* @.str2, [1 x i8]* @.str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @.str1, [1 x i8]* @.str1) nounwind
  call void (...)* @_ssdm_op_SpecInterface([64 x i32]* %A, [6 x i8]* @.str, i32 0, i32 0, [1 x i8]* @.str1, i32 0, i32 32, [1 x i8]* @.str1, [6 x i8]* @.str2, [1 x i8]* @.str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @.str1, [1 x i8]* @.str1) nounwind
  call void (...)* @_ssdm_op_SpecInterface(i32 0, [10 x i8]* @.str3, i32 0, i32 0, [1 x i8]* @.str1, i32 0, i32 0, [1 x i8]* @.str1, [1 x i8]* @.str1, [1 x i8]* @.str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @.str1, [1 x i8]* @.str1) nounwind, !dbg !43 ; [debug line = 5:1]
  call void @llvm.dbg.declare(metadata !{[32 x i32]* %"tempA[0]"}, metadata !45), !dbg !48 ; [debug line = 5:6] [debug variable = tempA[0]]
  call void @llvm.dbg.declare(metadata !{[32 x i32]* %"tempA[1]"}, metadata !49), !dbg !48 ; [debug line = 5:6] [debug variable = tempA[1]]
  call void @llvm.dbg.declare(metadata !{[32 x i32]* %"tempB[0]"}, metadata !50), !dbg !52 ; [debug line = 5:18] [debug variable = tempB[0]]
  call void @llvm.dbg.declare(metadata !{[32 x i32]* %"tempB[1]"}, metadata !53), !dbg !52 ; [debug line = 5:18] [debug variable = tempB[1]]
  call void @llvm.dbg.declare(metadata !{[32 x i32]* %"tempResult[0]"}, metadata !54), !dbg !56 ; [debug line = 5:30] [debug variable = tempResult[0]]
  call void @llvm.dbg.declare(metadata !{[32 x i32]* %"tempResult[1]"}, metadata !57), !dbg !56 ; [debug line = 5:30] [debug variable = tempResult[1]]
  %1 = lshr i7 -64, 1                             ; [#uses=0 type=i7]
  %2 = lshr i7 -64, 1                             ; [#uses=0 type=i7]
  br label %burst.rd.header

burst.rd.header:                                  ; preds = %burst.rd.body506, %0
  %indvar = phi i7 [ 0, %0 ], [ %indvar.next, %burst.rd.body506 ] ; [#uses=5 type=i7]
  %exitcond3 = icmp eq i7 %indvar, -64            ; [#uses=1 type=i1]
  %3 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 64, i64 64, i64 64) nounwind ; [#uses=0 type=i32]
  br i1 %exitcond3, label %burst.rd.header7.preheader, label %burst.rd.body

burst.rd.header7.preheader:                       ; preds = %burst.rd.header
  %4 = lshr i7 -64, 1                             ; [#uses=0 type=i7]
  %5 = lshr i7 -64, 1                             ; [#uses=0 type=i7]
  br label %burst.rd.header7

burst.rd.body:                                    ; preds = %burst.rd.header
  %burstread.rbegin = call i32 (...)* @_ssdm_op_SpecRegionBegin([17 x i8]* @burstread_OC_region.str) nounwind ; [#uses=1 type=i32]
  %6 = call i32 (...)* @_ssdm_op_SpecBurst([64 x i32]* %A, i32 1, i32 64, i32 1) nounwind ; [#uses=0 type=i32]
  call void (...)* @_ssdm_op_SpecPipeline(i32 1, i32 1, i32 1, i32 0, [1 x i8]* @.str8)
  call void (...)* @_ssdm_op_SpecLoopName([15 x i8]* @memcpy_OC_tempA_OC_A.str)
  %indvar.next = add i7 %indvar, 1                ; [#uses=1 type=i7]
  %tmp = zext i7 %indvar to i64, !dbg !58         ; [#uses=1 type=i64] [debug line = 6:2]
  %A.addr = getelementptr [64 x i32]* %A, i64 0, i64 %tmp, !dbg !58 ; [#uses=1 type=i32*] [debug line = 6:2]
  %A.load = load i32* %A.addr, align 4, !dbg !58  ; [#uses=2 type=i32] [debug line = 6:2]
  %arrayNo1 = trunc i7 %indvar to i1              ; [#uses=1 type=i1]
  %newIndex = lshr i7 %indvar, 1                  ; [#uses=1 type=i7]
  %newIndex1 = zext i7 %newIndex to i64           ; [#uses=2 type=i64]
  %"tempA[0].addr" = getelementptr [32 x i32]* %"tempA[0]", i64 0, i64 %newIndex1, !dbg !58 ; [#uses=1 type=i32*] [debug line = 6:2]
  %"tempA[1].addr" = getelementptr [32 x i32]* %"tempA[1]", i64 0, i64 %newIndex1, !dbg !58 ; [#uses=1 type=i32*] [debug line = 6:2]
  br i1 %arrayNo1, label %branch5, label %branch4, !dbg !58 ; [debug line = 6:2]

burst.rd.body506:                                 ; preds = %branch5, %branch4
  %burstread.rend = call i32 (...)* @_ssdm_op_SpecRegionEnd([17 x i8]* @burstread_OC_region.str, i32 %burstread.rbegin) nounwind ; [#uses=0 type=i32]
  br label %burst.rd.header

burst.rd.header7:                                 ; preds = %burst.rd.body8420, %burst.rd.header7.preheader
  %indvar9 = phi i7 [ %indvar.next1, %burst.rd.body8420 ], [ 0, %burst.rd.header7.preheader ] ; [#uses=5 type=i7]
  %exitcond4 = icmp eq i7 %indvar9, -64           ; [#uses=1 type=i1]
  %7 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 64, i64 64, i64 64) nounwind ; [#uses=0 type=i32]
  br i1 %exitcond4, label %burst.rd.end6.0.preheader, label %burst.rd.body8

burst.rd.end6.0.preheader:                        ; preds = %burst.rd.header7
  %"tempB[0].addr.1" = getelementptr [32 x i32]* %"tempB[0]", i64 0, i64 0 ; [#uses=1 type=i32*]
  %"tempB[0].load" = load i32* %"tempB[0].addr.1", align 16, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[0].addr.2" = getelementptr [32 x i32]* %"tempB[0]", i64 0, i64 4 ; [#uses=1 type=i32*]
  %"tempB[0].load.1" = load i32* %"tempB[0].addr.2", align 16, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[0].addr.3" = getelementptr [32 x i32]* %"tempB[0]", i64 0, i64 8 ; [#uses=1 type=i32*]
  %"tempB[0].load.2" = load i32* %"tempB[0].addr.3", align 16, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[0].addr.4" = getelementptr [32 x i32]* %"tempB[0]", i64 0, i64 12 ; [#uses=1 type=i32*]
  %"tempB[0].load.3" = load i32* %"tempB[0].addr.4", align 16, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[0].addr.5" = getelementptr [32 x i32]* %"tempB[0]", i64 0, i64 16 ; [#uses=1 type=i32*]
  %"tempB[0].load.4" = load i32* %"tempB[0].addr.5", align 16, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[0].addr.6" = getelementptr [32 x i32]* %"tempB[0]", i64 0, i64 20 ; [#uses=1 type=i32*]
  %"tempB[0].load.5" = load i32* %"tempB[0].addr.6", align 16, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[0].addr.7" = getelementptr [32 x i32]* %"tempB[0]", i64 0, i64 24 ; [#uses=1 type=i32*]
  %"tempB[0].load.6" = load i32* %"tempB[0].addr.7", align 16, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[0].addr.8" = getelementptr [32 x i32]* %"tempB[0]", i64 0, i64 28 ; [#uses=1 type=i32*]
  %"tempB[0].load.7" = load i32* %"tempB[0].addr.8", align 16, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[1].addr.1" = getelementptr [32 x i32]* %"tempB[1]", i64 0, i64 0 ; [#uses=1 type=i32*]
  %"tempB[1].load" = load i32* %"tempB[1].addr.1", align 4, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[1].addr.2" = getelementptr [32 x i32]* %"tempB[1]", i64 0, i64 4 ; [#uses=1 type=i32*]
  %"tempB[1].load.1" = load i32* %"tempB[1].addr.2", align 4, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[1].addr.3" = getelementptr [32 x i32]* %"tempB[1]", i64 0, i64 8 ; [#uses=1 type=i32*]
  %"tempB[1].load.2" = load i32* %"tempB[1].addr.3", align 4, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[1].addr.4" = getelementptr [32 x i32]* %"tempB[1]", i64 0, i64 12 ; [#uses=1 type=i32*]
  %"tempB[1].load.3" = load i32* %"tempB[1].addr.4", align 4, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[1].addr.5" = getelementptr [32 x i32]* %"tempB[1]", i64 0, i64 16 ; [#uses=1 type=i32*]
  %"tempB[1].load.4" = load i32* %"tempB[1].addr.5", align 4, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[1].addr.6" = getelementptr [32 x i32]* %"tempB[1]", i64 0, i64 20 ; [#uses=1 type=i32*]
  %"tempB[1].load.5" = load i32* %"tempB[1].addr.6", align 4, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[1].addr.7" = getelementptr [32 x i32]* %"tempB[1]", i64 0, i64 24 ; [#uses=1 type=i32*]
  %"tempB[1].load.6" = load i32* %"tempB[1].addr.7", align 4, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[1].addr.8" = getelementptr [32 x i32]* %"tempB[1]", i64 0, i64 28 ; [#uses=1 type=i32*]
  %"tempB[1].load.7" = load i32* %"tempB[1].addr.8", align 4, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[0].addr.9" = getelementptr [32 x i32]* %"tempB[0]", i64 0, i64 1 ; [#uses=1 type=i32*]
  %"tempB[0].load.8" = load i32* %"tempB[0].addr.9", align 8, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[0].addr.10" = getelementptr [32 x i32]* %"tempB[0]", i64 0, i64 5 ; [#uses=1 type=i32*]
  %"tempB[0].load.9" = load i32* %"tempB[0].addr.10", align 8, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[0].addr.11" = getelementptr [32 x i32]* %"tempB[0]", i64 0, i64 9 ; [#uses=1 type=i32*]
  %"tempB[0].load.10" = load i32* %"tempB[0].addr.11", align 8, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[0].addr.12" = getelementptr [32 x i32]* %"tempB[0]", i64 0, i64 13 ; [#uses=1 type=i32*]
  %"tempB[0].load.11" = load i32* %"tempB[0].addr.12", align 8, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[0].addr.13" = getelementptr [32 x i32]* %"tempB[0]", i64 0, i64 17 ; [#uses=1 type=i32*]
  %"tempB[0].load.12" = load i32* %"tempB[0].addr.13", align 8, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[0].addr.14" = getelementptr [32 x i32]* %"tempB[0]", i64 0, i64 21 ; [#uses=1 type=i32*]
  %"tempB[0].load.13" = load i32* %"tempB[0].addr.14", align 8, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[0].addr.15" = getelementptr [32 x i32]* %"tempB[0]", i64 0, i64 25 ; [#uses=1 type=i32*]
  %"tempB[0].load.14" = load i32* %"tempB[0].addr.15", align 8, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[0].addr.16" = getelementptr [32 x i32]* %"tempB[0]", i64 0, i64 29 ; [#uses=1 type=i32*]
  %"tempB[0].load.15" = load i32* %"tempB[0].addr.16", align 8, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[1].addr.9" = getelementptr [32 x i32]* %"tempB[1]", i64 0, i64 1 ; [#uses=1 type=i32*]
  %"tempB[1].load.8" = load i32* %"tempB[1].addr.9", align 4, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[1].addr.10" = getelementptr [32 x i32]* %"tempB[1]", i64 0, i64 5 ; [#uses=1 type=i32*]
  %"tempB[1].load.9" = load i32* %"tempB[1].addr.10", align 4, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[1].addr.11" = getelementptr [32 x i32]* %"tempB[1]", i64 0, i64 9 ; [#uses=1 type=i32*]
  %"tempB[1].load.10" = load i32* %"tempB[1].addr.11", align 4, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[1].addr.12" = getelementptr [32 x i32]* %"tempB[1]", i64 0, i64 13 ; [#uses=1 type=i32*]
  %"tempB[1].load.11" = load i32* %"tempB[1].addr.12", align 4, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[1].addr.13" = getelementptr [32 x i32]* %"tempB[1]", i64 0, i64 17 ; [#uses=1 type=i32*]
  %"tempB[1].load.12" = load i32* %"tempB[1].addr.13", align 4, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[1].addr.14" = getelementptr [32 x i32]* %"tempB[1]", i64 0, i64 21 ; [#uses=1 type=i32*]
  %"tempB[1].load.13" = load i32* %"tempB[1].addr.14", align 4, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[1].addr.15" = getelementptr [32 x i32]* %"tempB[1]", i64 0, i64 25 ; [#uses=1 type=i32*]
  %"tempB[1].load.14" = load i32* %"tempB[1].addr.15", align 4, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[1].addr.16" = getelementptr [32 x i32]* %"tempB[1]", i64 0, i64 29 ; [#uses=1 type=i32*]
  %"tempB[1].load.15" = load i32* %"tempB[1].addr.16", align 4, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[0].addr.17" = getelementptr [32 x i32]* %"tempB[0]", i64 0, i64 2 ; [#uses=1 type=i32*]
  %"tempB[0].load.16" = load i32* %"tempB[0].addr.17", align 16, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[0].addr.18" = getelementptr [32 x i32]* %"tempB[0]", i64 0, i64 6 ; [#uses=1 type=i32*]
  %"tempB[0].load.17" = load i32* %"tempB[0].addr.18", align 16, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[0].addr.19" = getelementptr [32 x i32]* %"tempB[0]", i64 0, i64 10 ; [#uses=1 type=i32*]
  %"tempB[0].load.18" = load i32* %"tempB[0].addr.19", align 16, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[0].addr.20" = getelementptr [32 x i32]* %"tempB[0]", i64 0, i64 14 ; [#uses=1 type=i32*]
  %"tempB[0].load.19" = load i32* %"tempB[0].addr.20", align 16, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[0].addr.21" = getelementptr [32 x i32]* %"tempB[0]", i64 0, i64 18 ; [#uses=1 type=i32*]
  %"tempB[0].load.20" = load i32* %"tempB[0].addr.21", align 16, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[0].addr.22" = getelementptr [32 x i32]* %"tempB[0]", i64 0, i64 22 ; [#uses=1 type=i32*]
  %"tempB[0].load.21" = load i32* %"tempB[0].addr.22", align 16, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[0].addr.23" = getelementptr [32 x i32]* %"tempB[0]", i64 0, i64 26 ; [#uses=1 type=i32*]
  %"tempB[0].load.22" = load i32* %"tempB[0].addr.23", align 16, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[0].addr.24" = getelementptr [32 x i32]* %"tempB[0]", i64 0, i64 30 ; [#uses=1 type=i32*]
  %"tempB[0].load.23" = load i32* %"tempB[0].addr.24", align 16, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[1].addr.17" = getelementptr [32 x i32]* %"tempB[1]", i64 0, i64 2 ; [#uses=1 type=i32*]
  %"tempB[1].load.16" = load i32* %"tempB[1].addr.17", align 4, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[1].addr.18" = getelementptr [32 x i32]* %"tempB[1]", i64 0, i64 6 ; [#uses=1 type=i32*]
  %"tempB[1].load.17" = load i32* %"tempB[1].addr.18", align 4, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[1].addr.19" = getelementptr [32 x i32]* %"tempB[1]", i64 0, i64 10 ; [#uses=1 type=i32*]
  %"tempB[1].load.18" = load i32* %"tempB[1].addr.19", align 4, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[1].addr.20" = getelementptr [32 x i32]* %"tempB[1]", i64 0, i64 14 ; [#uses=1 type=i32*]
  %"tempB[1].load.19" = load i32* %"tempB[1].addr.20", align 4, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[1].addr.21" = getelementptr [32 x i32]* %"tempB[1]", i64 0, i64 18 ; [#uses=1 type=i32*]
  %"tempB[1].load.20" = load i32* %"tempB[1].addr.21", align 4, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[1].addr.22" = getelementptr [32 x i32]* %"tempB[1]", i64 0, i64 22 ; [#uses=1 type=i32*]
  %"tempB[1].load.21" = load i32* %"tempB[1].addr.22", align 4, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[1].addr.23" = getelementptr [32 x i32]* %"tempB[1]", i64 0, i64 26 ; [#uses=1 type=i32*]
  %"tempB[1].load.22" = load i32* %"tempB[1].addr.23", align 4, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[1].addr.24" = getelementptr [32 x i32]* %"tempB[1]", i64 0, i64 30 ; [#uses=1 type=i32*]
  %"tempB[1].load.23" = load i32* %"tempB[1].addr.24", align 4, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[0].addr.25" = getelementptr [32 x i32]* %"tempB[0]", i64 0, i64 3 ; [#uses=1 type=i32*]
  %"tempB[0].load.24" = load i32* %"tempB[0].addr.25", align 8, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[0].addr.26" = getelementptr [32 x i32]* %"tempB[0]", i64 0, i64 7 ; [#uses=1 type=i32*]
  %"tempB[0].load.25" = load i32* %"tempB[0].addr.26", align 8, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[0].addr.27" = getelementptr [32 x i32]* %"tempB[0]", i64 0, i64 11 ; [#uses=1 type=i32*]
  %"tempB[0].load.26" = load i32* %"tempB[0].addr.27", align 8, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[0].addr.28" = getelementptr [32 x i32]* %"tempB[0]", i64 0, i64 15 ; [#uses=1 type=i32*]
  %"tempB[0].load.27" = load i32* %"tempB[0].addr.28", align 8, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[0].addr.29" = getelementptr [32 x i32]* %"tempB[0]", i64 0, i64 19 ; [#uses=1 type=i32*]
  %"tempB[0].load.28" = load i32* %"tempB[0].addr.29", align 8, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[0].addr.30" = getelementptr [32 x i32]* %"tempB[0]", i64 0, i64 23 ; [#uses=1 type=i32*]
  %"tempB[0].load.29" = load i32* %"tempB[0].addr.30", align 8, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[0].addr.31" = getelementptr [32 x i32]* %"tempB[0]", i64 0, i64 27 ; [#uses=1 type=i32*]
  %"tempB[0].load.30" = load i32* %"tempB[0].addr.31", align 8, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[0].addr.32" = getelementptr [32 x i32]* %"tempB[0]", i64 0, i64 31 ; [#uses=1 type=i32*]
  %"tempB[0].load.31" = load i32* %"tempB[0].addr.32", align 8, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[1].addr.25" = getelementptr [32 x i32]* %"tempB[1]", i64 0, i64 3 ; [#uses=1 type=i32*]
  %"tempB[1].load.24" = load i32* %"tempB[1].addr.25", align 4, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[1].addr.26" = getelementptr [32 x i32]* %"tempB[1]", i64 0, i64 7 ; [#uses=1 type=i32*]
  %"tempB[1].load.25" = load i32* %"tempB[1].addr.26", align 4, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[1].addr.27" = getelementptr [32 x i32]* %"tempB[1]", i64 0, i64 11 ; [#uses=1 type=i32*]
  %"tempB[1].load.26" = load i32* %"tempB[1].addr.27", align 4, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[1].addr.28" = getelementptr [32 x i32]* %"tempB[1]", i64 0, i64 15 ; [#uses=1 type=i32*]
  %"tempB[1].load.27" = load i32* %"tempB[1].addr.28", align 4, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[1].addr.29" = getelementptr [32 x i32]* %"tempB[1]", i64 0, i64 19 ; [#uses=1 type=i32*]
  %"tempB[1].load.28" = load i32* %"tempB[1].addr.29", align 4, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[1].addr.30" = getelementptr [32 x i32]* %"tempB[1]", i64 0, i64 23 ; [#uses=1 type=i32*]
  %"tempB[1].load.29" = load i32* %"tempB[1].addr.30", align 4, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[1].addr.31" = getelementptr [32 x i32]* %"tempB[1]", i64 0, i64 27 ; [#uses=1 type=i32*]
  %"tempB[1].load.30" = load i32* %"tempB[1].addr.31", align 4, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  %"tempB[1].addr.32" = getelementptr [32 x i32]* %"tempB[1]", i64 0, i64 31 ; [#uses=1 type=i32*]
  %"tempB[1].load.31" = load i32* %"tempB[1].addr.32", align 4, !dbg !59 ; [#uses=2 type=i32] [debug line = 16:5]
  br label %burst.rd.end6.0

burst.rd.body8:                                   ; preds = %burst.rd.header7
  %burstread.rbegin1 = call i32 (...)* @_ssdm_op_SpecRegionBegin([17 x i8]* @burstread_OC_region.str) nounwind ; [#uses=1 type=i32]
  %8 = call i32 (...)* @_ssdm_op_SpecBurst([64 x i32]* %B, i32 1, i32 64, i32 1) nounwind ; [#uses=0 type=i32]
  call void (...)* @_ssdm_op_SpecPipeline(i32 1, i32 1, i32 1, i32 0, [1 x i8]* @.str9)
  call void (...)* @_ssdm_op_SpecLoopName([15 x i8]* @memcpy_OC_tempB_OC_B.str)
  %indvar.next1 = add i7 %indvar9, 1              ; [#uses=1 type=i7]
  %tmp.1 = zext i7 %indvar9 to i64, !dbg !66      ; [#uses=1 type=i64] [debug line = 7:2]
  %B.addr = getelementptr [64 x i32]* %B, i64 0, i64 %tmp.1, !dbg !66 ; [#uses=1 type=i32*] [debug line = 7:2]
  %B.load = load i32* %B.addr, align 4, !dbg !66  ; [#uses=2 type=i32] [debug line = 7:2]
  %arrayNo2 = trunc i7 %indvar9 to i1             ; [#uses=1 type=i1]
  %newIndex2 = lshr i7 %indvar9, 1                ; [#uses=1 type=i7]
  %newIndex3 = zext i7 %newIndex2 to i64          ; [#uses=2 type=i64]
  %"tempB[0].addr" = getelementptr [32 x i32]* %"tempB[0]", i64 0, i64 %newIndex3, !dbg !66 ; [#uses=1 type=i32*] [debug line = 7:2]
  %"tempB[1].addr" = getelementptr [32 x i32]* %"tempB[1]", i64 0, i64 %newIndex3, !dbg !66 ; [#uses=1 type=i32*] [debug line = 7:2]
  br i1 %arrayNo2, label %branch3, label %branch2, !dbg !66 ; [debug line = 7:2]

burst.rd.body8420:                                ; preds = %branch3, %branch2
  %burstread.rend14 = call i32 (...)* @_ssdm_op_SpecRegionEnd([17 x i8]* @burstread_OC_region.str, i32 %burstread.rbegin1) nounwind ; [#uses=0 type=i32]
  br label %burst.rd.header7

burst.rd.end6.0:                                  ; preds = %burst.rd.end6.1, %burst.rd.end6.0.preheader
  %i = phi i4 [ %i.1.1, %burst.rd.end6.1 ], [ 0, %burst.rd.end6.0.preheader ] ; [#uses=3 type=i4]
  %i.cast = zext i4 %i to i5                      ; [#uses=1 type=i5]
  %9 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 4, i64 4, i64 4) nounwind ; [#uses=0 type=i32]
  %exitcond2 = icmp eq i4 %i, -8, !dbg !67        ; [#uses=1 type=i1] [debug line = 10:16]
  br i1 %exitcond2, label %burst.wr.header.preheader, label %burst.rd.end6.1, !dbg !67 ; [debug line = 10:16]

burst.wr.header.preheader:                        ; preds = %burst.rd.end6.0
  br label %burst.wr.header

burst.rd.end6.1:                                  ; preds = %burst.rd.end6.0
  call void (...)* @_ssdm_op_SpecLoopName([24 x i8]* @.str5) nounwind, !dbg !68 ; [debug line = 12:2]
  %tmp.2 = call i32 (...)* @_ssdm_op_SpecRegionBegin([24 x i8]* @.str5) nounwind, !dbg !68 ; [#uses=1 type=i32] [debug line = 12:2]
  call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @.str1) nounwind, !dbg !69 ; [debug line = 12:1]
  %tmp.4 = shl i5 %i.cast, 2                      ; [#uses=8 type=i5]
  %newIndex5 = zext i5 %tmp.4 to i64              ; [#uses=4 type=i64]
  %"tempResult[0].addr" = getelementptr [32 x i32]* %"tempResult[0]", i64 0, i64 %newIndex5 ; [#uses=1 type=i32*]
  %"tempA[0].addr.1" = getelementptr [32 x i32]* %"tempA[0]", i64 0, i64 %newIndex5 ; [#uses=1 type=i32*]
  %"tempA[0].load" = load i32* %"tempA[0].addr.1", align 16, !dbg !59 ; [#uses=8 type=i32] [debug line = 16:5]
  %tmp.10 = mul nsw i32 %"tempB[0].load", %"tempA[0].load", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %"tempA[1].addr.1" = getelementptr [32 x i32]* %"tempA[1]", i64 0, i64 %newIndex5 ; [#uses=1 type=i32*]
  %"tempA[1].load" = load i32* %"tempA[1].addr.1", align 4, !dbg !59 ; [#uses=8 type=i32] [debug line = 16:5]
  %tmp.10.0.0.1 = mul nsw i32 %"tempB[0].load.1", %"tempA[1].load", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %newIndex6 = or i5 %tmp.4, 1                    ; [#uses=1 type=i5]
  %newIndex7 = zext i5 %newIndex6 to i64          ; [#uses=4 type=i64]
  %"tempA[0].addr.2" = getelementptr [32 x i32]* %"tempA[0]", i64 0, i64 %newIndex7 ; [#uses=1 type=i32*]
  %"tempA[0].load.1" = load i32* %"tempA[0].addr.2", align 8, !dbg !59 ; [#uses=8 type=i32] [debug line = 16:5]
  %tmp.10.0.0.2 = mul nsw i32 %"tempB[0].load.2", %"tempA[0].load.1", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %"tempA[1].addr.2" = getelementptr [32 x i32]* %"tempA[1]", i64 0, i64 %newIndex7 ; [#uses=1 type=i32*]
  %"tempA[1].load.1" = load i32* %"tempA[1].addr.2", align 4, !dbg !59 ; [#uses=8 type=i32] [debug line = 16:5]
  %tmp.10.0.0.3 = mul nsw i32 %"tempB[0].load.3", %"tempA[1].load.1", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %newIndex8 = or i5 %tmp.4, 2                    ; [#uses=1 type=i5]
  %newIndex9 = zext i5 %newIndex8 to i64          ; [#uses=4 type=i64]
  %"tempA[0].addr.3" = getelementptr [32 x i32]* %"tempA[0]", i64 0, i64 %newIndex9 ; [#uses=1 type=i32*]
  %"tempA[0].load.2" = load i32* %"tempA[0].addr.3", align 16, !dbg !59 ; [#uses=8 type=i32] [debug line = 16:5]
  %tmp.10.0.0.4 = mul nsw i32 %"tempB[0].load.4", %"tempA[0].load.2", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %"tempA[1].addr.3" = getelementptr [32 x i32]* %"tempA[1]", i64 0, i64 %newIndex9 ; [#uses=1 type=i32*]
  %"tempA[1].load.2" = load i32* %"tempA[1].addr.3", align 4, !dbg !59 ; [#uses=8 type=i32] [debug line = 16:5]
  %tmp.10.0.0.5 = mul nsw i32 %"tempB[0].load.5", %"tempA[1].load.2", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %newIndex4 = or i5 %tmp.4, 3                    ; [#uses=1 type=i5]
  %newIndex10 = zext i5 %newIndex4 to i64         ; [#uses=4 type=i64]
  %"tempA[0].addr.4" = getelementptr [32 x i32]* %"tempA[0]", i64 0, i64 %newIndex10 ; [#uses=1 type=i32*]
  %"tempA[0].load.3" = load i32* %"tempA[0].addr.4", align 8, !dbg !59 ; [#uses=8 type=i32] [debug line = 16:5]
  %tmp.10.0.0.6 = mul nsw i32 %"tempB[0].load.6", %"tempA[0].load.3", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %"tempA[1].addr.4" = getelementptr [32 x i32]* %"tempA[1]", i64 0, i64 %newIndex10 ; [#uses=1 type=i32*]
  %"tempA[1].load.3" = load i32* %"tempA[1].addr.4", align 4, !dbg !59 ; [#uses=8 type=i32] [debug line = 16:5]
  %tmp.10.0.0.7 = mul nsw i32 %"tempB[0].load.7", %"tempA[1].load.3", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp2 = add i32 %tmp.10, %tmp.10.0.0.1, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp3 = add i32 %tmp.10.0.0.3, %tmp.10.0.0.2, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp1 = add i32 %tmp2, %tmp3, !dbg !59          ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp5 = add i32 %tmp.10.0.0.5, %tmp.10.0.0.4, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp6 = add i32 %tmp.10.0.0.7, %tmp.10.0.0.6, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp4 = add i32 %tmp5, %tmp6, !dbg !59          ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.11.0.0.7 = add nsw i32 %tmp1, %tmp4, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  store i32 %tmp.11.0.0.7, i32* %"tempResult[0].addr", align 16, !dbg !59 ; [debug line = 16:5]
  %"tempResult[1].addr" = getelementptr [32 x i32]* %"tempResult[1]", i64 0, i64 %newIndex5 ; [#uses=1 type=i32*]
  %tmp.10.0.1 = mul nsw i32 %"tempB[1].load", %"tempA[0].load", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.1.1 = mul nsw i32 %"tempB[1].load.1", %"tempA[1].load", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.1.2 = mul nsw i32 %"tempB[1].load.2", %"tempA[0].load.1", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.1.3 = mul nsw i32 %"tempB[1].load.3", %"tempA[1].load.1", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.1.4 = mul nsw i32 %"tempB[1].load.4", %"tempA[0].load.2", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.1.5 = mul nsw i32 %"tempB[1].load.5", %"tempA[1].load.2", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.1.6 = mul nsw i32 %"tempB[1].load.6", %"tempA[0].load.3", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.1.7 = mul nsw i32 %"tempB[1].load.7", %"tempA[1].load.3", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp8 = add i32 %tmp.10.0.1, %tmp.10.0.1.1, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp9 = add i32 %tmp.10.0.1.3, %tmp.10.0.1.2, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp7 = add i32 %tmp8, %tmp9, !dbg !59          ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp11 = add i32 %tmp.10.0.1.5, %tmp.10.0.1.4, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp12 = add i32 %tmp.10.0.1.7, %tmp.10.0.1.6, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp10 = add i32 %tmp11, %tmp12, !dbg !59       ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.11.0.1.7 = add nsw i32 %tmp7, %tmp10, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  store i32 %tmp.11.0.1.7, i32* %"tempResult[1].addr", align 4, !dbg !59 ; [debug line = 16:5]
  %"tempResult[0].addr.1" = getelementptr [32 x i32]* %"tempResult[0]", i64 0, i64 %newIndex7 ; [#uses=1 type=i32*]
  %tmp.10.0.2 = mul nsw i32 %"tempB[0].load.8", %"tempA[0].load", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.2.1 = mul nsw i32 %"tempB[0].load.9", %"tempA[1].load", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.2.2 = mul nsw i32 %"tempB[0].load.10", %"tempA[0].load.1", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.2.3 = mul nsw i32 %"tempB[0].load.11", %"tempA[1].load.1", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.2.4 = mul nsw i32 %"tempB[0].load.12", %"tempA[0].load.2", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.2.5 = mul nsw i32 %"tempB[0].load.13", %"tempA[1].load.2", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.2.6 = mul nsw i32 %"tempB[0].load.14", %"tempA[0].load.3", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.2.7 = mul nsw i32 %"tempB[0].load.15", %"tempA[1].load.3", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp14 = add i32 %tmp.10.0.2, %tmp.10.0.2.1, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp15 = add i32 %tmp.10.0.2.3, %tmp.10.0.2.2, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp13 = add i32 %tmp14, %tmp15, !dbg !59       ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp17 = add i32 %tmp.10.0.2.5, %tmp.10.0.2.4, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp18 = add i32 %tmp.10.0.2.7, %tmp.10.0.2.6, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp16 = add i32 %tmp17, %tmp18, !dbg !59       ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.11.0.2.7 = add nsw i32 %tmp13, %tmp16, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  store i32 %tmp.11.0.2.7, i32* %"tempResult[0].addr.1", align 8, !dbg !59 ; [debug line = 16:5]
  %"tempResult[1].addr.1" = getelementptr [32 x i32]* %"tempResult[1]", i64 0, i64 %newIndex7 ; [#uses=1 type=i32*]
  %tmp.10.0.3 = mul nsw i32 %"tempB[1].load.8", %"tempA[0].load", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.3.1 = mul nsw i32 %"tempB[1].load.9", %"tempA[1].load", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.3.2 = mul nsw i32 %"tempB[1].load.10", %"tempA[0].load.1", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.3.3 = mul nsw i32 %"tempB[1].load.11", %"tempA[1].load.1", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.3.4 = mul nsw i32 %"tempB[1].load.12", %"tempA[0].load.2", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.3.5 = mul nsw i32 %"tempB[1].load.13", %"tempA[1].load.2", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.3.6 = mul nsw i32 %"tempB[1].load.14", %"tempA[0].load.3", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.3.7 = mul nsw i32 %"tempB[1].load.15", %"tempA[1].load.3", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp20 = add i32 %tmp.10.0.3, %tmp.10.0.3.1, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp21 = add i32 %tmp.10.0.3.3, %tmp.10.0.3.2, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp19 = add i32 %tmp20, %tmp21, !dbg !59       ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp23 = add i32 %tmp.10.0.3.5, %tmp.10.0.3.4, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp24 = add i32 %tmp.10.0.3.7, %tmp.10.0.3.6, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp22 = add i32 %tmp23, %tmp24, !dbg !59       ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.11.0.3.7 = add nsw i32 %tmp19, %tmp22, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  store i32 %tmp.11.0.3.7, i32* %"tempResult[1].addr.1", align 4, !dbg !59 ; [debug line = 16:5]
  %"tempResult[0].addr.2" = getelementptr [32 x i32]* %"tempResult[0]", i64 0, i64 %newIndex9 ; [#uses=1 type=i32*]
  %tmp.10.0.4 = mul nsw i32 %"tempB[0].load.16", %"tempA[0].load", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.4.1 = mul nsw i32 %"tempB[0].load.17", %"tempA[1].load", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.4.2 = mul nsw i32 %"tempB[0].load.18", %"tempA[0].load.1", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.4.3 = mul nsw i32 %"tempB[0].load.19", %"tempA[1].load.1", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.4.4 = mul nsw i32 %"tempB[0].load.20", %"tempA[0].load.2", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.4.5 = mul nsw i32 %"tempB[0].load.21", %"tempA[1].load.2", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.4.6 = mul nsw i32 %"tempB[0].load.22", %"tempA[0].load.3", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.4.7 = mul nsw i32 %"tempB[0].load.23", %"tempA[1].load.3", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp26 = add i32 %tmp.10.0.4, %tmp.10.0.4.1, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp27 = add i32 %tmp.10.0.4.3, %tmp.10.0.4.2, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp25 = add i32 %tmp26, %tmp27, !dbg !59       ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp29 = add i32 %tmp.10.0.4.5, %tmp.10.0.4.4, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp30 = add i32 %tmp.10.0.4.7, %tmp.10.0.4.6, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp28 = add i32 %tmp29, %tmp30, !dbg !59       ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.11.0.4.7 = add nsw i32 %tmp25, %tmp28, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  store i32 %tmp.11.0.4.7, i32* %"tempResult[0].addr.2", align 16, !dbg !59 ; [debug line = 16:5]
  %"tempResult[1].addr.2" = getelementptr [32 x i32]* %"tempResult[1]", i64 0, i64 %newIndex9 ; [#uses=1 type=i32*]
  %tmp.10.0.5 = mul nsw i32 %"tempB[1].load.16", %"tempA[0].load", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.5.1 = mul nsw i32 %"tempB[1].load.17", %"tempA[1].load", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.5.2 = mul nsw i32 %"tempB[1].load.18", %"tempA[0].load.1", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.5.3 = mul nsw i32 %"tempB[1].load.19", %"tempA[1].load.1", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.5.4 = mul nsw i32 %"tempB[1].load.20", %"tempA[0].load.2", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.5.5 = mul nsw i32 %"tempB[1].load.21", %"tempA[1].load.2", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.5.6 = mul nsw i32 %"tempB[1].load.22", %"tempA[0].load.3", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.5.7 = mul nsw i32 %"tempB[1].load.23", %"tempA[1].load.3", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp32 = add i32 %tmp.10.0.5, %tmp.10.0.5.1, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp33 = add i32 %tmp.10.0.5.3, %tmp.10.0.5.2, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp31 = add i32 %tmp32, %tmp33, !dbg !59       ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp35 = add i32 %tmp.10.0.5.5, %tmp.10.0.5.4, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp36 = add i32 %tmp.10.0.5.7, %tmp.10.0.5.6, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp34 = add i32 %tmp35, %tmp36, !dbg !59       ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.11.0.5.7 = add nsw i32 %tmp31, %tmp34, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  store i32 %tmp.11.0.5.7, i32* %"tempResult[1].addr.2", align 4, !dbg !59 ; [debug line = 16:5]
  %"tempResult[0].addr.3" = getelementptr [32 x i32]* %"tempResult[0]", i64 0, i64 %newIndex10 ; [#uses=1 type=i32*]
  %tmp.10.0.6 = mul nsw i32 %"tempB[0].load.24", %"tempA[0].load", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.6.1 = mul nsw i32 %"tempB[0].load.25", %"tempA[1].load", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.6.2 = mul nsw i32 %"tempB[0].load.26", %"tempA[0].load.1", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.6.3 = mul nsw i32 %"tempB[0].load.27", %"tempA[1].load.1", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.6.4 = mul nsw i32 %"tempB[0].load.28", %"tempA[0].load.2", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.6.5 = mul nsw i32 %"tempB[0].load.29", %"tempA[1].load.2", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.6.6 = mul nsw i32 %"tempB[0].load.30", %"tempA[0].load.3", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.6.7 = mul nsw i32 %"tempB[0].load.31", %"tempA[1].load.3", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp38 = add i32 %tmp.10.0.6, %tmp.10.0.6.1, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp39 = add i32 %tmp.10.0.6.3, %tmp.10.0.6.2, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp37 = add i32 %tmp38, %tmp39, !dbg !59       ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp41 = add i32 %tmp.10.0.6.5, %tmp.10.0.6.4, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp42 = add i32 %tmp.10.0.6.7, %tmp.10.0.6.6, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp40 = add i32 %tmp41, %tmp42, !dbg !59       ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.11.0.6.7 = add nsw i32 %tmp37, %tmp40, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  store i32 %tmp.11.0.6.7, i32* %"tempResult[0].addr.3", align 8, !dbg !59 ; [debug line = 16:5]
  %"tempResult[1].addr.3" = getelementptr [32 x i32]* %"tempResult[1]", i64 0, i64 %newIndex10 ; [#uses=1 type=i32*]
  %tmp.10.0.7 = mul nsw i32 %"tempB[1].load.24", %"tempA[0].load", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.7.1 = mul nsw i32 %"tempB[1].load.25", %"tempA[1].load", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.7.2 = mul nsw i32 %"tempB[1].load.26", %"tempA[0].load.1", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.7.3 = mul nsw i32 %"tempB[1].load.27", %"tempA[1].load.1", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.7.4 = mul nsw i32 %"tempB[1].load.28", %"tempA[0].load.2", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.7.5 = mul nsw i32 %"tempB[1].load.29", %"tempA[1].load.2", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.7.6 = mul nsw i32 %"tempB[1].load.30", %"tempA[0].load.3", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.0.7.7 = mul nsw i32 %"tempB[1].load.31", %"tempA[1].load.3", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp44 = add i32 %tmp.10.0.7, %tmp.10.0.7.1, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp45 = add i32 %tmp.10.0.7.3, %tmp.10.0.7.2, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp43 = add i32 %tmp44, %tmp45, !dbg !59       ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp47 = add i32 %tmp.10.0.7.5, %tmp.10.0.7.4, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp48 = add i32 %tmp.10.0.7.7, %tmp.10.0.7.6, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp46 = add i32 %tmp47, %tmp48, !dbg !59       ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.11.0.7.7 = add nsw i32 %tmp43, %tmp46, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  store i32 %tmp.11.0.7.7, i32* %"tempResult[1].addr.3", align 4, !dbg !59 ; [debug line = 16:5]
  %10 = call i32 (...)* @_ssdm_op_SpecRegionEnd([24 x i8]* @.str5, i32 %tmp.2) nounwind, !dbg !70 ; [#uses=0 type=i32] [debug line = 16:61]
  %newIndex11 = or i5 %tmp.4, 4                   ; [#uses=1 type=i5]
  %newIndex12 = zext i5 %newIndex11 to i64        ; [#uses=4 type=i64]
  %"tempResult[0].addr.4" = getelementptr [32 x i32]* %"tempResult[0]", i64 0, i64 %newIndex12 ; [#uses=1 type=i32*]
  %"tempA[0].addr.5" = getelementptr [32 x i32]* %"tempA[0]", i64 0, i64 %newIndex12 ; [#uses=1 type=i32*]
  %"tempA[0].load.4" = load i32* %"tempA[0].addr.5", align 16, !dbg !59 ; [#uses=8 type=i32] [debug line = 16:5]
  %tmp.10.1 = mul nsw i32 %"tempB[0].load", %"tempA[0].load.4", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %"tempA[1].addr.5" = getelementptr [32 x i32]* %"tempA[1]", i64 0, i64 %newIndex12 ; [#uses=1 type=i32*]
  %"tempA[1].load.4" = load i32* %"tempA[1].addr.5", align 4, !dbg !59 ; [#uses=8 type=i32] [debug line = 16:5]
  %tmp.10.1.0.1 = mul nsw i32 %"tempB[0].load.1", %"tempA[1].load.4", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %newIndex13 = or i5 %tmp.4, 5                   ; [#uses=1 type=i5]
  %newIndex14 = zext i5 %newIndex13 to i64        ; [#uses=4 type=i64]
  %"tempA[0].addr.6" = getelementptr [32 x i32]* %"tempA[0]", i64 0, i64 %newIndex14 ; [#uses=1 type=i32*]
  %"tempA[0].load.5" = load i32* %"tempA[0].addr.6", align 8, !dbg !59 ; [#uses=8 type=i32] [debug line = 16:5]
  %tmp.10.1.0.2 = mul nsw i32 %"tempB[0].load.2", %"tempA[0].load.5", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %"tempA[1].addr.6" = getelementptr [32 x i32]* %"tempA[1]", i64 0, i64 %newIndex14 ; [#uses=1 type=i32*]
  %"tempA[1].load.5" = load i32* %"tempA[1].addr.6", align 4, !dbg !59 ; [#uses=8 type=i32] [debug line = 16:5]
  %tmp.10.1.0.3 = mul nsw i32 %"tempB[0].load.3", %"tempA[1].load.5", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %newIndex15 = or i5 %tmp.4, 6                   ; [#uses=1 type=i5]
  %newIndex16 = zext i5 %newIndex15 to i64        ; [#uses=4 type=i64]
  %"tempA[0].addr.7" = getelementptr [32 x i32]* %"tempA[0]", i64 0, i64 %newIndex16 ; [#uses=1 type=i32*]
  %"tempA[0].load.6" = load i32* %"tempA[0].addr.7", align 16, !dbg !59 ; [#uses=8 type=i32] [debug line = 16:5]
  %tmp.10.1.0.4 = mul nsw i32 %"tempB[0].load.4", %"tempA[0].load.6", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %"tempA[1].addr.7" = getelementptr [32 x i32]* %"tempA[1]", i64 0, i64 %newIndex16 ; [#uses=1 type=i32*]
  %"tempA[1].load.6" = load i32* %"tempA[1].addr.7", align 4, !dbg !59 ; [#uses=8 type=i32] [debug line = 16:5]
  %tmp.10.1.0.5 = mul nsw i32 %"tempB[0].load.5", %"tempA[1].load.6", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %newIndex17 = or i5 %tmp.4, 7                   ; [#uses=1 type=i5]
  %newIndex18 = zext i5 %newIndex17 to i64        ; [#uses=4 type=i64]
  %"tempA[0].addr.8" = getelementptr [32 x i32]* %"tempA[0]", i64 0, i64 %newIndex18 ; [#uses=1 type=i32*]
  %"tempA[0].load.7" = load i32* %"tempA[0].addr.8", align 8, !dbg !59 ; [#uses=8 type=i32] [debug line = 16:5]
  %tmp.10.1.0.6 = mul nsw i32 %"tempB[0].load.6", %"tempA[0].load.7", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %"tempA[1].addr.8" = getelementptr [32 x i32]* %"tempA[1]", i64 0, i64 %newIndex18 ; [#uses=1 type=i32*]
  %"tempA[1].load.7" = load i32* %"tempA[1].addr.8", align 4, !dbg !59 ; [#uses=8 type=i32] [debug line = 16:5]
  %tmp.10.1.0.7 = mul nsw i32 %"tempB[0].load.7", %"tempA[1].load.7", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp50 = add i32 %tmp.10.1, %tmp.10.1.0.1, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp51 = add i32 %tmp.10.1.0.3, %tmp.10.1.0.2, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp49 = add i32 %tmp50, %tmp51, !dbg !59       ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp53 = add i32 %tmp.10.1.0.5, %tmp.10.1.0.4, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp54 = add i32 %tmp.10.1.0.7, %tmp.10.1.0.6, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp52 = add i32 %tmp53, %tmp54, !dbg !59       ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.11.1.0.7 = add nsw i32 %tmp49, %tmp52, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  store i32 %tmp.11.1.0.7, i32* %"tempResult[0].addr.4", align 16, !dbg !59 ; [debug line = 16:5]
  %"tempResult[1].addr.4" = getelementptr [32 x i32]* %"tempResult[1]", i64 0, i64 %newIndex12 ; [#uses=1 type=i32*]
  %tmp.10.1.1 = mul nsw i32 %"tempB[1].load", %"tempA[0].load.4", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.1.1 = mul nsw i32 %"tempB[1].load.1", %"tempA[1].load.4", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.1.2 = mul nsw i32 %"tempB[1].load.2", %"tempA[0].load.5", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.1.3 = mul nsw i32 %"tempB[1].load.3", %"tempA[1].load.5", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.1.4 = mul nsw i32 %"tempB[1].load.4", %"tempA[0].load.6", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.1.5 = mul nsw i32 %"tempB[1].load.5", %"tempA[1].load.6", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.1.6 = mul nsw i32 %"tempB[1].load.6", %"tempA[0].load.7", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.1.7 = mul nsw i32 %"tempB[1].load.7", %"tempA[1].load.7", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp56 = add i32 %tmp.10.1.1, %tmp.10.1.1.1, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp57 = add i32 %tmp.10.1.1.3, %tmp.10.1.1.2, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp55 = add i32 %tmp56, %tmp57, !dbg !59       ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp59 = add i32 %tmp.10.1.1.5, %tmp.10.1.1.4, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp60 = add i32 %tmp.10.1.1.7, %tmp.10.1.1.6, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp58 = add i32 %tmp59, %tmp60, !dbg !59       ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.11.1.1.7 = add nsw i32 %tmp55, %tmp58, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  store i32 %tmp.11.1.1.7, i32* %"tempResult[1].addr.4", align 4, !dbg !59 ; [debug line = 16:5]
  %"tempResult[0].addr.5" = getelementptr [32 x i32]* %"tempResult[0]", i64 0, i64 %newIndex14 ; [#uses=1 type=i32*]
  %tmp.10.1.2 = mul nsw i32 %"tempB[0].load.8", %"tempA[0].load.4", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.2.1 = mul nsw i32 %"tempB[0].load.9", %"tempA[1].load.4", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.2.2 = mul nsw i32 %"tempB[0].load.10", %"tempA[0].load.5", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.2.3 = mul nsw i32 %"tempB[0].load.11", %"tempA[1].load.5", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.2.4 = mul nsw i32 %"tempB[0].load.12", %"tempA[0].load.6", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.2.5 = mul nsw i32 %"tempB[0].load.13", %"tempA[1].load.6", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.2.6 = mul nsw i32 %"tempB[0].load.14", %"tempA[0].load.7", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.2.7 = mul nsw i32 %"tempB[0].load.15", %"tempA[1].load.7", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp62 = add i32 %tmp.10.1.2, %tmp.10.1.2.1, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp63 = add i32 %tmp.10.1.2.3, %tmp.10.1.2.2, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp61 = add i32 %tmp62, %tmp63, !dbg !59       ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp65 = add i32 %tmp.10.1.2.5, %tmp.10.1.2.4, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp66 = add i32 %tmp.10.1.2.7, %tmp.10.1.2.6, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp64 = add i32 %tmp65, %tmp66, !dbg !59       ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.11.1.2.7 = add nsw i32 %tmp61, %tmp64, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  store i32 %tmp.11.1.2.7, i32* %"tempResult[0].addr.5", align 8, !dbg !59 ; [debug line = 16:5]
  %"tempResult[1].addr.5" = getelementptr [32 x i32]* %"tempResult[1]", i64 0, i64 %newIndex14 ; [#uses=1 type=i32*]
  %tmp.10.1.3 = mul nsw i32 %"tempB[1].load.8", %"tempA[0].load.4", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.3.1 = mul nsw i32 %"tempB[1].load.9", %"tempA[1].load.4", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.3.2 = mul nsw i32 %"tempB[1].load.10", %"tempA[0].load.5", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.3.3 = mul nsw i32 %"tempB[1].load.11", %"tempA[1].load.5", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.3.4 = mul nsw i32 %"tempB[1].load.12", %"tempA[0].load.6", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.3.5 = mul nsw i32 %"tempB[1].load.13", %"tempA[1].load.6", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.3.6 = mul nsw i32 %"tempB[1].load.14", %"tempA[0].load.7", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.3.7 = mul nsw i32 %"tempB[1].load.15", %"tempA[1].load.7", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp68 = add i32 %tmp.10.1.3, %tmp.10.1.3.1, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp69 = add i32 %tmp.10.1.3.3, %tmp.10.1.3.2, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp67 = add i32 %tmp68, %tmp69, !dbg !59       ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp71 = add i32 %tmp.10.1.3.5, %tmp.10.1.3.4, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp72 = add i32 %tmp.10.1.3.7, %tmp.10.1.3.6, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp70 = add i32 %tmp71, %tmp72, !dbg !59       ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.11.1.3.7 = add nsw i32 %tmp67, %tmp70, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  store i32 %tmp.11.1.3.7, i32* %"tempResult[1].addr.5", align 4, !dbg !59 ; [debug line = 16:5]
  %"tempResult[0].addr.6" = getelementptr [32 x i32]* %"tempResult[0]", i64 0, i64 %newIndex16 ; [#uses=1 type=i32*]
  %tmp.10.1.4 = mul nsw i32 %"tempB[0].load.16", %"tempA[0].load.4", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.4.1 = mul nsw i32 %"tempB[0].load.17", %"tempA[1].load.4", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.4.2 = mul nsw i32 %"tempB[0].load.18", %"tempA[0].load.5", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.4.3 = mul nsw i32 %"tempB[0].load.19", %"tempA[1].load.5", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.4.4 = mul nsw i32 %"tempB[0].load.20", %"tempA[0].load.6", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.4.5 = mul nsw i32 %"tempB[0].load.21", %"tempA[1].load.6", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.4.6 = mul nsw i32 %"tempB[0].load.22", %"tempA[0].load.7", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.4.7 = mul nsw i32 %"tempB[0].load.23", %"tempA[1].load.7", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp74 = add i32 %tmp.10.1.4, %tmp.10.1.4.1, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp75 = add i32 %tmp.10.1.4.3, %tmp.10.1.4.2, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp73 = add i32 %tmp74, %tmp75, !dbg !59       ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp77 = add i32 %tmp.10.1.4.5, %tmp.10.1.4.4, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp78 = add i32 %tmp.10.1.4.7, %tmp.10.1.4.6, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp76 = add i32 %tmp77, %tmp78, !dbg !59       ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.11.1.4.7 = add nsw i32 %tmp73, %tmp76, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  store i32 %tmp.11.1.4.7, i32* %"tempResult[0].addr.6", align 16, !dbg !59 ; [debug line = 16:5]
  %"tempResult[1].addr.6" = getelementptr [32 x i32]* %"tempResult[1]", i64 0, i64 %newIndex16 ; [#uses=1 type=i32*]
  %tmp.10.1.5 = mul nsw i32 %"tempB[1].load.16", %"tempA[0].load.4", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.5.1 = mul nsw i32 %"tempB[1].load.17", %"tempA[1].load.4", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.5.2 = mul nsw i32 %"tempB[1].load.18", %"tempA[0].load.5", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.5.3 = mul nsw i32 %"tempB[1].load.19", %"tempA[1].load.5", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.5.4 = mul nsw i32 %"tempB[1].load.20", %"tempA[0].load.6", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.5.5 = mul nsw i32 %"tempB[1].load.21", %"tempA[1].load.6", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.5.6 = mul nsw i32 %"tempB[1].load.22", %"tempA[0].load.7", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.5.7 = mul nsw i32 %"tempB[1].load.23", %"tempA[1].load.7", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp80 = add i32 %tmp.10.1.5, %tmp.10.1.5.1, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp81 = add i32 %tmp.10.1.5.3, %tmp.10.1.5.2, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp79 = add i32 %tmp80, %tmp81, !dbg !59       ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp83 = add i32 %tmp.10.1.5.5, %tmp.10.1.5.4, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp84 = add i32 %tmp.10.1.5.7, %tmp.10.1.5.6, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp82 = add i32 %tmp83, %tmp84, !dbg !59       ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.11.1.5.7 = add nsw i32 %tmp79, %tmp82, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  store i32 %tmp.11.1.5.7, i32* %"tempResult[1].addr.6", align 4, !dbg !59 ; [debug line = 16:5]
  %"tempResult[0].addr.7" = getelementptr [32 x i32]* %"tempResult[0]", i64 0, i64 %newIndex18 ; [#uses=1 type=i32*]
  %tmp.10.1.6 = mul nsw i32 %"tempB[0].load.24", %"tempA[0].load.4", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.6.1 = mul nsw i32 %"tempB[0].load.25", %"tempA[1].load.4", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.6.2 = mul nsw i32 %"tempB[0].load.26", %"tempA[0].load.5", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.6.3 = mul nsw i32 %"tempB[0].load.27", %"tempA[1].load.5", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.6.4 = mul nsw i32 %"tempB[0].load.28", %"tempA[0].load.6", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.6.5 = mul nsw i32 %"tempB[0].load.29", %"tempA[1].load.6", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.6.6 = mul nsw i32 %"tempB[0].load.30", %"tempA[0].load.7", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.6.7 = mul nsw i32 %"tempB[0].load.31", %"tempA[1].load.7", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp86 = add i32 %tmp.10.1.6, %tmp.10.1.6.1, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp87 = add i32 %tmp.10.1.6.3, %tmp.10.1.6.2, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp85 = add i32 %tmp86, %tmp87, !dbg !59       ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp89 = add i32 %tmp.10.1.6.5, %tmp.10.1.6.4, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp90 = add i32 %tmp.10.1.6.7, %tmp.10.1.6.6, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp88 = add i32 %tmp89, %tmp90, !dbg !59       ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.11.1.6.7 = add nsw i32 %tmp85, %tmp88, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  store i32 %tmp.11.1.6.7, i32* %"tempResult[0].addr.7", align 8, !dbg !59 ; [debug line = 16:5]
  %"tempResult[1].addr.7" = getelementptr [32 x i32]* %"tempResult[1]", i64 0, i64 %newIndex18 ; [#uses=1 type=i32*]
  %tmp.10.1.7 = mul nsw i32 %"tempB[1].load.24", %"tempA[0].load.4", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.7.1 = mul nsw i32 %"tempB[1].load.25", %"tempA[1].load.4", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.7.2 = mul nsw i32 %"tempB[1].load.26", %"tempA[0].load.5", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.7.3 = mul nsw i32 %"tempB[1].load.27", %"tempA[1].load.5", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.7.4 = mul nsw i32 %"tempB[1].load.28", %"tempA[0].load.6", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.7.5 = mul nsw i32 %"tempB[1].load.29", %"tempA[1].load.6", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.7.6 = mul nsw i32 %"tempB[1].load.30", %"tempA[0].load.7", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.10.1.7.7 = mul nsw i32 %"tempB[1].load.31", %"tempA[1].load.7", !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp92 = add i32 %tmp.10.1.7, %tmp.10.1.7.1, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp93 = add i32 %tmp.10.1.7.3, %tmp.10.1.7.2, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp91 = add i32 %tmp92, %tmp93, !dbg !59       ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp95 = add i32 %tmp.10.1.7.5, %tmp.10.1.7.4, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp96 = add i32 %tmp.10.1.7.7, %tmp.10.1.7.6, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp94 = add i32 %tmp95, %tmp96, !dbg !59       ; [#uses=1 type=i32] [debug line = 16:5]
  %tmp.11.1.7.7 = add nsw i32 %tmp91, %tmp94, !dbg !59 ; [#uses=1 type=i32] [debug line = 16:5]
  store i32 %tmp.11.1.7.7, i32* %"tempResult[1].addr.7", align 4, !dbg !59 ; [debug line = 16:5]
  %i.1.1 = add i4 %i, 2, !dbg !71                 ; [#uses=1 type=i4] [debug line = 10:25]
  br label %burst.rd.end6.0, !dbg !71             ; [debug line = 10:25]

burst.wr.header:                                  ; preds = %burst.wr.body_ifconv, %burst.wr.header.preheader
  %indvar1 = phi i7 [ %indvar.next2, %burst.wr.body_ifconv ], [ 0, %burst.wr.header.preheader ] ; [#uses=5 type=i7]
  %exitcond5 = icmp eq i7 %indvar1, -64           ; [#uses=1 type=i1]
  %11 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 64, i64 64, i64 64) nounwind ; [#uses=0 type=i32]
  br i1 %exitcond5, label %memcpy.tail, label %burst.wr.body_ifconv

burst.wr.body_ifconv:                             ; preds = %burst.wr.header
  %burstwrite.rbegin = call i32 (...)* @_ssdm_op_SpecRegionBegin([18 x i8]* @burstwrite_OC_region.str) nounwind ; [#uses=1 type=i32]
  %12 = call i32 (...)* @_ssdm_op_SpecBurst([64 x i32]* %result, i32 0, i32 64, i32 1) nounwind ; [#uses=0 type=i32]
  call void (...)* @_ssdm_op_SpecPipeline(i32 1, i32 1, i32 1, i32 0, [1 x i8]* @.str10)
  call void (...)* @_ssdm_op_SpecLoopName([29 x i8]* @memcpy_OC_result_OC_tempResult_OC_gep.str)
  %indvar.next2 = add i7 %indvar1, 1              ; [#uses=1 type=i7]
  %tmp.3 = zext i7 %indvar1 to i64, !dbg !72      ; [#uses=1 type=i64] [debug line = 18:2]
  %arrayNo = trunc i7 %indvar1 to i1              ; [#uses=1 type=i1]
  %newIndex19 = lshr i7 %indvar1, 1               ; [#uses=1 type=i7]
  %newIndex20 = zext i7 %newIndex19 to i64        ; [#uses=2 type=i64]
  %"tempResult[0].addr.8" = getelementptr [32 x i32]* %"tempResult[0]", i64 0, i64 %newIndex20, !dbg !72 ; [#uses=1 type=i32*] [debug line = 18:2]
  %"tempResult[1].addr.8" = getelementptr [32 x i32]* %"tempResult[1]", i64 0, i64 %newIndex20, !dbg !72 ; [#uses=1 type=i32*] [debug line = 18:2]
  %"tempResult[1].load" = load i32* %"tempResult[1].addr.8", align 4, !dbg !72 ; [#uses=1 type=i32] [debug line = 18:2]
  %"tempResult[0].load" = load i32* %"tempResult[0].addr.8", align 4, !dbg !72 ; [#uses=1 type=i32] [debug line = 18:2]
  %tempResult.load.phi = select i1 %arrayNo, i32 %"tempResult[1].load", i32 %"tempResult[0].load", !dbg !72 ; [#uses=1 type=i32] [debug line = 18:2]
  %result.addr = getelementptr [64 x i32]* %result, i64 0, i64 %tmp.3, !dbg !72 ; [#uses=1 type=i32*] [debug line = 18:2]
  store i32 %tempResult.load.phi, i32* %result.addr, align 4, !dbg !72 ; [debug line = 18:2]
  %burstwrite.rend = call i32 (...)* @_ssdm_op_SpecRegionEnd([18 x i8]* @burstwrite_OC_region.str, i32 %burstwrite.rbegin) nounwind ; [#uses=0 type=i32]
  br label %burst.wr.header

memcpy.tail:                                      ; preds = %burst.wr.header
  ret void, !dbg !73                              ; [debug line = 19:1]

branch2:                                          ; preds = %burst.rd.body8
  store i32 %B.load, i32* %"tempB[0].addr", align 4, !dbg !66 ; [debug line = 7:2]
  br label %burst.rd.body8420, !dbg !66           ; [debug line = 7:2]

branch3:                                          ; preds = %burst.rd.body8
  store i32 %B.load, i32* %"tempB[1].addr", align 4, !dbg !66 ; [debug line = 7:2]
  br label %burst.rd.body8420, !dbg !66           ; [debug line = 7:2]

branch4:                                          ; preds = %burst.rd.body
  store i32 %A.load, i32* %"tempA[0].addr", align 4, !dbg !58 ; [debug line = 6:2]
  br label %burst.rd.body506, !dbg !58            ; [debug line = 6:2]

branch5:                                          ; preds = %burst.rd.body
  store i32 %A.load, i32* %"tempA[1].addr", align 4, !dbg !58 ; [debug line = 6:2]
  br label %burst.rd.body506, !dbg !58            ; [debug line = 6:2]
}

; [#uses=3]
declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone

; [#uses=6]
declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone

; [#uses=1]
declare void @_ssdm_op_SpecTopModule(...)

; [#uses=4]
declare i32 @_ssdm_op_SpecRegionEnd(...)

; [#uses=4]
declare i32 @_ssdm_op_SpecRegionBegin(...)

; [#uses=4]
declare void @_ssdm_op_SpecPipeline(...) nounwind

; [#uses=4]
declare i32 @_ssdm_op_SpecLoopTripCount(...)

; [#uses=4]
declare void @_ssdm_op_SpecLoopName(...) nounwind

; [#uses=4]
declare void @_ssdm_op_SpecInterface(...) nounwind

; [#uses=3]
declare i32 @_ssdm_op_SpecBurst(...)

; [#uses=3]
declare void @_ssdm_op_SpecBitsMap(...)

!llvm.dbg.cu = !{!0}
!opencl.kernels = !{!13}
!hls.encrypted.func = !{}
!llvm.map.gv = !{}

!0 = metadata !{i32 786449, i32 0, i32 4, metadata !"/home/hakta/Documents/matrix_mult/solution3/.autopilot/db/matrix_mult.pragma.2.cpp", metadata !"/home/hakta/Documents", metadata !"clang version 3.1 ", i1 true, i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1} ; [ DW_TAG_compile_unit ]
!1 = metadata !{metadata !2}
!2 = metadata !{i32 0}
!3 = metadata !{metadata !4}
!4 = metadata !{metadata !5}
!5 = metadata !{i32 786478, i32 0, metadata !6, metadata !"matrix_mult", metadata !"matrix_mult", metadata !"_Z11matrix_multPiS_S_", metadata !6, i32 4, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, null, null, null, metadata !11, i32 4} ; [ DW_TAG_subprogram ]
!6 = metadata !{i32 786473, metadata !"matrix_mult/matrix_mult.cpp", metadata !"/home/hakta/Documents", null} ; [ DW_TAG_file_type ]
!7 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
!8 = metadata !{null, metadata !9, metadata !9, metadata !9}
!9 = metadata !{i32 786447, null, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !10} ; [ DW_TAG_pointer_type ]
!10 = metadata !{i32 786468, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
!11 = metadata !{metadata !12}
!12 = metadata !{i32 786468}                      ; [ DW_TAG_base_type ]
!13 = metadata !{null, metadata !14, metadata !15, metadata !16, metadata !17, metadata !18, metadata !19}
!14 = metadata !{metadata !"kernel_arg_addr_space", i32 1, i32 1, i32 1}
!15 = metadata !{metadata !"kernel_arg_access_qual", metadata !"none", metadata !"none", metadata !"none"}
!16 = metadata !{metadata !"kernel_arg_type", metadata !"int*", metadata !"int*", metadata !"int*"}
!17 = metadata !{metadata !"kernel_arg_type_qual", metadata !"", metadata !"", metadata !""}
!18 = metadata !{metadata !"kernel_arg_name", metadata !"A", metadata !"B", metadata !"result"}
!19 = metadata !{metadata !"reqd_work_group_size", i32 1, i32 1, i32 1}
!20 = metadata !{metadata !21}
!21 = metadata !{i32 0, i32 31, metadata !22}
!22 = metadata !{metadata !23}
!23 = metadata !{metadata !"A", metadata !24, metadata !"int", i32 0, i32 31}
!24 = metadata !{metadata !25}
!25 = metadata !{i32 0, i32 63, i32 1}
!26 = metadata !{metadata !27}
!27 = metadata !{i32 0, i32 31, metadata !28}
!28 = metadata !{metadata !29}
!29 = metadata !{metadata !"B", metadata !24, metadata !"int", i32 0, i32 31}
!30 = metadata !{metadata !31}
!31 = metadata !{i32 0, i32 31, metadata !32}
!32 = metadata !{metadata !33}
!33 = metadata !{metadata !"result", metadata !24, metadata !"int", i32 0, i32 31}
!34 = metadata !{i32 786689, metadata !5, metadata !"A", null, i32 4, metadata !35, i32 0, i32 0} ; [ DW_TAG_arg_variable ]
!35 = metadata !{i32 786433, null, metadata !"", null, i32 0, i64 2048, i64 32, i32 0, i32 0, metadata !10, metadata !36, i32 0, i32 0} ; [ DW_TAG_array_type ]
!36 = metadata !{metadata !37}
!37 = metadata !{i32 786465, i64 0, i64 63}       ; [ DW_TAG_subrange_type ]
!38 = metadata !{i32 4, i32 22, metadata !5, null}
!39 = metadata !{i32 786689, metadata !5, metadata !"B", null, i32 4, metadata !35, i32 0, i32 0} ; [ DW_TAG_arg_variable ]
!40 = metadata !{i32 4, i32 34, metadata !5, null}
!41 = metadata !{i32 786689, metadata !5, metadata !"result", null, i32 4, metadata !35, i32 0, i32 0} ; [ DW_TAG_arg_variable ]
!42 = metadata !{i32 4, i32 46, metadata !5, null}
!43 = metadata !{i32 5, i32 1, metadata !44, null}
!44 = metadata !{i32 786443, metadata !5, i32 4, i32 59, metadata !6, i32 0} ; [ DW_TAG_lexical_block ]
!45 = metadata !{i32 790529, metadata !46, metadata !"tempA[0]", null, i32 5, metadata !47, i32 0, i32 0} ; [ DW_TAG_auto_variable_field ]
!46 = metadata !{i32 786688, metadata !44, metadata !"tempA", metadata !6, i32 5, metadata !35, i32 0, i32 0} ; [ DW_TAG_auto_variable ]
!47 = metadata !{i32 786433, null, metadata !"", null, i32 0, i64 1024, i64 32, i32 0, i32 0, metadata !10, metadata !36, i32 0, i32 0} ; [ DW_TAG_array_type ]
!48 = metadata !{i32 5, i32 6, metadata !44, null}
!49 = metadata !{i32 790529, metadata !46, metadata !"tempA[1]", null, i32 5, metadata !47, i32 0, i32 0} ; [ DW_TAG_auto_variable_field ]
!50 = metadata !{i32 790529, metadata !51, metadata !"tempB[0]", null, i32 5, metadata !47, i32 0, i32 0} ; [ DW_TAG_auto_variable_field ]
!51 = metadata !{i32 786688, metadata !44, metadata !"tempB", metadata !6, i32 5, metadata !35, i32 0, i32 0} ; [ DW_TAG_auto_variable ]
!52 = metadata !{i32 5, i32 18, metadata !44, null}
!53 = metadata !{i32 790529, metadata !51, metadata !"tempB[1]", null, i32 5, metadata !47, i32 0, i32 0} ; [ DW_TAG_auto_variable_field ]
!54 = metadata !{i32 790529, metadata !55, metadata !"tempResult[0]", null, i32 5, metadata !47, i32 0, i32 0} ; [ DW_TAG_auto_variable_field ]
!55 = metadata !{i32 786688, metadata !44, metadata !"tempResult", metadata !6, i32 5, metadata !35, i32 0, i32 0} ; [ DW_TAG_auto_variable ]
!56 = metadata !{i32 5, i32 30, metadata !44, null}
!57 = metadata !{i32 790529, metadata !55, metadata !"tempResult[1]", null, i32 5, metadata !47, i32 0, i32 0} ; [ DW_TAG_auto_variable_field ]
!58 = metadata !{i32 6, i32 2, metadata !44, null}
!59 = metadata !{i32 16, i32 5, metadata !60, null}
!60 = metadata !{i32 786443, metadata !61, i32 16, i32 5, metadata !6, i32 6} ; [ DW_TAG_lexical_block ]
!61 = metadata !{i32 786443, metadata !62, i32 15, i32 4, metadata !6, i32 5} ; [ DW_TAG_lexical_block ]
!62 = metadata !{i32 786443, metadata !63, i32 12, i32 31, metadata !6, i32 4} ; [ DW_TAG_lexical_block ]
!63 = metadata !{i32 786443, metadata !64, i32 12, i32 3, metadata !6, i32 3} ; [ DW_TAG_lexical_block ]
!64 = metadata !{i32 786443, metadata !65, i32 12, i32 1, metadata !6, i32 2} ; [ DW_TAG_lexical_block ]
!65 = metadata !{i32 786443, metadata !44, i32 10, i32 2, metadata !6, i32 1} ; [ DW_TAG_lexical_block ]
!66 = metadata !{i32 7, i32 2, metadata !44, null}
!67 = metadata !{i32 10, i32 16, metadata !65, null}
!68 = metadata !{i32 12, i32 2, metadata !64, null}
!69 = metadata !{i32 12, i32 1, metadata !64, null}
!70 = metadata !{i32 16, i32 61, metadata !63, null}
!71 = metadata !{i32 10, i32 25, metadata !65, null}
!72 = metadata !{i32 18, i32 2, metadata !44, null}
!73 = metadata !{i32 19, i32 1, metadata !44, null}