================================================================ == Vivado HLS Report for 'matrix_mult' ================================================================ * Date: Mon Mar 19 10:08:09 2018 * Version: 2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017) * Project: matrix_mult * Solution: solution0 * Product family: zynq * Target device: xc7z020clg484-1 ================================================================ == Performance Estimates ================================================================ + Timing (ns): * Summary: +--------+-------+----------+------------+ | Clock | Target| Estimated| Uncertainty| +--------+-------+----------+------------+ |ap_clk | 10.00| 8.75| 1.25| +--------+-------+----------+------------+ + Latency (clock cycles): * Summary: +------+------+------+------+---------+ | Latency | Interval | Pipeline| | min | max | min | max | Type | +------+------+------+------+---------+ | 2411| 2411| 2411| 2411| none | +------+------+------+------+---------+ + Detail: * Instance: N/A * Loop: +----------------------------------+------+------+----------+-----------+-----------+------+----------+ | | Latency | Iteration| Initiation Interval | Trip | | | Loop Name | min | max | Latency | achieved | target | Count| Pipelined| +----------------------------------+------+------+----------+-----------+-----------+------+----------+ |- memcpy.tempA.A | 65| 65| 3| 1| 1| 64| yes | |- memcpy.tempB.B | 65| 65| 3| 1| 1| 64| yes | |- matrix_mult__outer_loop | 2192| 2192| 274| -| -| 8| no | | + matrix_mult__inner_loop | 272| 272| 34| -| -| 8| no | | ++ matrix_mult__innermost_loop | 32| 32| 4| -| -| 8| no | |- memcpy.result.tempResult.gep | 65| 65| 3| 1| 1| 64| yes | +----------------------------------+------+------+----------+-----------+-----------+------+----------+ ================================================================ == Utilization Estimates ================================================================ * Summary: +-----------------+---------+-------+--------+-------+ | Name | BRAM_18K| DSP48E| FF | LUT | +-----------------+---------+-------+--------+-------+ |DSP | -| -| -| -| |Expression | -| 3| 0| 358| |FIFO | -| -| -| -| |Instance | 2| -| 662| 812| |Memory | 3| -| 0| 0| |Multiplexer | -| -| -| 408| |Register | -| -| 508| -| +-----------------+---------+-------+--------+-------+ |Total | 5| 3| 1170| 1578| +-----------------+---------+-------+--------+-------+ |Available | 280| 220| 106400| 53200| +-----------------+---------+-------+--------+-------+ |Utilization (%) | 1| 1| 1| 2| +-----------------+---------+-------+--------+-------+ + Detail: * Instance: +------------------------------+----------------------------+---------+-------+-----+-----+ | Instance | Module | BRAM_18K| DSP48E| FF | LUT | +------------------------------+----------------------------+---------+-------+-----+-----+ |matrix_mult_AXILiteS_s_axi_U |matrix_mult_AXILiteS_s_axi | 0| 0| 150| 232| |matrix_mult_gmem_m_axi_U |matrix_mult_gmem_m_axi | 2| 0| 512| 580| +------------------------------+----------------------------+---------+-------+-----+-----+ |Total | | 2| 0| 662| 812| +------------------------------+----------------------------+---------+-------+-----+-----+ * DSP48: N/A * Memory: +--------------+-------------------+---------+---+----+------+-----+------+-------------+ | Memory | Module | BRAM_18K| FF| LUT| Words| Bits| Banks| W*Bits*Banks| +--------------+-------------------+---------+---+----+------+-----+------+-------------+ |tempA_U |matrix_mult_tempA | 1| 0| 0| 64| 32| 1| 2048| |tempB_U |matrix_mult_tempA | 1| 0| 0| 64| 32| 1| 2048| |tempResult_U |matrix_mult_tempA | 1| 0| 0| 64| 32| 1| 2048| +--------------+-------------------+---------+---+----+------+-----+------+-------------+ |Total | | 3| 0| 0| 192| 96| 3| 6144| +--------------+-------------------+---------+---+----+------+-----+------+-------------+ * FIFO: N/A * Expression: +-----------------------------------+----------+-------+---+----+------------+------------+ | Variable Name | Operation| DSP48E| FF| LUT| Bitwidth P0| Bitwidth P1| +-----------------------------------+----------+-------+---+----+------------+------------+ |tmp_10_fu_516_p2 | * | 3| 0| 20| 32| 32| |i_1_fu_424_p2 | + | 0| 0| 13| 4| 1| |indvar_next1_fu_407_p2 | + | 0| 0| 15| 7| 1| |indvar_next2_fu_531_p2 | + | 0| 0| 15| 7| 1| |indvar_next_fu_390_p2 | + | 0| 0| 15| 7| 1| |j_1_fu_452_p2 | + | 0| 0| 13| 4| 1| |k_1_fu_478_p2 | + | 0| 0| 13| 4| 1| |tmp_11_fu_520_p2 | + | 0| 0| 39| 32| 32| |tmp_4_fu_506_p2 | + | 0| 0| 15| 6| 6| |tmp_5_fu_458_p2 | + | 0| 0| 15| 6| 6| |tmp_8_fu_484_p2 | + | 0| 0| 15| 6| 6| |ap_block_pp0_stage0_11001 | and | 0| 0| 8| 1| 1| |ap_block_pp1_stage0_11001 | and | 0| 0| 8| 1| 1| |ap_block_pp2_stage0_11001 | and | 0| 0| 8| 1| 1| |ap_block_state10_pp0_stage0_iter1 | and | 0| 0| 8| 1| 1| |ap_block_state20_pp1_stage0_iter1 | and | 0| 0| 8| 1| 1| |ap_block_state23_io | and | 0| 0| 8| 1| 1| |ap_block_state31_io | and | 0| 0| 8| 1| 1| |exitcond1_fu_446_p2 | icmp | 0| 0| 11| 4| 5| |exitcond2_fu_418_p2 | icmp | 0| 0| 11| 4| 5| |exitcond3_fu_384_p2 | icmp | 0| 0| 11| 7| 8| |exitcond4_fu_401_p2 | icmp | 0| 0| 11| 7| 8| |exitcond5_fu_525_p2 | icmp | 0| 0| 11| 7| 8| |exitcond_fu_472_p2 | icmp | 0| 0| 11| 4| 5| |ap_enable_pp0 | xor | 0| 0| 8| 1| 2| |ap_enable_pp1 | xor | 0| 0| 8| 1| 2| |ap_enable_pp2 | xor | 0| 0| 8| 1| 2| |ap_enable_reg_pp0_iter1 | xor | 0| 0| 8| 2| 1| |ap_enable_reg_pp1_iter1 | xor | 0| 0| 8| 2| 1| |ap_enable_reg_pp2_iter1 | xor | 0| 0| 8| 2| 1| +-----------------------------------+----------+-------+---+----+------------+------------+ |Total | | 3| 0| 358| 164| 143| +-----------------------------------+----------+-------+---+----+------------+------------+ * Multiplexer: +----------------------------------+-----+-----------+-----+-----------+ | Name | LUT | Input Size| Bits| Total Bits| +----------------------------------+-----+-----------+-----+-----------+ |ap_NS_fsm | 141| 31| 1| 31| |ap_enable_reg_pp0_iter1 | 9| 2| 1| 2| |ap_enable_reg_pp0_iter2 | 9| 2| 1| 2| |ap_enable_reg_pp1_iter1 | 9| 2| 1| 2| |ap_enable_reg_pp1_iter2 | 9| 2| 1| 2| |ap_enable_reg_pp2_iter1 | 9| 2| 1| 2| |ap_enable_reg_pp2_iter2 | 9| 2| 1| 2| |ap_phi_mux_indvar9_phi_fu_261_p4 | 9| 2| 7| 14| |ap_phi_mux_indvar_phi_fu_249_p4 | 9| 2| 7| 14| |ap_sig_ioackin_gmem_ARREADY | 9| 2| 1| 2| |ap_sig_ioackin_gmem_AWREADY | 9| 2| 1| 2| |ap_sig_ioackin_gmem_WREADY | 9| 2| 1| 2| |gmem_ARADDR | 15| 3| 32| 96| |gmem_blk_n_AR | 9| 2| 1| 2| |gmem_blk_n_AW | 9| 2| 1| 2| |gmem_blk_n_B | 9| 2| 1| 2| |gmem_blk_n_R | 9| 2| 1| 2| |gmem_blk_n_W | 9| 2| 1| 2| |i_reg_269 | 9| 2| 4| 8| |indvar1_reg_315 | 9| 2| 7| 14| |indvar9_reg_257 | 9| 2| 7| 14| |indvar_reg_245 | 9| 2| 7| 14| |j_reg_280 | 9| 2| 4| 8| |k_reg_304 | 9| 2| 4| 8| |tempA_address0 | 15| 3| 6| 18| |tempB_address0 | 15| 3| 6| 18| |tempResult_address0 | 15| 3| 6| 18| |tempResult_load_1_reg_291 | 9| 2| 32| 64| +----------------------------------+-----+-----------+-----+-----------+ |Total | 408| 89| 144| 367| +----------------------------------+-----+-----------+-----+-----------+ * Register: +------------------------------------+----+----+-----+-----------+ | Name | FF | LUT| Bits| Const Bits| +------------------------------------+----+----+-----+-----------+ |A1_reg_552 | 30| 0| 30| 0| |B3_reg_547 | 30| 0| 30| 0| |ap_CS_fsm | 30| 0| 30| 0| |ap_enable_reg_pp0_iter0 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter1 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter2 | 1| 0| 1| 0| |ap_enable_reg_pp1_iter0 | 1| 0| 1| 0| |ap_enable_reg_pp1_iter1 | 1| 0| 1| 0| |ap_enable_reg_pp1_iter2 | 1| 0| 1| 0| |ap_enable_reg_pp2_iter0 | 1| 0| 1| 0| |ap_enable_reg_pp2_iter1 | 1| 0| 1| 0| |ap_enable_reg_pp2_iter2 | 1| 0| 1| 0| |ap_reg_ioackin_gmem_ARREADY | 1| 0| 1| 0| |ap_reg_ioackin_gmem_AWREADY | 1| 0| 1| 0| |ap_reg_ioackin_gmem_WREADY | 1| 0| 1| 0| |ap_reg_pp0_iter1_exitcond3_reg_575 | 1| 0| 1| 0| |ap_reg_pp0_iter1_indvar_reg_245 | 7| 0| 7| 0| |ap_reg_pp1_iter1_exitcond4_reg_589 | 1| 0| 1| 0| |ap_reg_pp1_iter1_indvar9_reg_257 | 7| 0| 7| 0| |ap_reg_pp2_iter1_exitcond5_reg_674 | 1| 0| 1| 0| |exitcond3_reg_575 | 1| 0| 1| 0| |exitcond4_reg_589 | 1| 0| 1| 0| |exitcond5_reg_674 | 1| 0| 1| 0| |gmem_addr_1_read_reg_598 | 32| 0| 32| 0| |gmem_addr_1_reg_569 | 30| 0| 32| 2| |gmem_addr_2_read_reg_584 | 32| 0| 32| 0| |gmem_addr_reg_563 | 30| 0| 32| 2| |i_1_reg_607 | 4| 0| 4| 0| |i_reg_269 | 4| 0| 4| 0| |indvar1_reg_315 | 7| 0| 7| 0| |indvar9_reg_257 | 7| 0| 7| 0| |indvar_next1_reg_593 | 7| 0| 7| 0| |indvar_next_reg_579 | 7| 0| 7| 0| |indvar_reg_245 | 7| 0| 7| 0| |j_1_reg_626 | 4| 0| 4| 0| |j_cast3_reg_618 | 4| 0| 6| 2| |j_reg_280 | 4| 0| 4| 0| |k_1_reg_639 | 4| 0| 4| 0| |k_reg_304 | 4| 0| 4| 0| |result5_reg_542 | 30| 0| 30| 0| |tempA_load_reg_654 | 32| 0| 32| 0| |tempB_load_reg_659 | 32| 0| 32| 0| |tempResult_addr_1_reg_631 | 6| 0| 6| 0| |tempResult_load_1_reg_291 | 32| 0| 32| 0| |tempResult_load_reg_688 | 32| 0| 32| 0| |tmp_10_reg_664 | 32| 0| 32| 0| |tmp_2_reg_612 | 3| 0| 6| 3| +------------------------------------+----+----+-----+-----------+ |Total | 508| 0| 517| 9| +------------------------------------+----+----+-----+-----------+ ================================================================ == Interface ================================================================ * Summary: +------------------------+-----+-----+------------+--------------+--------------+ | RTL Ports | Dir | Bits| Protocol | Source Object| C Type | +------------------------+-----+-----+------------+--------------+--------------+ |s_axi_AXILiteS_AWVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_AWREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_AWADDR | in | 6| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WDATA | in | 32| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WSTRB | in | 4| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARADDR | in | 6| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RVALID | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RREADY | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RDATA | out | 32| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RRESP | out | 2| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BVALID | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BREADY | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BRESP | out | 2| s_axi | AXILiteS | scalar | |ap_clk | in | 1| ap_ctrl_hs | matrix_mult | return value | |ap_rst_n | in | 1| ap_ctrl_hs | matrix_mult | return value | |interrupt | out | 1| ap_ctrl_hs | matrix_mult | return value | |m_axi_gmem_AWVALID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_AWREADY | in | 1| m_axi | gmem | pointer | |m_axi_gmem_AWADDR | out | 32| m_axi | gmem | pointer | |m_axi_gmem_AWID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_AWLEN | out | 8| m_axi | gmem | pointer | |m_axi_gmem_AWSIZE | out | 3| m_axi | gmem | pointer | |m_axi_gmem_AWBURST | out | 2| m_axi | gmem | pointer | |m_axi_gmem_AWLOCK | out | 2| m_axi | gmem | pointer | |m_axi_gmem_AWCACHE | out | 4| m_axi | gmem | pointer | |m_axi_gmem_AWPROT | out | 3| m_axi | gmem | pointer | |m_axi_gmem_AWQOS | out | 4| m_axi | gmem | pointer | |m_axi_gmem_AWREGION | out | 4| m_axi | gmem | pointer | |m_axi_gmem_AWUSER | out | 1| m_axi | gmem | pointer | |m_axi_gmem_WVALID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_WREADY | in | 1| m_axi | gmem | pointer | |m_axi_gmem_WDATA | out | 32| m_axi | gmem | pointer | |m_axi_gmem_WSTRB | out | 4| m_axi | gmem | pointer | |m_axi_gmem_WLAST | out | 1| m_axi | gmem | pointer | |m_axi_gmem_WID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_WUSER | out | 1| m_axi | gmem | pointer | |m_axi_gmem_ARVALID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_ARREADY | in | 1| m_axi | gmem | pointer | |m_axi_gmem_ARADDR | out | 32| m_axi | gmem | pointer | |m_axi_gmem_ARID | out | 1| m_axi | gmem | pointer | |m_axi_gmem_ARLEN | out | 8| m_axi | gmem | pointer | |m_axi_gmem_ARSIZE | out | 3| m_axi | gmem | pointer | |m_axi_gmem_ARBURST | out | 2| m_axi | gmem | pointer | |m_axi_gmem_ARLOCK | out | 2| m_axi | gmem | pointer | |m_axi_gmem_ARCACHE | out | 4| m_axi | gmem | pointer | |m_axi_gmem_ARPROT | out | 3| m_axi | gmem | pointer | |m_axi_gmem_ARQOS | out | 4| m_axi | gmem | pointer | |m_axi_gmem_ARREGION | out | 4| m_axi | gmem | pointer | |m_axi_gmem_ARUSER | out | 1| m_axi | gmem | pointer | |m_axi_gmem_RVALID | in | 1| m_axi | gmem | pointer | |m_axi_gmem_RREADY | out | 1| m_axi | gmem | pointer | |m_axi_gmem_RDATA | in | 32| m_axi | gmem | pointer | |m_axi_gmem_RLAST | in | 1| m_axi | gmem | pointer | |m_axi_gmem_RID | in | 1| m_axi | gmem | pointer | |m_axi_gmem_RUSER | in | 1| m_axi | gmem | pointer | |m_axi_gmem_RRESP | in | 2| m_axi | gmem | pointer | |m_axi_gmem_BVALID | in | 1| m_axi | gmem | pointer | |m_axi_gmem_BREADY | out | 1| m_axi | gmem | pointer | |m_axi_gmem_BRESP | in | 2| m_axi | gmem | pointer | |m_axi_gmem_BID | in | 1| m_axi | gmem | pointer | |m_axi_gmem_BUSER | in | 1| m_axi | gmem | pointer | +------------------------+-----+-----+------------+--------------+--------------+