Folder Path
/
MSc
/
HLS-FPGA
/
edge_detection_hw
/
edge_detection_hw.srcs
/
sources_1
/
bd
/
design_1
/
ip
/
5
directories
0
files
0 B
total
List
Grid
Name
Size
Modified
Up
design_1_auto_pc_0/
—
05/17/2022 08:16:46 PM +00:00
design_1_conv_stream_0_1/
—
05/17/2022 08:16:47 PM +00:00
design_1_processing_system7_0_1/
—
05/17/2022 08:16:48 PM +00:00
design_1_ps7_0_axi_periph_0/
—
05/17/2022 08:16:48 PM +00:00
design_1_rst_ps7_0_100M_0/
—
05/17/2022 08:16:48 PM +00:00