Folder Path

/MSc/HLS-FPGA/edge_detection_hw/edge_detection_hw.srcs/sources_1/bd/design_1/

7 directories 3 files 76 KiB total

	Name	Size	Modified
	Up
	hdl/	—	05/17/2022 08:16:46 PM +00:00
	hw_handoff/	—	05/17/2022 08:16:46 PM +00:00
	ip/	—	05/17/2022 08:16:48 PM +00:00
	ipshared/	—	05/17/2022 08:16:50 PM +00:00
	sim/	—	05/17/2022 08:16:50 PM +00:00
	synth/	—	05/17/2022 08:16:50 PM +00:00
	ui/	—	05/17/2022 08:16:50 PM +00:00
	design_1.bd	71 KiB	05/17/2022 08:16:46 PM +00:00
	design_1.bxml	4.3 KiB	05/17/2022 08:16:46 PM +00:00
	design_1_ooc.xdc	653 B	05/17/2022 08:16:46 PM +00:00