Folder Path
/
MSc
/
HLS-FPGA
/
edge_detection_hw
/
edge_detection_hw.cache
/
ip
/
2017.4
/
f8a3979c5d63192c
/
0
directories
6
files
13 MiB
total
List
Grid
Name
Size
Modified
Up
design_1_conv_stream_0_1.dcp
2.5 MiB
05/17/2022 08:16:32 PM +00:00
design_1_conv_stream_0_1_sim_netlist.v
4.4 MiB
05/17/2022 08:16:31 PM +00:00
design_1_conv_stream_0_1_sim_netlist.vhdl
6.3 MiB
05/17/2022 08:16:32 PM +00:00
design_1_conv_stream_0_1_stub.v
8.5 KiB
05/17/2022 08:16:31 PM +00:00
design_1_conv_stream_0_1_stub.vhdl
8.4 KiB
05/17/2022 08:16:31 PM +00:00
f8a3979c5d63192c.xci
8.1 KiB
05/17/2022 08:16:31 PM +00:00