Folder Path
/
MSc
/
HLS-FPGA
/
edge_detection_hw
/
edge_detection_hw.cache
/
ip
/
2017.4
/
bf406d6b1e52f1f1
/
0
directories
6
files
89 KiB
total
List
Grid
Name
Size
Modified
Up
bf406d6b1e52f1f1.xci
4.9 KiB
05/17/2022 08:16:31 PM +00:00
design_1_rst_ps7_0_100M_0.dcp
21 KiB
05/17/2022 08:16:31 PM +00:00
design_1_rst_ps7_0_100M_0_sim_netlist.v
25 KiB
05/17/2022 08:16:31 PM +00:00
design_1_rst_ps7_0_100M_0_sim_netlist.vhdl
35 KiB
05/17/2022 08:16:31 PM +00:00
design_1_rst_ps7_0_100M_0_stub.v
1.8 KiB
05/17/2022 08:16:31 PM +00:00
design_1_rst_ps7_0_100M_0_stub.vhdl
1.9 KiB
05/17/2022 08:16:31 PM +00:00