================================================================ == Vivado HLS Report for 'convolution' ================================================================ * Date: Fri May 25 14:09:47 2018 * Version: 2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017) * Project: edge_detection * Solution: solution2 * Product family: zynq * Target device: xc7z020clg484-1 ================================================================ == Performance Estimates ================================================================ + Timing (ns): * Summary: +--------+-------+----------+------------+ | Clock | Target| Estimated| Uncertainty| +--------+-------+----------+------------+ |ap_clk | 10.00| 8.51| 1.25| +--------+-------+----------+------------+ + Latency (clock cycles): * Summary: +---------+---------+---------+---------+---------+ | Latency | Interval | Pipeline| | min | max | min | max | Type | +---------+---------+---------+---------+---------+ | 3494765| 3494765| 3494765| 3494765| none | +---------+---------+---------+---------+---------+ + Detail: * Instance: N/A * Loop: +---------------------+---------+---------+----------+-----------+-----------+------+----------+ | | Latency | Iteration| Initiation Interval | Trip | | | Loop Name | min | max | Latency | achieved | target | Count| Pipelined| +---------------------+---------+---------+----------+-----------+-----------+------+----------+ |- Loop 1 | 3494764| 3494764| 38404| -| -| 91| no | | + Loop 1.1 | 38402| 38402| 422| -| -| 91| no | | ++ Loop 1.1.1 | 420| 420| 42| -| -| 10| no | | +++ Loop 1.1.1.1 | 40| 40| 4| -| -| 10| no | +---------------------+---------+---------+----------+-----------+-----------+------+----------+ ================================================================ == Utilization Estimates ================================================================ * Summary: +-----------------+---------+-------+--------+-------+ | Name | BRAM_18K| DSP48E| FF | LUT | +-----------------+---------+-------+--------+-------+ |DSP | -| -| -| -| |Expression | -| 3| 0| 303| |FIFO | -| -| -| -| |Instance | 66| -| 276| 250| |Memory | -| -| -| -| |Multiplexer | -| -| -| 119| |Register | -| -| 217| -| +-----------------+---------+-------+--------+-------+ |Total | 66| 3| 493| 672| +-----------------+---------+-------+--------+-------+ |Available | 280| 220| 106400| 53200| +-----------------+---------+-------+--------+-------+ |Utilization (%) | 23| 1| ~0 | 1| +-----------------+---------+-------+--------+-------+ + Detail: * Instance: +------------------------------+----------------------------+---------+-------+-----+-----+ | Instance | Module | BRAM_18K| DSP48E| FF | LUT | +------------------------------+----------------------------+---------+-------+-----+-----+ |convolution_AXILiteS_s_axi_U |convolution_AXILiteS_s_axi | 66| 0| 276| 250| +------------------------------+----------------------------+---------+-------+-----+-----+ |Total | | 66| 0| 276| 250| +------------------------------+----------------------------+---------+-------+-----+-----+ * DSP48: N/A * Memory: N/A * FIFO: N/A * Expression: +---------------------+----------+-------+---+----+------------+------------+ | Variable Name | Operation| DSP48E| FF| LUT| Bitwidth P0| Bitwidth P1| +---------------------+----------+-------+---+----+------------+------------+ |tmp_6_fu_231_p2 | * | 0| 0| 33| 7| 7| |tmp_7_fu_307_p2 | * | 3| 0| 20| 32| 32| |i_1_fu_172_p2 | + | 0| 0| 15| 7| 1| |j_1_fu_188_p2 | + | 0| 0| 15| 7| 1| |k_1_fu_215_p2 | + | 0| 0| 13| 4| 1| |l_1_fu_267_p2 | + | 0| 0| 13| 4| 1| |next_mul_fu_160_p2 | + | 0| 0| 21| 14| 7| |tmp1_fu_273_p2 | + | 0| 0| 14| 14| 14| |tmp2_fu_288_p2 | + | 0| 0| 15| 5| 5| |tmp_2_fu_194_p2 | + | 0| 0| 21| 14| 14| |tmp_4_fu_297_p2 | + | 0| 0| 15| 7| 7| |tmp_5_fu_221_p2 | + | 0| 0| 15| 7| 7| |tmp_9_fu_311_p2 | + | 0| 0| 39| 32| 32| |tmp_s_fu_278_p2 | + | 0| 0| 14| 14| 14| |exitcond1_fu_209_p2 | icmp | 0| 0| 9| 4| 4| |exitcond2_fu_182_p2 | icmp | 0| 0| 11| 7| 7| |exitcond3_fu_166_p2 | icmp | 0| 0| 11| 7| 7| |exitcond_fu_261_p2 | icmp | 0| 0| 9| 4| 4| +---------------------+----------+-------+---+----+------------+------------+ |Total | | 3| 0| 303| 190| 165| +---------------------+----------+-------+---+----+------------+------------+ * Multiplexer: +-----------------+----+-----------+-----+-----------+ | Name | LUT| Input Size| Bits| Total Bits| +-----------------+----+-----------+-----+-----------+ |C_address0 | 15| 3| 14| 42| |C_d0 | 15| 3| 32| 96| |ap_NS_fsm | 44| 9| 1| 9| |i_reg_103 | 9| 2| 7| 14| |j_reg_127 | 9| 2| 7| 14| |k_reg_138 | 9| 2| 4| 8| |l_reg_149 | 9| 2| 4| 8| |phi_mul_reg_115 | 9| 2| 14| 28| +-----------------+----+-----------+-----+-----------+ |Total | 119| 25| 83| 219| +-----------------+----+-----------+-----+-----------+ * Register: +------------------+----+----+-----+-----------+ | Name | FF | LUT| Bits| Const Bits| +------------------+----+----+-----+-----------+ |A_load_reg_389 | 32| 0| 32| 0| |B_load_reg_394 | 32| 0| 32| 0| |C_addr_reg_343 | 14| 0| 14| 0| |ap_CS_fsm | 8| 0| 8| 0| |i_1_reg_325 | 7| 0| 7| 0| |i_reg_103 | 7| 0| 7| 0| |j_1_reg_338 | 7| 0| 7| 0| |j_cast5_reg_330 | 7| 0| 14| 7| |j_reg_127 | 7| 0| 7| 0| |k_1_reg_351 | 4| 0| 4| 0| |k_reg_138 | 4| 0| 4| 0| |l_1_reg_374 | 4| 0| 4| 0| |l_reg_149 | 4| 0| 4| 0| |next_mul_reg_317 | 14| 0| 14| 0| |p_shl8_reg_366 | 4| 0| 5| 1| |p_shl_reg_361 | 4| 0| 7| 3| |phi_mul_reg_115 | 14| 0| 14| 0| |tmp_6_reg_356 | 12| 0| 14| 2| |tmp_7_reg_399 | 32| 0| 32| 0| +------------------+----+----+-----+-----------+ |Total | 217| 0| 230| 13| +------------------+----+----+-----+-----------+ ================================================================ == Interface ================================================================ * Summary: +------------------------+-----+-----+------------+--------------+--------------+ | RTL Ports | Dir | Bits| Protocol | Source Object| C Type | +------------------------+-----+-----+------------+--------------+--------------+ |s_axi_AXILiteS_AWVALID | in | 1| s_axi | AXILiteS | array | |s_axi_AXILiteS_AWREADY | out | 1| s_axi | AXILiteS | array | |s_axi_AXILiteS_AWADDR | in | 18| s_axi | AXILiteS | array | |s_axi_AXILiteS_WVALID | in | 1| s_axi | AXILiteS | array | |s_axi_AXILiteS_WREADY | out | 1| s_axi | AXILiteS | array | |s_axi_AXILiteS_WDATA | in | 32| s_axi | AXILiteS | array | |s_axi_AXILiteS_WSTRB | in | 4| s_axi | AXILiteS | array | |s_axi_AXILiteS_ARVALID | in | 1| s_axi | AXILiteS | array | |s_axi_AXILiteS_ARREADY | out | 1| s_axi | AXILiteS | array | |s_axi_AXILiteS_ARADDR | in | 18| s_axi | AXILiteS | array | |s_axi_AXILiteS_RVALID | out | 1| s_axi | AXILiteS | array | |s_axi_AXILiteS_RREADY | in | 1| s_axi | AXILiteS | array | |s_axi_AXILiteS_RDATA | out | 32| s_axi | AXILiteS | array | |s_axi_AXILiteS_RRESP | out | 2| s_axi | AXILiteS | array | |s_axi_AXILiteS_BVALID | out | 1| s_axi | AXILiteS | array | |s_axi_AXILiteS_BREADY | in | 1| s_axi | AXILiteS | array | |s_axi_AXILiteS_BRESP | out | 2| s_axi | AXILiteS | array | |ap_clk | in | 1| ap_ctrl_hs | convolution | return value | |ap_rst_n | in | 1| ap_ctrl_hs | convolution | return value | |interrupt | out | 1| ap_ctrl_hs | convolution | return value | +------------------------+-----+-----+------------+--------------+--------------+