Folder Path
/
MSc
/
HLS-FPGA
/
edge_detection
/
solution2
/
sim
/
vhdl
/
xsim.dir
/
xil_defaultlib
/
0
directories
7
files
503 KiB
total
List
Grid
Name
Size
Modified
Up
aesl_axi_slave_axilites.vdb
208 KiB
05/17/2022 08:15:59 PM +00:00
aesl_sim_components.vdb
29 KiB
05/17/2022 08:15:59 PM +00:00
apatb_convolution_top.vdb
114 KiB
05/17/2022 08:15:59 PM +00:00
convolution.vdb
76 KiB
05/17/2022 08:15:59 PM +00:00
convolution_axilites_s_axi.vdb
63 KiB
05/17/2022 08:15:59 PM +00:00
convolution_axilites_s_axi_ram.vdb
11 KiB
05/17/2022 08:15:59 PM +00:00
xil_defaultlib.rlx
1.8 KiB
05/17/2022 08:15:59 PM +00:00