================================================================
== Vivado HLS Report for 'convolution'
================================================================
* Date:           Fri May 25 14:09:47 2018

* Version:        2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017)
* Project:        edge_detection
* Solution:       solution2
* Product family: zynq
* Target device:  xc7z020clg484-1


================================================================
== Performance Estimates
================================================================
+ Timing (ns): 
    * Summary: 
    +--------+-------+----------+------------+
    |  Clock | Target| Estimated| Uncertainty|
    +--------+-------+----------+------------+
    |ap_clk  |  10.00|      8.51|        1.25|
    +--------+-------+----------+------------+

+ Latency (clock cycles): 
    * Summary: 
    +---------+---------+---------+---------+---------+
    |      Latency      |      Interval     | Pipeline|
    |   min   |   max   |   min   |   max   |   Type  |
    +---------+---------+---------+---------+---------+
    |  3494765|  3494765|  3494765|  3494765|   none  |
    +---------+---------+---------+---------+---------+

    + Detail: 
        * Instance: 
        N/A

        * Loop: 
        +---------------------+---------+---------+----------+-----------+-----------+------+----------+
        |                     |      Latency      | Iteration|  Initiation Interval  | Trip |          |
        |      Loop Name      |   min   |   max   |  Latency |  achieved |   target  | Count| Pipelined|
        +---------------------+---------+---------+----------+-----------+-----------+------+----------+
        |- Loop 1             |  3494764|  3494764|     38404|          -|          -|    91|    no    |
        | + Loop 1.1          |    38402|    38402|       422|          -|          -|    91|    no    |
        |  ++ Loop 1.1.1      |      420|      420|        42|          -|          -|    10|    no    |
        |   +++ Loop 1.1.1.1  |       40|       40|         4|          -|          -|    10|    no    |
        +---------------------+---------+---------+----------+-----------+-----------+------+----------+

============================================================
+ Verbose Summary: Synthesis Manager
============================================================
InlineROM: 1
ExposeGlobal: 0
============================================================
+ Verbose Summary: CDFG Model
============================================================
IsTopModel: 1
ResetActiveHigh: 1
IsCombinational: 0
IsDatapathOnly: 0
HasWiredReturn: 1
HasMFsm: 0
HasVarLatency: 1
IsPipeline: 0
IsRtlPipelined: 0
IsInstanceOverlapped: 0
IsDontTouch: 0
HasImplIP: 0
IsGatedGlobalClock: 0


============================================================
+ Verbose Summary: Schedule
============================================================
* Number of FSM states : 8
* Pipeline : 0
* Dataflow Pipeline: 0

* FSM state transitions: 
1 --> 
	2  / true
2 --> 
	3  / (!exitcond3)
3 --> 
	4  / (!exitcond2)
	2  / (exitcond2)
4 --> 
	5  / (!exitcond1)
	3  / (exitcond1)
5 --> 
	6  / (!exitcond)
	4  / (exitcond)
6 --> 
	7  / true
7 --> 
	8  / true
8 --> 
	5  / true

* FSM state operations: 

 <State 1> : 1.77ns
ST_1 : Operation 9 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecBitsMap([10000 x i32]* %A) nounwind, !map !7"
ST_1 : Operation 10 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecBitsMap([100 x i32]* %B) nounwind, !map !13"
ST_1 : Operation 11 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecBitsMap([8281 x i32]* %C) nounwind, !map !19"
ST_1 : Operation 12 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecTopModule([12 x i8]* @convolution_str) nounwind"
ST_1 : Operation 13 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(i32 0, [10 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1, [1 x i8]* @p_str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1) nounwind" [edge_detection/edge_detection.cpp:10]
ST_1 : Operation 14 [1/1] (0.00ns)   --->   "%empty = call i32 (...)* @_ssdm_op_SpecMemCore([8281 x i32]* %C, [1 x i8]* @p_str5, [7 x i8]* @RAM_1P_str, [1 x i8]* @p_str5, i32 -1, [1 x i8]* @p_str5, [1 x i8]* @p_str5, [1 x i8]* @p_str5, [1 x i8]* @p_str5, [1 x i8]* @p_str5) nounwind"
ST_1 : Operation 15 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface([8281 x i32]* %C, [10 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1, [1 x i8]* @p_str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1) nounwind"
ST_1 : Operation 16 [1/1] (0.00ns)   --->   "%empty_2 = call i32 (...)* @_ssdm_op_SpecMemCore([100 x i32]* %B, [1 x i8]* @p_str4, [7 x i8]* @RAM_1P_str, [1 x i8]* @p_str4, i32 -1, [1 x i8]* @p_str4, [1 x i8]* @p_str4, [1 x i8]* @p_str4, [1 x i8]* @p_str4, [1 x i8]* @p_str4) nounwind"
ST_1 : Operation 17 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface([100 x i32]* %B, [10 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1, [1 x i8]* @p_str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1) nounwind"
ST_1 : Operation 18 [1/1] (0.00ns)   --->   "%empty_3 = call i32 (...)* @_ssdm_op_SpecMemCore([10000 x i32]* %A, [1 x i8]* @p_str3, [7 x i8]* @RAM_1P_str, [1 x i8]* @p_str3, i32 -1, [1 x i8]* @p_str3, [1 x i8]* @p_str3, [1 x i8]* @p_str3, [1 x i8]* @p_str3, [1 x i8]* @p_str3) nounwind"
ST_1 : Operation 19 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface([10000 x i32]* %A, [10 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1, [1 x i8]* @p_str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1) nounwind"
ST_1 : Operation 20 [1/1] (1.76ns)   --->   "br label %.loopexit1" [edge_detection/edge_detection.cpp:10]

 <State 2> : 2.04ns
ST_2 : Operation 21 [1/1] (0.00ns)   --->   "%i = phi i7 [ 0, %0 ], [ %i_1, %.loopexit1.loopexit ]"
ST_2 : Operation 22 [1/1] (0.00ns)   --->   "%phi_mul = phi i14 [ 0, %0 ], [ %next_mul, %.loopexit1.loopexit ]"
ST_2 : Operation 23 [1/1] (2.03ns)   --->   "%next_mul = add i14 %phi_mul, 91"   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.55> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_2 : Operation 24 [1/1] (1.48ns)   --->   "%exitcond3 = icmp eq i7 %i, -37" [edge_detection/edge_detection.cpp:10]   --->   Core 25 'Cmp' <Latency = 0> <II = 1> <Delay = 1.30> <FuncUnit> <Opcode : 'icmp'> <InPorts = 2> <OutPorts = 1>
ST_2 : Operation 25 [1/1] (0.00ns)   --->   "%empty_4 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 91, i64 91, i64 91) nounwind"
ST_2 : Operation 26 [1/1] (1.87ns)   --->   "%i_1 = add i7 %i, 1" [edge_detection/edge_detection.cpp:10]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.55> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_2 : Operation 27 [1/1] (0.00ns)   --->   "br i1 %exitcond3, label %3, label %.preheader4.preheader" [edge_detection/edge_detection.cpp:10]
ST_2 : Operation 28 [1/1] (1.76ns)   --->   "br label %.preheader4" [edge_detection/edge_detection.cpp:11]
ST_2 : Operation 29 [1/1] (0.00ns)   --->   "ret void" [edge_detection/edge_detection.cpp:20]

 <State 3> : 4.60ns
ST_3 : Operation 30 [1/1] (0.00ns)   --->   "%j = phi i7 [ %j_1, %.preheader4.loopexit ], [ 0, %.preheader4.preheader ]"
ST_3 : Operation 31 [1/1] (0.00ns)   --->   "%j_cast5 = zext i7 %j to i14" [edge_detection/edge_detection.cpp:11]
ST_3 : Operation 32 [1/1] (1.48ns)   --->   "%exitcond2 = icmp eq i7 %j, -37" [edge_detection/edge_detection.cpp:11]   --->   Core 25 'Cmp' <Latency = 0> <II = 1> <Delay = 1.30> <FuncUnit> <Opcode : 'icmp'> <InPorts = 2> <OutPorts = 1>
ST_3 : Operation 33 [1/1] (0.00ns)   --->   "%empty_5 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 91, i64 91, i64 91) nounwind"
ST_3 : Operation 34 [1/1] (1.87ns)   --->   "%j_1 = add i7 %j, 1" [edge_detection/edge_detection.cpp:11]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.55> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_3 : Operation 35 [1/1] (0.00ns)   --->   "br i1 %exitcond2, label %.loopexit1.loopexit, label %1" [edge_detection/edge_detection.cpp:11]
ST_3 : Operation 36 [1/1] (2.03ns)   --->   "%tmp_2 = add i14 %phi_mul, %j_cast5" [edge_detection/edge_detection.cpp:12]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.55> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_3 : Operation 37 [1/1] (0.00ns)   --->   "%tmp_3 = zext i14 %tmp_2 to i64" [edge_detection/edge_detection.cpp:12]
ST_3 : Operation 38 [1/1] (0.00ns)   --->   "%C_addr = getelementptr [8281 x i32]* %C, i64 0, i64 %tmp_3" [edge_detection/edge_detection.cpp:12]
ST_3 : Operation 39 [1/1] (2.56ns)   --->   "store i32 0, i32* %C_addr, align 4" [edge_detection/edge_detection.cpp:12]   --->   Core 42 'RAM_1P' <Latency = 1> <II = 1> <Delay = 2.56> <Storage> <Opcode : 'load' 'store'> <Ports = 1> <Width = 32> <Depth = 8281> <RAM>
ST_3 : Operation 40 [1/1] (1.76ns)   --->   "br label %.loopexit" [edge_detection/edge_detection.cpp:13]
ST_3 : Operation 41 [1/1] (0.00ns)   --->   "br label %.loopexit1"

 <State 4> : 6.04ns
ST_4 : Operation 42 [1/1] (0.00ns)   --->   "%k = phi i4 [ 0, %1 ], [ %k_1, %.loopexit.loopexit ]"
ST_4 : Operation 43 [1/1] (0.00ns)   --->   "%k_cast4 = zext i4 %k to i7" [edge_detection/edge_detection.cpp:13]
ST_4 : Operation 44 [1/1] (1.30ns)   --->   "%exitcond1 = icmp eq i4 %k, -6" [edge_detection/edge_detection.cpp:13]   --->   Core 25 'Cmp' <Latency = 0> <II = 1> <Delay = 1.30> <FuncUnit> <Opcode : 'icmp'> <InPorts = 2> <OutPorts = 1>
ST_4 : Operation 45 [1/1] (0.00ns)   --->   "%empty_6 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 10, i64 10, i64 10) nounwind"
ST_4 : Operation 46 [1/1] (1.73ns)   --->   "%k_1 = add i4 %k, 1" [edge_detection/edge_detection.cpp:13]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.55> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_4 : Operation 47 [1/1] (0.00ns)   --->   "br i1 %exitcond1, label %.preheader4.loopexit, label %.preheader.preheader" [edge_detection/edge_detection.cpp:13]
ST_4 : Operation 48 [1/1] (1.87ns)   --->   "%tmp_5 = add i7 %k_cast4, %i" [edge_detection/edge_detection.cpp:15]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.55> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_4 : Operation 49 [1/1] (0.00ns)   --->   "%tmp_5_cast_cast = zext i7 %tmp_5 to i14" [edge_detection/edge_detection.cpp:15]
ST_4 : Operation 50 [1/1] (4.17ns)   --->   "%tmp_6 = mul i14 %tmp_5_cast_cast, 100" [edge_detection/edge_detection.cpp:15]   --->   Core 16 'Mul' <Latency = 0> <II = 1> <Delay = 8.51> <FuncUnit> <Opcode : 'mul'> <InPorts = 2> <OutPorts = 1>
ST_4 : Operation 51 [1/1] (0.00ns)   --->   "%p_shl = call i7 @_ssdm_op_BitConcatenate.i7.i4.i3(i4 %k, i3 0)" [edge_detection/edge_detection.cpp:15]
ST_4 : Operation 52 [1/1] (0.00ns)   --->   "%p_shl8 = call i5 @_ssdm_op_BitConcatenate.i5.i4.i1(i4 %k, i1 false)" [edge_detection/edge_detection.cpp:15]
ST_4 : Operation 53 [1/1] (1.76ns)   --->   "br label %.preheader" [edge_detection/edge_detection.cpp:14]
ST_4 : Operation 54 [1/1] (0.00ns)   --->   "br label %.preheader4"

 <State 5> : 6.41ns
ST_5 : Operation 55 [1/1] (0.00ns)   --->   "%l = phi i4 [ %l_1, %2 ], [ 0, %.preheader.preheader ]"
ST_5 : Operation 56 [1/1] (0.00ns)   --->   "%l_cast3 = zext i4 %l to i14" [edge_detection/edge_detection.cpp:14]
ST_5 : Operation 57 [1/1] (0.00ns)   --->   "%l_cast = zext i4 %l to i5" [edge_detection/edge_detection.cpp:14]
ST_5 : Operation 58 [1/1] (1.30ns)   --->   "%exitcond = icmp eq i4 %l, -6" [edge_detection/edge_detection.cpp:14]   --->   Core 25 'Cmp' <Latency = 0> <II = 1> <Delay = 1.30> <FuncUnit> <Opcode : 'icmp'> <InPorts = 2> <OutPorts = 1>
ST_5 : Operation 59 [1/1] (0.00ns)   --->   "%empty_7 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 10, i64 10, i64 10) nounwind"
ST_5 : Operation 60 [1/1] (1.73ns)   --->   "%l_1 = add i4 %l, 1" [edge_detection/edge_detection.cpp:14]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.55> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_5 : Operation 61 [1/1] (0.00ns)   --->   "br i1 %exitcond, label %.loopexit.loopexit, label %2" [edge_detection/edge_detection.cpp:14]
ST_5 : Operation 62 [1/1] (0.00ns) (grouped into TernaryAdder)   --->   "%tmp1 = add i14 %tmp_6, %l_cast3" [edge_detection/edge_detection.cpp:15]   --->   Core 80 'TAddSub' <Latency = 0> <II = 1> <Delay = 1.92> <IPBlock> <Opcode : 'add' 'sub'> <InPorts = 3> <OutPorts = 1> <Sync> <CReg>
ST_5 : Operation 63 [1/1] (3.84ns) (root node of TernaryAdder)   --->   "%tmp_s = add i14 %tmp1, %j_cast5" [edge_detection/edge_detection.cpp:15]   --->   Core 80 'TAddSub' <Latency = 0> <II = 1> <Delay = 1.92> <IPBlock> <Opcode : 'add' 'sub'> <InPorts = 3> <OutPorts = 1> <Sync> <CReg>
ST_5 : Operation 64 [1/1] (0.00ns)   --->   "%tmp_1 = zext i14 %tmp_s to i64" [edge_detection/edge_detection.cpp:15]
ST_5 : Operation 65 [1/1] (0.00ns)   --->   "%A_addr = getelementptr [10000 x i32]* %A, i64 0, i64 %tmp_1" [edge_detection/edge_detection.cpp:15]
ST_5 : Operation 66 [2/2] (2.56ns)   --->   "%A_load = load i32* %A_addr, align 4" [edge_detection/edge_detection.cpp:15]   --->   Core 42 'RAM_1P' <Latency = 1> <II = 1> <Delay = 2.56> <Storage> <Opcode : 'load' 'store'> <Ports = 1> <Width = 32> <Depth = 8281> <RAM>
ST_5 : Operation 67 [1/1] (1.78ns)   --->   "%tmp2 = add i5 %p_shl8, %l_cast" [edge_detection/edge_detection.cpp:15]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.55> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_5 : Operation 68 [1/1] (0.00ns)   --->   "%tmp2_cast = zext i5 %tmp2 to i7" [edge_detection/edge_detection.cpp:15]
ST_5 : Operation 69 [1/1] (1.87ns)   --->   "%tmp_4 = add i7 %tmp2_cast, %p_shl" [edge_detection/edge_detection.cpp:15]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.55> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_5 : Operation 70 [1/1] (0.00ns)   --->   "%tmp_8 = zext i7 %tmp_4 to i64" [edge_detection/edge_detection.cpp:15]
ST_5 : Operation 71 [1/1] (0.00ns)   --->   "%B_addr = getelementptr [100 x i32]* %B, i64 0, i64 %tmp_8" [edge_detection/edge_detection.cpp:15]
ST_5 : Operation 72 [2/2] (2.30ns)   --->   "%B_load = load i32* %B_addr, align 4" [edge_detection/edge_detection.cpp:15]   --->   Core 42 'RAM_1P' <Latency = 1> <II = 1> <Delay = 2.56> <Storage> <Opcode : 'load' 'store'> <Ports = 1> <Width = 32> <Depth = 8281> <RAM>
ST_5 : Operation 73 [1/1] (0.00ns)   --->   "br label %.loopexit"

 <State 6> : 2.57ns
ST_6 : Operation 74 [1/2] (2.56ns)   --->   "%A_load = load i32* %A_addr, align 4" [edge_detection/edge_detection.cpp:15]   --->   Core 42 'RAM_1P' <Latency = 1> <II = 1> <Delay = 2.56> <Storage> <Opcode : 'load' 'store'> <Ports = 1> <Width = 32> <Depth = 8281> <RAM>
ST_6 : Operation 75 [1/2] (2.30ns)   --->   "%B_load = load i32* %B_addr, align 4" [edge_detection/edge_detection.cpp:15]   --->   Core 42 'RAM_1P' <Latency = 1> <II = 1> <Delay = 2.56> <Storage> <Opcode : 'load' 'store'> <Ports = 1> <Width = 32> <Depth = 8281> <RAM>

 <State 7> : 8.51ns
ST_7 : Operation 76 [1/1] (8.51ns)   --->   "%tmp_7 = mul nsw i32 %A_load, %B_load" [edge_detection/edge_detection.cpp:15]   --->   Core 16 'Mul' <Latency = 0> <II = 1> <Delay = 8.51> <FuncUnit> <Opcode : 'mul'> <InPorts = 2> <OutPorts = 1>
ST_7 : Operation 77 [2/2] (2.56ns)   --->   "%C_load = load i32* %C_addr, align 4" [edge_detection/edge_detection.cpp:15]   --->   Core 42 'RAM_1P' <Latency = 1> <II = 1> <Delay = 2.56> <Storage> <Opcode : 'load' 'store'> <Ports = 1> <Width = 32> <Depth = 8281> <RAM>

 <State 8> : 7.68ns
ST_8 : Operation 78 [1/2] (2.56ns)   --->   "%C_load = load i32* %C_addr, align 4" [edge_detection/edge_detection.cpp:15]   --->   Core 42 'RAM_1P' <Latency = 1> <II = 1> <Delay = 2.56> <Storage> <Opcode : 'load' 'store'> <Ports = 1> <Width = 32> <Depth = 8281> <RAM>
ST_8 : Operation 79 [1/1] (2.55ns)   --->   "%tmp_9 = add nsw i32 %C_load, %tmp_7" [edge_detection/edge_detection.cpp:15]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.55> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_8 : Operation 80 [1/1] (2.56ns)   --->   "store i32 %tmp_9, i32* %C_addr, align 4" [edge_detection/edge_detection.cpp:15]   --->   Core 42 'RAM_1P' <Latency = 1> <II = 1> <Delay = 2.56> <Storage> <Opcode : 'load' 'store'> <Ports = 1> <Width = 32> <Depth = 8281> <RAM>
ST_8 : Operation 81 [1/1] (0.00ns)   --->   "br label %.preheader" [edge_detection/edge_detection.cpp:14]


============================================================
+ Verbose Summary: Binding
============================================================
STG Binding: 
---------------- STG Properties BEGIN ----------------
- Is combinational: 0
- Is one-state seq: 0
- Is datapath-only: 0
- Is pipelined: 0
- Is top level: 1
Port [ Return ] is wired: 1; IO mode=ap_ctrl_hs:ce=0
Port [ A]:  wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=1; pingpong=0; private_global=0; MemPort=[1]; IO mode=ap_memory:ce=0
Port [ B]:  wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=1; pingpong=0; private_global=0; MemPort=[1]; IO mode=ap_memory:ce=0
Port [ C]:  wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=2; type=1; pingpong=0; private_global=0; MemPort=[2]; IO mode=ap_memory:ce=0
---------------- STG Properties END ------------------

---------------- Datapath Model BEGIN ----------------

<LifeTime>
<method=bitvector/>
StgValue_9      (specbitsmap      ) [ 000000000]
StgValue_10     (specbitsmap      ) [ 000000000]
StgValue_11     (specbitsmap      ) [ 000000000]
StgValue_12     (spectopmodule    ) [ 000000000]
StgValue_13     (specinterface    ) [ 000000000]
empty           (specmemcore      ) [ 000000000]
StgValue_15     (specinterface    ) [ 000000000]
empty_2         (specmemcore      ) [ 000000000]
StgValue_17     (specinterface    ) [ 000000000]
empty_3         (specmemcore      ) [ 000000000]
StgValue_19     (specinterface    ) [ 000000000]
StgValue_20     (br               ) [ 011111111]
i               (phi              ) [ 001011111]
phi_mul         (phi              ) [ 001111111]
next_mul        (add              ) [ 011111111]
exitcond3       (icmp             ) [ 001111111]
empty_4         (speclooptripcount) [ 000000000]
i_1             (add              ) [ 011111111]
StgValue_27     (br               ) [ 000000000]
StgValue_28     (br               ) [ 001111111]
StgValue_29     (ret              ) [ 000000000]
j               (phi              ) [ 000100000]
j_cast5         (zext             ) [ 000011111]
exitcond2       (icmp             ) [ 001111111]
empty_5         (speclooptripcount) [ 000000000]
j_1             (add              ) [ 001111111]
StgValue_35     (br               ) [ 000000000]
tmp_2           (add              ) [ 000000000]
tmp_3           (zext             ) [ 000000000]
C_addr          (getelementptr    ) [ 000011111]
StgValue_39     (store            ) [ 000000000]
StgValue_40     (br               ) [ 001111111]
StgValue_41     (br               ) [ 011111111]
k               (phi              ) [ 000010000]
k_cast4         (zext             ) [ 000000000]
exitcond1       (icmp             ) [ 001111111]
empty_6         (speclooptripcount) [ 000000000]
k_1             (add              ) [ 001111111]
StgValue_47     (br               ) [ 000000000]
tmp_5           (add              ) [ 000000000]
tmp_5_cast_cast (zext             ) [ 000000000]
tmp_6           (mul              ) [ 000001111]
p_shl           (bitconcatenate   ) [ 000001111]
p_shl8          (bitconcatenate   ) [ 000001111]
StgValue_53     (br               ) [ 001111111]
StgValue_54     (br               ) [ 001111111]
l               (phi              ) [ 000001000]
l_cast3         (zext             ) [ 000000000]
l_cast          (zext             ) [ 000000000]
exitcond        (icmp             ) [ 001111111]
empty_7         (speclooptripcount) [ 000000000]
l_1             (add              ) [ 001111111]
StgValue_61     (br               ) [ 000000000]
tmp1            (add              ) [ 000000000]
tmp_s           (add              ) [ 000000000]
tmp_1           (zext             ) [ 000000000]
A_addr          (getelementptr    ) [ 000000100]
tmp2            (add              ) [ 000000000]
tmp2_cast       (zext             ) [ 000000000]
tmp_4           (add              ) [ 000000000]
tmp_8           (zext             ) [ 000000000]
B_addr          (getelementptr    ) [ 000000100]
StgValue_73     (br               ) [ 001111111]
A_load          (load             ) [ 000000010]
B_load          (load             ) [ 000000010]
tmp_7           (mul              ) [ 000000001]
C_load          (load             ) [ 000000000]
tmp_9           (add              ) [ 000000000]
StgValue_80     (store            ) [ 000000000]
StgValue_81     (br               ) [ 001111111]
</LifeTime>

<model>

<comp_list>
<comp id="0" class="1000" name="A">
<pin_list>
<pin id="1" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="A"/><MemPortTyVec>1 </MemPortTyVec>
</StgValue>
</bind>
</comp>

<comp id="2" class="1000" name="B">
<pin_list>
<pin id="3" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="B"/><MemPortTyVec>1 </MemPortTyVec>
</StgValue>
</bind>
</comp>

<comp id="4" class="1000" name="C">
<pin_list>
<pin id="5" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="C"/><MemPortTyVec>2 </MemPortTyVec>
</StgValue>
</bind>
</comp>

<comp id="6" class="1001" name="const_6">
<pin_list>
<pin id="7" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecBitsMap"/></StgValue>
</bind>
</comp>

<comp id="8" class="1001" name="const_8">
<pin_list>
<pin id="9" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecTopModule"/></StgValue>
</bind>
</comp>

<comp id="10" class="1001" name="const_10">
<pin_list>
<pin id="11" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="convolution_str"/></StgValue>
</bind>
</comp>

<comp id="12" class="1001" name="const_12">
<pin_list>
<pin id="13" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecInterface"/></StgValue>
</bind>
</comp>

<comp id="14" class="1001" name="const_14">
<pin_list>
<pin id="15" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="16" class="1001" name="const_16">
<pin_list>
<pin id="17" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str"/></StgValue>
</bind>
</comp>

<comp id="18" class="1001" name="const_18">
<pin_list>
<pin id="19" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str1"/></StgValue>
</bind>
</comp>

<comp id="20" class="1001" name="const_20">
<pin_list>
<pin id="21" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecMemCore"/></StgValue>
</bind>
</comp>

<comp id="22" class="1001" name="const_22">
<pin_list>
<pin id="23" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str5"/></StgValue>
</bind>
</comp>

<comp id="24" class="1001" name="const_24">
<pin_list>
<pin id="25" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="RAM_1P_str"/></StgValue>
</bind>
</comp>

<comp id="26" class="1001" name="const_26">
<pin_list>
<pin id="27" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="28" class="1001" name="const_28">
<pin_list>
<pin id="29" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str4"/></StgValue>
</bind>
</comp>

<comp id="30" class="1001" name="const_30">
<pin_list>
<pin id="31" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str3"/></StgValue>
</bind>
</comp>

<comp id="32" class="1001" name="const_32">
<pin_list>
<pin id="33" dir="1" index="0" bw="1" slack="1"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="34" class="1001" name="const_34">
<pin_list>
<pin id="35" dir="1" index="0" bw="1" slack="1"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="36" class="1001" name="const_36">
<pin_list>
<pin id="37" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="38" class="1001" name="const_38">
<pin_list>
<pin id="39" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="40" class="1001" name="const_40">
<pin_list>
<pin id="41" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecLoopTripCount"/></StgValue>
</bind>
</comp>

<comp id="42" class="1001" name="const_42">
<pin_list>
<pin id="43" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="44" class="1001" name="const_44">
<pin_list>
<pin id="45" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="46" class="1001" name="const_46">
<pin_list>
<pin id="47" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="48" class="1001" name="const_48">
<pin_list>
<pin id="49" dir="1" index="0" bw="1" slack="1"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="50" class="1001" name="const_50">
<pin_list>
<pin id="51" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="52" class="1001" name="const_52">
<pin_list>
<pin id="53" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="54" class="1001" name="const_54">
<pin_list>
<pin id="55" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="56" class="1001" name="const_56">
<pin_list>
<pin id="57" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="58" class="1001" name="const_58">
<pin_list>
<pin id="59" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_BitConcatenate.i7.i4.i3"/></StgValue>
</bind>
</comp>

<comp id="60" class="1001" name="const_60">
<pin_list>
<pin id="61" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="62" class="1001" name="const_62">
<pin_list>
<pin id="63" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_BitConcatenate.i5.i4.i1"/></StgValue>
</bind>
</comp>

<comp id="64" class="1001" name="const_64">
<pin_list>
<pin id="65" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="66" class="1004" name="C_addr_gep_fu_66">
<pin_list>
<pin id="67" dir="0" index="0" bw="32" slack="0"/>
<pin id="68" dir="0" index="1" bw="1" slack="0"/>
<pin id="69" dir="0" index="2" bw="14" slack="0"/>
<pin id="70" dir="1" index="3" bw="14" slack="0"/>
</pin_list>
<bind>
<opcode="getelementptr(29) " fcode="getelementptr"/>
<opset="C_addr/3 "/>
</bind>
</comp>

<comp id="73" class="1004" name="grp_access_fu_73">
<pin_list>
<pin id="74" dir="0" index="0" bw="14" slack="0"/>
<pin id="75" dir="0" index="1" bw="32" slack="0"/>
<pin id="76" dir="1" index="2" bw="32" slack="0"/>
</pin_list>
<bind>
<opcode="load(27) store(28) " fcode="store"/>
<opset="StgValue_39/3 C_load/7 StgValue_80/8 "/>
</bind>
</comp>

<comp id="79" class="1004" name="A_addr_gep_fu_79">
<pin_list>
<pin id="80" dir="0" index="0" bw="32" slack="0"/>
<pin id="81" dir="0" index="1" bw="1" slack="0"/>
<pin id="82" dir="0" index="2" bw="14" slack="0"/>
<pin id="83" dir="1" index="3" bw="14" slack="0"/>
</pin_list>
<bind>
<opcode="getelementptr(29) " fcode="getelementptr"/>
<opset="A_addr/5 "/>
</bind>
</comp>

<comp id="86" class="1004" name="grp_access_fu_86">
<pin_list>
<pin id="87" dir="0" index="0" bw="14" slack="0"/>
<pin id="88" dir="0" index="1" bw="32" slack="2147483647"/>
<pin id="89" dir="1" index="2" bw="32" slack="1"/>
</pin_list>
<bind>
<opcode="load(27) " fcode="load"/>
<opset="A_load/5 "/>
</bind>
</comp>

<comp id="91" class="1004" name="B_addr_gep_fu_91">
<pin_list>
<pin id="92" dir="0" index="0" bw="32" slack="0"/>
<pin id="93" dir="0" index="1" bw="1" slack="0"/>
<pin id="94" dir="0" index="2" bw="7" slack="0"/>
<pin id="95" dir="1" index="3" bw="7" slack="0"/>
</pin_list>
<bind>
<opcode="getelementptr(29) " fcode="getelementptr"/>
<opset="B_addr/5 "/>
</bind>
</comp>

<comp id="98" class="1004" name="grp_access_fu_98">
<pin_list>
<pin id="99" dir="0" index="0" bw="7" slack="0"/>
<pin id="100" dir="0" index="1" bw="32" slack="2147483647"/>
<pin id="101" dir="1" index="2" bw="32" slack="1"/>
</pin_list>
<bind>
<opcode="load(27) " fcode="load"/>
<opset="B_load/5 "/>
</bind>
</comp>

<comp id="103" class="1005" name="i_reg_103">
<pin_list>
<pin id="104" dir="0" index="0" bw="7" slack="1"/>
<pin id="105" dir="1" index="1" bw="7" slack="1"/>
</pin_list>
<bind>
<opset="i (phireg) "/>
</bind>
</comp>

<comp id="107" class="1004" name="i_phi_fu_107">
<pin_list>
<pin id="108" dir="0" index="0" bw="1" slack="1"/>
<pin id="109" dir="0" index="1" bw="0" slack="2147483647"/>
<pin id="110" dir="0" index="2" bw="7" slack="0"/>
<pin id="111" dir="0" index="3" bw="0" slack="2147483647"/>
<pin id="112" dir="1" index="4" bw="7" slack="0"/>
</pin_list>
<bind>
<opcode="phi(47) " fcode="phi"/>
<opset="i/2 "/>
</bind>
</comp>

<comp id="115" class="1005" name="phi_mul_reg_115">
<pin_list>
<pin id="116" dir="0" index="0" bw="14" slack="1"/>
<pin id="117" dir="1" index="1" bw="14" slack="1"/>
</pin_list>
<bind>
<opset="phi_mul (phireg) "/>
</bind>
</comp>

<comp id="119" class="1004" name="phi_mul_phi_fu_119">
<pin_list>
<pin id="120" dir="0" index="0" bw="1" slack="1"/>
<pin id="121" dir="0" index="1" bw="0" slack="2147483647"/>
<pin id="122" dir="0" index="2" bw="14" slack="0"/>
<pin id="123" dir="0" index="3" bw="0" slack="2147483647"/>
<pin id="124" dir="1" index="4" bw="14" slack="0"/>
</pin_list>
<bind>
<opcode="phi(47) " fcode="phi"/>
<opset="phi_mul/2 "/>
</bind>
</comp>

<comp id="127" class="1005" name="j_reg_127">
<pin_list>
<pin id="128" dir="0" index="0" bw="7" slack="1"/>
<pin id="129" dir="1" index="1" bw="7" slack="1"/>
</pin_list>
<bind>
<opset="j (phireg) "/>
</bind>
</comp>

<comp id="131" class="1004" name="j_phi_fu_131">
<pin_list>
<pin id="132" dir="0" index="0" bw="7" slack="0"/>
<pin id="133" dir="0" index="1" bw="0" slack="2147483647"/>
<pin id="134" dir="0" index="2" bw="1" slack="1"/>
<pin id="135" dir="0" index="3" bw="0" slack="2147483647"/>
<pin id="136" dir="1" index="4" bw="7" slack="0"/>
</pin_list>
<bind>
<opcode="phi(47) " fcode="phi"/>
<opset="j/3 "/>
</bind>
</comp>

<comp id="138" class="1005" name="k_reg_138">
<pin_list>
<pin id="139" dir="0" index="0" bw="4" slack="1"/>
<pin id="140" dir="1" index="1" bw="4" slack="1"/>
</pin_list>
<bind>
<opset="k (phireg) "/>
</bind>
</comp>

<comp id="142" class="1004" name="k_phi_fu_142">
<pin_list>
<pin id="143" dir="0" index="0" bw="1" slack="1"/>
<pin id="144" dir="0" index="1" bw="0" slack="2147483647"/>
<pin id="145" dir="0" index="2" bw="4" slack="0"/>
<pin id="146" dir="0" index="3" bw="0" slack="2147483647"/>
<pin id="147" dir="1" index="4" bw="4" slack="0"/>
</pin_list>
<bind>
<opcode="phi(47) " fcode="phi"/>
<opset="k/4 "/>
</bind>
</comp>

<comp id="149" class="1005" name="l_reg_149">
<pin_list>
<pin id="150" dir="0" index="0" bw="4" slack="1"/>
<pin id="151" dir="1" index="1" bw="4" slack="1"/>
</pin_list>
<bind>
<opset="l (phireg) "/>
</bind>
</comp>

<comp id="153" class="1004" name="l_phi_fu_153">
<pin_list>
<pin id="154" dir="0" index="0" bw="4" slack="0"/>
<pin id="155" dir="0" index="1" bw="0" slack="2147483647"/>
<pin id="156" dir="0" index="2" bw="1" slack="1"/>
<pin id="157" dir="0" index="3" bw="0" slack="2147483647"/>
<pin id="158" dir="1" index="4" bw="4" slack="0"/>
</pin_list>
<bind>
<opcode="phi(47) " fcode="phi"/>
<opset="l/5 "/>
</bind>
</comp>

<comp id="160" class="1004" name="next_mul_fu_160">
<pin_list>
<pin id="161" dir="0" index="0" bw="14" slack="0"/>
<pin id="162" dir="0" index="1" bw="8" slack="0"/>
<pin id="163" dir="1" index="2" bw="14" slack="0"/>
</pin_list>
<bind>
<opcode="add(8) " fcode="add"/>
<opset="next_mul/2 "/>
</bind>
</comp>

<comp id="166" class="1004" name="exitcond3_fu_166">
<pin_list>
<pin id="167" dir="0" index="0" bw="7" slack="0"/>
<pin id="168" dir="0" index="1" bw="7" slack="0"/>
<pin id="169" dir="1" index="2" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<opcode="icmp(45) " fcode="icmp"/>
<opset="exitcond3/2 "/>
</bind>
</comp>

<comp id="172" class="1004" name="i_1_fu_172">
<pin_list>
<pin id="173" dir="0" index="0" bw="7" slack="0"/>
<pin id="174" dir="0" index="1" bw="1" slack="0"/>
<pin id="175" dir="1" index="2" bw="7" slack="0"/>
</pin_list>
<bind>
<opcode="add(8) " fcode="add"/>
<opset="i_1/2 "/>
</bind>
</comp>

<comp id="178" class="1004" name="j_cast5_fu_178">
<pin_list>
<pin id="179" dir="0" index="0" bw="7" slack="0"/>
<pin id="180" dir="1" index="1" bw="14" slack="0"/>
</pin_list>
<bind>
<opcode="zext(34) " fcode="zext"/>
<opset="j_cast5/3 "/>
</bind>
</comp>

<comp id="182" class="1004" name="exitcond2_fu_182">
<pin_list>
<pin id="183" dir="0" index="0" bw="7" slack="0"/>
<pin id="184" dir="0" index="1" bw="7" slack="0"/>
<pin id="185" dir="1" index="2" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<opcode="icmp(45) " fcode="icmp"/>
<opset="exitcond2/3 "/>
</bind>
</comp>

<comp id="188" class="1004" name="j_1_fu_188">
<pin_list>
<pin id="189" dir="0" index="0" bw="7" slack="0"/>
<pin id="190" dir="0" index="1" bw="1" slack="0"/>
<pin id="191" dir="1" index="2" bw="7" slack="0"/>
</pin_list>
<bind>
<opcode="add(8) " fcode="add"/>
<opset="j_1/3 "/>
</bind>
</comp>

<comp id="194" class="1004" name="tmp_2_fu_194">
<pin_list>
<pin id="195" dir="0" index="0" bw="14" slack="1"/>
<pin id="196" dir="0" index="1" bw="7" slack="0"/>
<pin id="197" dir="1" index="2" bw="14" slack="0"/>
</pin_list>
<bind>
<opcode="add(8) " fcode="add"/>
<opset="tmp_2/3 "/>
</bind>
</comp>

<comp id="200" class="1004" name="tmp_3_fu_200">
<pin_list>
<pin id="201" dir="0" index="0" bw="14" slack="0"/>
<pin id="202" dir="1" index="1" bw="64" slack="0"/>
</pin_list>
<bind>
<opcode="zext(34) " fcode="zext"/>
<opset="tmp_3/3 "/>
</bind>
</comp>

<comp id="205" class="1004" name="k_cast4_fu_205">
<pin_list>
<pin id="206" dir="0" index="0" bw="4" slack="0"/>
<pin id="207" dir="1" index="1" bw="7" slack="0"/>
</pin_list>
<bind>
<opcode="zext(34) " fcode="zext"/>
<opset="k_cast4/4 "/>
</bind>
</comp>

<comp id="209" class="1004" name="exitcond1_fu_209">
<pin_list>
<pin id="210" dir="0" index="0" bw="4" slack="0"/>
<pin id="211" dir="0" index="1" bw="4" slack="0"/>
<pin id="212" dir="1" index="2" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<opcode="icmp(45) " fcode="icmp"/>
<opset="exitcond1/4 "/>
</bind>
</comp>

<comp id="215" class="1004" name="k_1_fu_215">
<pin_list>
<pin id="216" dir="0" index="0" bw="4" slack="0"/>
<pin id="217" dir="0" index="1" bw="1" slack="0"/>
<pin id="218" dir="1" index="2" bw="4" slack="0"/>
</pin_list>
<bind>
<opcode="add(8) " fcode="add"/>
<opset="k_1/4 "/>
</bind>
</comp>

<comp id="221" class="1004" name="tmp_5_fu_221">
<pin_list>
<pin id="222" dir="0" index="0" bw="4" slack="0"/>
<pin id="223" dir="0" index="1" bw="7" slack="2"/>
<pin id="224" dir="1" index="2" bw="7" slack="0"/>
</pin_list>
<bind>
<opcode="add(8) " fcode="add"/>
<opset="tmp_5/4 "/>
</bind>
</comp>

<comp id="227" class="1004" name="tmp_5_cast_cast_fu_227">
<pin_list>
<pin id="228" dir="0" index="0" bw="7" slack="0"/>
<pin id="229" dir="1" index="1" bw="14" slack="0"/>
</pin_list>
<bind>
<opcode="zext(34) " fcode="zext"/>
<opset="tmp_5_cast_cast/4 "/>
</bind>
</comp>

<comp id="231" class="1004" name="tmp_6_fu_231">
<pin_list>
<pin id="232" dir="0" index="0" bw="7" slack="0"/>
<pin id="233" dir="0" index="1" bw="8" slack="0"/>
<pin id="234" dir="1" index="2" bw="14" slack="1"/>
</pin_list>
<bind>
<opcode="mul(12) " fcode="mul"/>
<opset="tmp_6/4 "/>
</bind>
</comp>

<comp id="237" class="1004" name="p_shl_fu_237">
<pin_list>
<pin id="238" dir="0" index="0" bw="7" slack="0"/>
<pin id="239" dir="0" index="1" bw="4" slack="0"/>
<pin id="240" dir="0" index="2" bw="1" slack="0"/>
<pin id="241" dir="1" index="3" bw="7" slack="1"/>
</pin_list>
<bind>
<opcode="bitconcatenate(1004) " fcode="bitconcatenate"/>
<opset="p_shl/4 "/>
</bind>
</comp>

<comp id="245" class="1004" name="p_shl8_fu_245">
<pin_list>
<pin id="246" dir="0" index="0" bw="5" slack="0"/>
<pin id="247" dir="0" index="1" bw="4" slack="0"/>
<pin id="248" dir="0" index="2" bw="1" slack="0"/>
<pin id="249" dir="1" index="3" bw="5" slack="1"/>
</pin_list>
<bind>
<opcode="bitconcatenate(1004) " fcode="bitconcatenate"/>
<opset="p_shl8/4 "/>
</bind>
</comp>

<comp id="253" class="1004" name="l_cast3_fu_253">
<pin_list>
<pin id="254" dir="0" index="0" bw="4" slack="0"/>
<pin id="255" dir="1" index="1" bw="14" slack="0"/>
</pin_list>
<bind>
<opcode="zext(34) " fcode="zext"/>
<opset="l_cast3/5 "/>
</bind>
</comp>

<comp id="257" class="1004" name="l_cast_fu_257">
<pin_list>
<pin id="258" dir="0" index="0" bw="4" slack="0"/>
<pin id="259" dir="1" index="1" bw="5" slack="0"/>
</pin_list>
<bind>
<opcode="zext(34) " fcode="zext"/>
<opset="l_cast/5 "/>
</bind>
</comp>

<comp id="261" class="1004" name="exitcond_fu_261">
<pin_list>
<pin id="262" dir="0" index="0" bw="4" slack="0"/>
<pin id="263" dir="0" index="1" bw="4" slack="0"/>
<pin id="264" dir="1" index="2" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<opcode="icmp(45) " fcode="icmp"/>
<opset="exitcond/5 "/>
</bind>
</comp>

<comp id="267" class="1004" name="l_1_fu_267">
<pin_list>
<pin id="268" dir="0" index="0" bw="4" slack="0"/>
<pin id="269" dir="0" index="1" bw="1" slack="0"/>
<pin id="270" dir="1" index="2" bw="4" slack="0"/>
</pin_list>
<bind>
<opcode="add(8) " fcode="add"/>
<opset="l_1/5 "/>
</bind>
</comp>

<comp id="273" class="1004" name="tmp1_fu_273">
<pin_list>
<pin id="274" dir="0" index="0" bw="14" slack="1"/>
<pin id="275" dir="0" index="1" bw="4" slack="0"/>
<pin id="276" dir="1" index="2" bw="14" slack="0"/>
</pin_list>
<bind>
<opcode="add(8) " fcode="add"/>
<opset="tmp1/5 "/>
</bind>
</comp>

<comp id="278" class="1004" name="tmp_s_fu_278">
<pin_list>
<pin id="279" dir="0" index="0" bw="14" slack="0"/>
<pin id="280" dir="0" index="1" bw="7" slack="2"/>
<pin id="281" dir="1" index="2" bw="14" slack="0"/>
</pin_list>
<bind>
<opcode="add(8) " fcode="add"/>
<opset="tmp_s/5 "/>
</bind>
</comp>

<comp id="283" class="1004" name="tmp_1_fu_283">
<pin_list>
<pin id="284" dir="0" index="0" bw="14" slack="0"/>
<pin id="285" dir="1" index="1" bw="64" slack="0"/>
</pin_list>
<bind>
<opcode="zext(34) " fcode="zext"/>
<opset="tmp_1/5 "/>
</bind>
</comp>

<comp id="288" class="1004" name="tmp2_fu_288">
<pin_list>
<pin id="289" dir="0" index="0" bw="5" slack="1"/>
<pin id="290" dir="0" index="1" bw="4" slack="0"/>
<pin id="291" dir="1" index="2" bw="5" slack="0"/>
</pin_list>
<bind>
<opcode="add(8) " fcode="add"/>
<opset="tmp2/5 "/>
</bind>
</comp>

<comp id="293" class="1004" name="tmp2_cast_fu_293">
<pin_list>
<pin id="294" dir="0" index="0" bw="5" slack="0"/>
<pin id="295" dir="1" index="1" bw="7" slack="0"/>
</pin_list>
<bind>
<opcode="zext(34) " fcode="zext"/>
<opset="tmp2_cast/5 "/>
</bind>
</comp>

<comp id="297" class="1004" name="tmp_4_fu_297">
<pin_list>
<pin id="298" dir="0" index="0" bw="5" slack="0"/>
<pin id="299" dir="0" index="1" bw="7" slack="1"/>
<pin id="300" dir="1" index="2" bw="7" slack="0"/>
</pin_list>
<bind>
<opcode="add(8) " fcode="add"/>
<opset="tmp_4/5 "/>
</bind>
</comp>

<comp id="302" class="1004" name="tmp_8_fu_302">
<pin_list>
<pin id="303" dir="0" index="0" bw="7" slack="0"/>
<pin id="304" dir="1" index="1" bw="64" slack="0"/>
</pin_list>
<bind>
<opcode="zext(34) " fcode="zext"/>
<opset="tmp_8/5 "/>
</bind>
</comp>

<comp id="307" class="1004" name="tmp_7_fu_307">
<pin_list>
<pin id="308" dir="0" index="0" bw="32" slack="1"/>
<pin id="309" dir="0" index="1" bw="32" slack="1"/>
<pin id="310" dir="1" index="2" bw="32" slack="1"/>
</pin_list>
<bind>
<opcode="mul(12) " fcode="mul"/>
<opset="tmp_7/7 "/>
</bind>
</comp>

<comp id="311" class="1004" name="tmp_9_fu_311">
<pin_list>
<pin id="312" dir="0" index="0" bw="32" slack="0"/>
<pin id="313" dir="0" index="1" bw="32" slack="1"/>
<pin id="314" dir="1" index="2" bw="32" slack="0"/>
</pin_list>
<bind>
<opcode="add(8) " fcode="add"/>
<opset="tmp_9/8 "/>
</bind>
</comp>

<comp id="317" class="1005" name="next_mul_reg_317">
<pin_list>
<pin id="318" dir="0" index="0" bw="14" slack="0"/>
<pin id="319" dir="1" index="1" bw="14" slack="0"/>
</pin_list>
<bind>
<opset="next_mul "/>
</bind>
</comp>

<comp id="325" class="1005" name="i_1_reg_325">
<pin_list>
<pin id="326" dir="0" index="0" bw="7" slack="0"/>
<pin id="327" dir="1" index="1" bw="7" slack="0"/>
</pin_list>
<bind>
<opset="i_1 "/>
</bind>
</comp>

<comp id="330" class="1005" name="j_cast5_reg_330">
<pin_list>
<pin id="331" dir="0" index="0" bw="14" slack="2"/>
<pin id="332" dir="1" index="1" bw="14" slack="2"/>
</pin_list>
<bind>
<opset="j_cast5 "/>
</bind>
</comp>

<comp id="338" class="1005" name="j_1_reg_338">
<pin_list>
<pin id="339" dir="0" index="0" bw="7" slack="0"/>
<pin id="340" dir="1" index="1" bw="7" slack="0"/>
</pin_list>
<bind>
<opset="j_1 "/>
</bind>
</comp>

<comp id="343" class="1005" name="C_addr_reg_343">
<pin_list>
<pin id="344" dir="0" index="0" bw="14" slack="4"/>
<pin id="345" dir="1" index="1" bw="14" slack="4"/>
</pin_list>
<bind>
<opset="C_addr "/>
</bind>
</comp>

<comp id="351" class="1005" name="k_1_reg_351">
<pin_list>
<pin id="352" dir="0" index="0" bw="4" slack="0"/>
<pin id="353" dir="1" index="1" bw="4" slack="0"/>
</pin_list>
<bind>
<opset="k_1 "/>
</bind>
</comp>

<comp id="356" class="1005" name="tmp_6_reg_356">
<pin_list>
<pin id="357" dir="0" index="0" bw="14" slack="1"/>
<pin id="358" dir="1" index="1" bw="14" slack="1"/>
</pin_list>
<bind>
<opset="tmp_6 "/>
</bind>
</comp>

<comp id="361" class="1005" name="p_shl_reg_361">
<pin_list>
<pin id="362" dir="0" index="0" bw="7" slack="1"/>
<pin id="363" dir="1" index="1" bw="7" slack="1"/>
</pin_list>
<bind>
<opset="p_shl "/>
</bind>
</comp>

<comp id="366" class="1005" name="p_shl8_reg_366">
<pin_list>
<pin id="367" dir="0" index="0" bw="5" slack="1"/>
<pin id="368" dir="1" index="1" bw="5" slack="1"/>
</pin_list>
<bind>
<opset="p_shl8 "/>
</bind>
</comp>

<comp id="374" class="1005" name="l_1_reg_374">
<pin_list>
<pin id="375" dir="0" index="0" bw="4" slack="0"/>
<pin id="376" dir="1" index="1" bw="4" slack="0"/>
</pin_list>
<bind>
<opset="l_1 "/>
</bind>
</comp>

<comp id="379" class="1005" name="A_addr_reg_379">
<pin_list>
<pin id="380" dir="0" index="0" bw="14" slack="1"/>
<pin id="381" dir="1" index="1" bw="14" slack="1"/>
</pin_list>
<bind>
<opset="A_addr "/>
</bind>
</comp>

<comp id="384" class="1005" name="B_addr_reg_384">
<pin_list>
<pin id="385" dir="0" index="0" bw="7" slack="1"/>
<pin id="386" dir="1" index="1" bw="7" slack="1"/>
</pin_list>
<bind>
<opset="B_addr "/>
</bind>
</comp>

<comp id="389" class="1005" name="A_load_reg_389">
<pin_list>
<pin id="390" dir="0" index="0" bw="32" slack="1"/>
<pin id="391" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="A_load "/>
</bind>
</comp>

<comp id="394" class="1005" name="B_load_reg_394">
<pin_list>
<pin id="395" dir="0" index="0" bw="32" slack="1"/>
<pin id="396" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="B_load "/>
</bind>
</comp>

<comp id="399" class="1005" name="tmp_7_reg_399">
<pin_list>
<pin id="400" dir="0" index="0" bw="32" slack="1"/>
<pin id="401" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="tmp_7 "/>
</bind>
</comp>

</comp_list>

<net_list>
<net id="71"><net_src comp="4" pin="0"/><net_sink comp="66" pin=0"/></net>

<net id="72"><net_src comp="46" pin="0"/><net_sink comp="66" pin=1"/></net>

<net id="77"><net_src comp="14" pin="0"/><net_sink comp="73" pin=1"/></net>

<net id="78"><net_src comp="66" pin="3"/><net_sink comp="73" pin=0"/></net>

<net id="84"><net_src comp="0" pin="0"/><net_sink comp="79" pin=0"/></net>

<net id="85"><net_src comp="46" pin="0"/><net_sink comp="79" pin=1"/></net>

<net id="90"><net_src comp="79" pin="3"/><net_sink comp="86" pin=0"/></net>

<net id="96"><net_src comp="2" pin="0"/><net_sink comp="91" pin=0"/></net>

<net id="97"><net_src comp="46" pin="0"/><net_sink comp="91" pin=1"/></net>

<net id="102"><net_src comp="91" pin="3"/><net_sink comp="98" pin=0"/></net>

<net id="106"><net_src comp="32" pin="0"/><net_sink comp="103" pin=0"/></net>

<net id="113"><net_src comp="103" pin="1"/><net_sink comp="107" pin=0"/></net>

<net id="114"><net_src comp="107" pin="4"/><net_sink comp="103" pin=0"/></net>

<net id="118"><net_src comp="34" pin="0"/><net_sink comp="115" pin=0"/></net>

<net id="125"><net_src comp="115" pin="1"/><net_sink comp="119" pin=0"/></net>

<net id="126"><net_src comp="119" pin="4"/><net_sink comp="115" pin=0"/></net>

<net id="130"><net_src comp="32" pin="0"/><net_sink comp="127" pin=0"/></net>

<net id="137"><net_src comp="127" pin="1"/><net_sink comp="131" pin=2"/></net>

<net id="141"><net_src comp="48" pin="0"/><net_sink comp="138" pin=0"/></net>

<net id="148"><net_src comp="138" pin="1"/><net_sink comp="142" pin=0"/></net>

<net id="152"><net_src comp="48" pin="0"/><net_sink comp="149" pin=0"/></net>

<net id="159"><net_src comp="149" pin="1"/><net_sink comp="153" pin=2"/></net>

<net id="164"><net_src comp="119" pin="4"/><net_sink comp="160" pin=0"/></net>

<net id="165"><net_src comp="36" pin="0"/><net_sink comp="160" pin=1"/></net>

<net id="170"><net_src comp="107" pin="4"/><net_sink comp="166" pin=0"/></net>

<net id="171"><net_src comp="38" pin="0"/><net_sink comp="166" pin=1"/></net>

<net id="176"><net_src comp="107" pin="4"/><net_sink comp="172" pin=0"/></net>

<net id="177"><net_src comp="44" pin="0"/><net_sink comp="172" pin=1"/></net>

<net id="181"><net_src comp="131" pin="4"/><net_sink comp="178" pin=0"/></net>

<net id="186"><net_src comp="131" pin="4"/><net_sink comp="182" pin=0"/></net>

<net id="187"><net_src comp="38" pin="0"/><net_sink comp="182" pin=1"/></net>

<net id="192"><net_src comp="131" pin="4"/><net_sink comp="188" pin=0"/></net>

<net id="193"><net_src comp="44" pin="0"/><net_sink comp="188" pin=1"/></net>

<net id="198"><net_src comp="115" pin="1"/><net_sink comp="194" pin=0"/></net>

<net id="199"><net_src comp="178" pin="1"/><net_sink comp="194" pin=1"/></net>

<net id="203"><net_src comp="194" pin="2"/><net_sink comp="200" pin=0"/></net>

<net id="204"><net_src comp="200" pin="1"/><net_sink comp="66" pin=2"/></net>

<net id="208"><net_src comp="142" pin="4"/><net_sink comp="205" pin=0"/></net>

<net id="213"><net_src comp="142" pin="4"/><net_sink comp="209" pin=0"/></net>

<net id="214"><net_src comp="50" pin="0"/><net_sink comp="209" pin=1"/></net>

<net id="219"><net_src comp="142" pin="4"/><net_sink comp="215" pin=0"/></net>

<net id="220"><net_src comp="54" pin="0"/><net_sink comp="215" pin=1"/></net>

<net id="225"><net_src comp="205" pin="1"/><net_sink comp="221" pin=0"/></net>

<net id="226"><net_src comp="103" pin="1"/><net_sink comp="221" pin=1"/></net>

<net id="230"><net_src comp="221" pin="2"/><net_sink comp="227" pin=0"/></net>

<net id="235"><net_src comp="227" pin="1"/><net_sink comp="231" pin=0"/></net>

<net id="236"><net_src comp="56" pin="0"/><net_sink comp="231" pin=1"/></net>

<net id="242"><net_src comp="58" pin="0"/><net_sink comp="237" pin=0"/></net>

<net id="243"><net_src comp="142" pin="4"/><net_sink comp="237" pin=1"/></net>

<net id="244"><net_src comp="60" pin="0"/><net_sink comp="237" pin=2"/></net>

<net id="250"><net_src comp="62" pin="0"/><net_sink comp="245" pin=0"/></net>

<net id="251"><net_src comp="142" pin="4"/><net_sink comp="245" pin=1"/></net>

<net id="252"><net_src comp="64" pin="0"/><net_sink comp="245" pin=2"/></net>

<net id="256"><net_src comp="153" pin="4"/><net_sink comp="253" pin=0"/></net>

<net id="260"><net_src comp="153" pin="4"/><net_sink comp="257" pin=0"/></net>

<net id="265"><net_src comp="153" pin="4"/><net_sink comp="261" pin=0"/></net>

<net id="266"><net_src comp="50" pin="0"/><net_sink comp="261" pin=1"/></net>

<net id="271"><net_src comp="153" pin="4"/><net_sink comp="267" pin=0"/></net>

<net id="272"><net_src comp="54" pin="0"/><net_sink comp="267" pin=1"/></net>

<net id="277"><net_src comp="253" pin="1"/><net_sink comp="273" pin=1"/></net>

<net id="282"><net_src comp="273" pin="2"/><net_sink comp="278" pin=0"/></net>

<net id="286"><net_src comp="278" pin="2"/><net_sink comp="283" pin=0"/></net>

<net id="287"><net_src comp="283" pin="1"/><net_sink comp="79" pin=2"/></net>

<net id="292"><net_src comp="257" pin="1"/><net_sink comp="288" pin=1"/></net>

<net id="296"><net_src comp="288" pin="2"/><net_sink comp="293" pin=0"/></net>

<net id="301"><net_src comp="293" pin="1"/><net_sink comp="297" pin=0"/></net>

<net id="305"><net_src comp="297" pin="2"/><net_sink comp="302" pin=0"/></net>

<net id="306"><net_src comp="302" pin="1"/><net_sink comp="91" pin=2"/></net>

<net id="315"><net_src comp="73" pin="2"/><net_sink comp="311" pin=0"/></net>

<net id="316"><net_src comp="311" pin="2"/><net_sink comp="73" pin=1"/></net>

<net id="320"><net_src comp="160" pin="2"/><net_sink comp="317" pin=0"/></net>

<net id="321"><net_src comp="317" pin="1"/><net_sink comp="119" pin=2"/></net>

<net id="328"><net_src comp="172" pin="2"/><net_sink comp="325" pin=0"/></net>

<net id="329"><net_src comp="325" pin="1"/><net_sink comp="107" pin=2"/></net>

<net id="333"><net_src comp="178" pin="1"/><net_sink comp="330" pin=0"/></net>

<net id="334"><net_src comp="330" pin="1"/><net_sink comp="278" pin=1"/></net>

<net id="341"><net_src comp="188" pin="2"/><net_sink comp="338" pin=0"/></net>

<net id="342"><net_src comp="338" pin="1"/><net_sink comp="131" pin=0"/></net>

<net id="346"><net_src comp="66" pin="3"/><net_sink comp="343" pin=0"/></net>

<net id="347"><net_src comp="343" pin="1"/><net_sink comp="73" pin=0"/></net>

<net id="354"><net_src comp="215" pin="2"/><net_sink comp="351" pin=0"/></net>

<net id="355"><net_src comp="351" pin="1"/><net_sink comp="142" pin=2"/></net>

<net id="359"><net_src comp="231" pin="2"/><net_sink comp="356" pin=0"/></net>

<net id="360"><net_src comp="356" pin="1"/><net_sink comp="273" pin=0"/></net>

<net id="364"><net_src comp="237" pin="3"/><net_sink comp="361" pin=0"/></net>

<net id="365"><net_src comp="361" pin="1"/><net_sink comp="297" pin=1"/></net>

<net id="369"><net_src comp="245" pin="3"/><net_sink comp="366" pin=0"/></net>

<net id="370"><net_src comp="366" pin="1"/><net_sink comp="288" pin=0"/></net>

<net id="377"><net_src comp="267" pin="2"/><net_sink comp="374" pin=0"/></net>

<net id="378"><net_src comp="374" pin="1"/><net_sink comp="153" pin=0"/></net>

<net id="382"><net_src comp="79" pin="3"/><net_sink comp="379" pin=0"/></net>

<net id="383"><net_src comp="379" pin="1"/><net_sink comp="86" pin=0"/></net>

<net id="387"><net_src comp="91" pin="3"/><net_sink comp="384" pin=0"/></net>

<net id="388"><net_src comp="384" pin="1"/><net_sink comp="98" pin=0"/></net>

<net id="392"><net_src comp="86" pin="2"/><net_sink comp="389" pin=0"/></net>

<net id="393"><net_src comp="389" pin="1"/><net_sink comp="307" pin=0"/></net>

<net id="397"><net_src comp="98" pin="2"/><net_sink comp="394" pin=0"/></net>

<net id="398"><net_src comp="394" pin="1"/><net_sink comp="307" pin=1"/></net>

<net id="402"><net_src comp="307" pin="2"/><net_sink comp="399" pin=0"/></net>

<net id="403"><net_src comp="399" pin="1"/><net_sink comp="311" pin=1"/></net>

</net_list>

</model> 
---------------- Datapath Model END ------------------

* FSMD analyzer results:
  - Output states:
	Port: C | {3 8 }
 - Input state : 
	Port: convolution : A | {5 6 }
	Port: convolution : B | {5 6 }
	Port: convolution : C | {7 8 }
  - Chain level:
	State 1
	State 2
		next_mul : 1
		exitcond3 : 1
		i_1 : 1
		StgValue_27 : 2
	State 3
		j_cast5 : 1
		exitcond2 : 1
		j_1 : 1
		StgValue_35 : 2
		tmp_2 : 2
		tmp_3 : 3
		C_addr : 4
		StgValue_39 : 5
	State 4
		k_cast4 : 1
		exitcond1 : 1
		k_1 : 1
		StgValue_47 : 2
		tmp_5 : 2
		tmp_5_cast_cast : 3
		tmp_6 : 4
		p_shl : 1
		p_shl8 : 1
	State 5
		l_cast3 : 1
		l_cast : 1
		exitcond : 1
		l_1 : 1
		StgValue_61 : 2
		tmp1 : 2
		tmp_s : 3
		tmp_1 : 4
		A_addr : 5
		A_load : 6
		tmp2 : 2
		tmp2_cast : 3
		tmp_4 : 4
		tmp_8 : 5
		B_addr : 6
		B_load : 7
	State 6
	State 7
	State 8
		tmp_9 : 1
		StgValue_80 : 2


============================================================
+ Verbose Summary: Datapath Resource usage 
============================================================

* Functional unit list:
|----------|------------------------|---------|---------|---------|
| Operation|     Functional Unit    |  DSP48E |    FF   |   LUT   |
|----------|------------------------|---------|---------|---------|
|          |     next_mul_fu_160    |    0    |    0    |    21   |
|          |       i_1_fu_172       |    0    |    0    |    15   |
|          |       j_1_fu_188       |    0    |    0    |    15   |
|          |      tmp_2_fu_194      |    0    |    0    |    21   |
|          |       k_1_fu_215       |    0    |    0    |    13   |
|    add   |      tmp_5_fu_221      |    0    |    0    |    15   |
|          |       l_1_fu_267       |    0    |    0    |    13   |
|          |       tmp1_fu_273      |    0    |    0    |    14   |
|          |      tmp_s_fu_278      |    0    |    0    |    14   |
|          |       tmp2_fu_288      |    0    |    0    |    15   |
|          |      tmp_4_fu_297      |    0    |    0    |    15   |
|          |      tmp_9_fu_311      |    0    |    0    |    39   |
|----------|------------------------|---------|---------|---------|
|    mul   |      tmp_6_fu_231      |    0    |    0    |    41   |
|          |      tmp_7_fu_307      |    3    |    0    |    20   |
|----------|------------------------|---------|---------|---------|
|          |    exitcond3_fu_166    |    0    |    0    |    11   |
|   icmp   |    exitcond2_fu_182    |    0    |    0    |    11   |
|          |    exitcond1_fu_209    |    0    |    0    |    9    |
|          |     exitcond_fu_261    |    0    |    0    |    9    |
|----------|------------------------|---------|---------|---------|
|          |     j_cast5_fu_178     |    0    |    0    |    0    |
|          |      tmp_3_fu_200      |    0    |    0    |    0    |
|          |     k_cast4_fu_205     |    0    |    0    |    0    |
|          | tmp_5_cast_cast_fu_227 |    0    |    0    |    0    |
|   zext   |     l_cast3_fu_253     |    0    |    0    |    0    |
|          |      l_cast_fu_257     |    0    |    0    |    0    |
|          |      tmp_1_fu_283      |    0    |    0    |    0    |
|          |    tmp2_cast_fu_293    |    0    |    0    |    0    |
|          |      tmp_8_fu_302      |    0    |    0    |    0    |
|----------|------------------------|---------|---------|---------|
|bitconcatenate|      p_shl_fu_237      |    0    |    0    |    0    |
|          |      p_shl8_fu_245     |    0    |    0    |    0    |
|----------|------------------------|---------|---------|---------|
|   Total  |                        |    3    |    0    |   311   |
|----------|------------------------|---------|---------|---------|

Memories:
N/A

* Register list:
+----------------+--------+
|                |   FF   |
+----------------+--------+
| A_addr_reg_379 |   14   |
| A_load_reg_389 |   32   |
| B_addr_reg_384 |    7   |
| B_load_reg_394 |   32   |
| C_addr_reg_343 |   14   |
|   i_1_reg_325  |    7   |
|    i_reg_103   |    7   |
|   j_1_reg_338  |    7   |
| j_cast5_reg_330|   14   |
|    j_reg_127   |    7   |
|   k_1_reg_351  |    4   |
|    k_reg_138   |    4   |
|   l_1_reg_374  |    4   |
|    l_reg_149   |    4   |
|next_mul_reg_317|   14   |
| p_shl8_reg_366 |    5   |
|  p_shl_reg_361 |    7   |
| phi_mul_reg_115|   14   |
|  tmp_6_reg_356 |   14   |
|  tmp_7_reg_399 |   32   |
+----------------+--------+
|      Total     |   243  |
+----------------+--------+

* Multiplexer (MUX) list: 
|------------------|------|------|------|--------||---------||---------|
|       Comp       |  Pin | Size |  BW  | S x BW ||  Delay  ||   LUT   |
|------------------|------|------|------|--------||---------||---------|
| grp_access_fu_73 |  p0  |   2  |  14  |   28   ||    9    |
| grp_access_fu_73 |  p1  |   2  |  32  |   64   ||    9    |
| grp_access_fu_86 |  p0  |   2  |  14  |   28   ||    9    |
| grp_access_fu_98 |  p0  |   2  |   7  |   14   ||    9    |
|     i_reg_103    |  p0  |   2  |   7  |   14   ||    9    |
|  phi_mul_reg_115 |  p0  |   2  |  14  |   28   ||    9    |
|------------------|------|------|------|--------||---------||---------|
|       Total      |      |      |      |   176  ||  10.614 ||    54   |
|------------------|------|------|------|--------||---------||---------|



* Summary:
+-----------+--------+--------+--------+--------+
|           | DSP48E |  Delay |   FF   |   LUT  |
+-----------+--------+--------+--------+--------+
|  Function |    3   |    -   |    0   |   311  |
|   Memory  |    -   |    -   |    -   |    -   |
|Multiplexer|    -   |   10   |    -   |   54   |
|  Register |    -   |    -   |   243  |    -   |
+-----------+--------+--------+--------+--------+
|   Total   |    3   |   10   |   243  |   365  |
+-----------+--------+--------+--------+--------+