================================================================ == Vivado HLS Report for 'convolve' ================================================================ * Date: Tue May 29 16:07:21 2018 * Version: 2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017) * Project: edge_detection * Solution: solution1 * Product family: zynq * Target device: xc7z020clg484-1 ================================================================ == Performance Estimates ================================================================ + Timing (ns): * Summary: +--------+-------+----------+------------+ | Clock | Target| Estimated| Uncertainty| +--------+-------+----------+------------+ |ap_clk | 10.00| 7.26| 1.25| +--------+-------+----------+------------+ + Latency (clock cycles): * Summary: +---------+---------+---------+---------+---------+ | Latency | Interval | Pipeline| | min | max | min | max | Type | +---------+---------+---------+---------+---------+ | 2333221| 2333221| 2333221| 2333221| none | +---------+---------+---------+---------+---------+ + Detail: * Instance: N/A * Loop: +-----------------------+---------+---------+----------+-----------+-----------+--------+----------+ | | Latency | Iteration| Initiation Interval | Trip | | | Loop Name | min | max | Latency | achieved | target | Count | Pipelined| +-----------------------+---------+---------+----------+-----------+-----------+--------+----------+ |- iterate_over_pixels | 2332859| 2332859| 63| 3| 1| 777600| yes | +-----------------------+---------+---------+----------+-----------+-----------+--------+----------+ ================================================================ == Utilization Estimates ================================================================ * Summary: +-----------------+---------+-------+--------+-------+ | Name | BRAM_18K| DSP48E| FF | LUT | +-----------------+---------+-------+--------+-------+ |DSP | -| -| -| -| |Expression | -| -| 0| 290| |FIFO | -| -| -| -| |Instance | 0| 12| 1340| 2147| |Memory | 4| -| 0| 0| |Multiplexer | -| -| -| 8373| |Register | 0| -| 2076| 416| +-----------------+---------+-------+--------+-------+ |Total | 4| 12| 3416| 11226| +-----------------+---------+-------+--------+-------+ |Available | 280| 220| 106400| 53200| +-----------------+---------+-------+--------+-------+ |Utilization (%) | 1| 5| 3| 21| +-----------------+---------+-------+--------+-------+ + Detail: * Instance: +---------------------------+-------------------------+---------+-------+-----+-----+ | Instance | Module | BRAM_18K| DSP48E| FF | LUT | +---------------------------+-------------------------+---------+-------+-----+-----+ |convolve_AXILiteS_s_axi_U |convolve_AXILiteS_s_axi | 0| 0| 36| 40| |convolve_fadd_32ndEe_U1 |convolve_fadd_32ndEe | 0| 2| 205| 390| |convolve_fadd_32ndEe_U2 |convolve_fadd_32ndEe | 0| 2| 205| 390| |convolve_fadd_32ndEe_U3 |convolve_fadd_32ndEe | 0| 2| 205| 390| |convolve_fmul_32neOg_U4 |convolve_fmul_32neOg | 0| 3| 143| 321| |convolve_fmul_32neOg_U5 |convolve_fmul_32neOg | 0| 3| 143| 321| |convolve_urem_12nfYi_U6 |convolve_urem_12nfYi | 0| 0| 403| 295| +---------------------------+-------------------------+---------+-------+-----+-----+ |Total | | 0| 12| 1340| 2147| +---------------------------+-------------------------+---------+-------+-----+-----+ * DSP48: N/A * Memory: +----------------+----------------------+---------+---+----+------+-----+------+-------------+ | Memory | Module | BRAM_18K| FF| LUT| Words| Bits| Banks| W*Bits*Banks| +----------------+----------------------+---------+---+----+------+-----+------+-------------+ |temp_array_0_U |convolve_temp_arrbkb | 2| 0| 0| 720| 32| 1| 23040| |temp_array_1_U |convolve_temp_arrcud | 2| 0| 0| 720| 32| 1| 23040| +----------------+----------------------+---------+---+----+------+-----+------+-------------+ |Total | | 4| 0| 0| 1440| 64| 2| 46080| +----------------+----------------------+---------+---+----+------+-----+------+-------------+ * FIFO: N/A * Expression: +-------------------------------------+----------+-------+---+----+------------+------------+ | Variable Name | Operation| DSP48E| FF| LUT| Bitwidth P0| Bitwidth P1| +-------------------------------------+----------+-------+---+----+------------+------------+ |grp_fu_13282_p0 | + | 0| 0| 19| 11| 12| |i_fu_13336_p2 | + | 0| 0| 27| 20| 1| |next_urem_fu_13316_p2 | + | 0| 0| 27| 20| 1| |tmp_19_5_fu_13251_p2 | + | 0| 0| 18| 10| 11| |tmp_8_fu_13347_p2 | + | 0| 0| 17| 9| 10| |ap_block_pp0_stage1_11001 | and | 0| 0| 8| 1| 1| |ap_block_pp0_stage2_01001 | and | 0| 0| 8| 1| 1| |ap_block_state363_pp0_stage1_iter0 | and | 0| 0| 8| 1| 1| |ap_block_state424_pp0_stage2_iter20 | and | 0| 0| 8| 1| 1| |or_cond_fu_13310_p2 | and | 0| 0| 8| 1| 1| |exitcond_fu_13233_p2 | icmp | 0| 0| 18| 20| 20| |icmp_fu_13304_p2 | icmp | 0| 0| 13| 9| 1| |tmp_12_fu_13322_p2 | icmp | 0| 0| 18| 20| 10| |tmp_4_fu_13288_p2 | icmp | 0| 0| 18| 20| 11| |tmp_7_fu_13342_p2 | icmp | 0| 0| 13| 10| 10| |tmp_9_fu_13257_p2 | icmp | 0| 0| 13| 11| 11| |idx_urem_fu_13328_p3 | select | 0| 0| 20| 1| 20| |newIndex1_fu_13352_p3 | select | 0| 0| 10| 1| 10| |newIndex3_fu_13263_p3 | select | 0| 0| 11| 1| 11| |ap_enable_pp0 | xor | 0| 0| 8| 1| 2| +-------------------------------------+----------+-------+---+----+------------+------------+ |Total | | 0| 0| 290| 169| 146| +-------------------------------------+----------+-------+---+----+------------+------------+ * Multiplexer: +---------------------------------------+------+-----------+-----+-----------+ | Name | LUT | Input Size| Bits| Total Bits| +---------------------------------------+------+-----------+-----+-----------+ |ap_NS_fsm | 1609| 366| 1| 366| |ap_enable_reg_pp0_iter20 | 9| 2| 1| 2| |ap_enable_reg_pp0_iter5 | 9| 2| 1| 2| |ap_phi_mux_crop_1_10_phi_fu_13157_p4 | 9| 2| 32| 64| |ap_phi_mux_crop_4_9_phi_fu_13181_p4 | 9| 2| 32| 64| |ap_phi_mux_crop_4_phi_fu_13169_p4 | 9| 2| 32| 64| |ap_phi_mux_crop_7_8_phi_fu_13109_p4 | 9| 2| 32| 64| |ap_phi_mux_phi_urem_phi_fu_13133_p4 | 9| 2| 20| 40| |ap_phi_mux_pos_assign_phi_fu_13121_p4 | 9| 2| 20| 40| |crop_1_10_reg_13153 | 9| 2| 32| 64| |crop_1_reg_13190 | 9| 2| 32| 64| |crop_4_9_reg_13177 | 9| 2| 32| 64| |crop_4_reg_13165 | 9| 2| 32| 64| |crop_7_8_reg_13105 | 9| 2| 32| 64| |crop_7_reg_13140 | 9| 2| 32| 64| |grp_fu_13203_p0 | 21| 4| 32| 128| |grp_fu_13203_p1 | 21| 4| 32| 128| |grp_fu_13209_p0 | 21| 4| 32| 128| |grp_fu_13209_p1 | 21| 4| 32| 128| |grp_fu_13214_p0 | 21| 4| 32| 128| |grp_fu_13214_p1 | 21| 4| 32| 128| |grp_fu_13219_p0 | 21| 4| 32| 128| |grp_fu_13226_p0 | 15| 3| 32| 96| |grp_fu_13226_p1 | 15| 3| 32| 96| |in_V_blk_n | 9| 2| 1| 2| |out_V_blk_n | 9| 2| 1| 2| |phi_urem_reg_13129 | 9| 2| 20| 40| |pos_assign_reg_13117 | 9| 2| 20| 40| |temp_array_0_address0 | 1593| 362| 10| 3620| |temp_array_0_address1 | 1593| 362| 10| 3620| |temp_array_0_d0 | 15| 3| 32| 96| |temp_array_1_address0 | 1597| 363| 10| 3630| |temp_array_1_address1 | 1597| 363| 10| 3630| |temp_array_1_d0 | 15| 3| 32| 96| |temp_array_1_d1 | 15| 3| 32| 96| +---------------------------------------+------+-----------+-----+-----------+ |Total | 8373| 1895| 829| 17050| +---------------------------------------+------+-----------+-----+-----------+ * Register: +---------------------------------+-----+----+-----+-----------+ | Name | FF | LUT| Bits| Const Bits| +---------------------------------+-----+----+-----+-----------+ |ap_CS_fsm | 365| 0| 365| 0| |ap_enable_reg_pp0_iter0 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter1 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter10 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter11 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter12 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter13 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter14 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter15 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter16 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter17 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter18 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter19 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter2 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter20 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter3 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter4 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter5 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter6 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter7 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter8 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter9 | 1| 0| 1| 0| |crop_1_10_reg_13153 | 32| 0| 32| 0| |crop_1_reg_13190 | 32| 0| 32| 0| |crop_2_reg_20627 | 32| 0| 32| 0| |crop_4_9_reg_13177 | 32| 0| 32| 0| |crop_4_reg_13165 | 32| 0| 32| 0| |crop_5_reg_20638 | 32| 0| 32| 0| |crop_7_8_reg_13105 | 32| 0| 32| 0| |crop_7_reg_13140 | 32| 0| 32| 0| |exitcond_reg_20569 | 1| 0| 1| 0| |i_reg_20606 | 20| 0| 20| 0| |idx_urem_reg_20594 | 20| 0| 20| 0| |or_cond_reg_20590 | 1| 0| 1| 0| |phi_urem_reg_13129 | 20| 0| 20| 0| |pos_assign_reg_13117 | 20| 0| 20| 0| |result_1_reg_20670 | 32| 0| 32| 0| |result_2_reg_20675 | 32| 0| 32| 0| |result_3_reg_20680 | 32| 0| 32| 0| |result_4_reg_20685 | 32| 0| 32| 0| |result_5_reg_20690 | 32| 0| 32| 0| |result_6_reg_20695 | 32| 0| 32| 0| |result_7_reg_20700 | 32| 0| 32| 0| |result_reg_20665 | 32| 0| 32| 0| |temp_array_0_addr_720_reg_20621 | 10| 0| 10| 0| |temp_array_1_addr_720_reg_20580 | 10| 0| 10| 0| |temp_array_1_addr_721_reg_20633 | 10| 0| 10| 0| |tmp_10_reg_20573 | 10| 0| 10| 0| |tmp_13_reg_20599 | 32| 0| 32| 0| |tmp_28_2_reg_20660 | 32| 0| 32| 0| |tmp_28_4_reg_20655 | 32| 0| 32| 0| |tmp_28_6_reg_20611 | 32| 0| 32| 0| |tmp_28_8_reg_20616 | 32| 0| 32| 0| |tmp_3_reg_20705 | 32| 0| 32| 0| |tmp_6_reg_20650 | 32| 0| 32| 0| |crop_1_reg_13190 | 64| 32| 32| 0| |crop_4_reg_13165 | 64| 32| 32| 0| |crop_5_reg_20638 | 64| 32| 32| 0| |crop_7_reg_13140 | 64| 32| 32| 0| |exitcond_reg_20569 | 64| 32| 1| 0| |or_cond_reg_20590 | 64| 32| 1| 0| |temp_array_1_addr_720_reg_20580 | 64| 32| 10| 0| |tmp_10_reg_20573 | 64| 32| 10| 0| |tmp_13_reg_20599 | 64| 32| 32| 0| |tmp_28_2_reg_20660 | 64| 32| 32| 0| |tmp_28_4_reg_20655 | 64| 32| 32| 0| |tmp_28_6_reg_20611 | 64| 32| 32| 0| |tmp_28_8_reg_20616 | 64| 32| 32| 0| +---------------------------------+-----+----+-----+-----------+ |Total | 2076| 416| 1554| 0| +---------------------------------+-----+----+-----+-----------+ ================================================================ == Interface ================================================================ * Summary: +------------------------+-----+-----+------------+--------------+--------------+ | RTL Ports | Dir | Bits| Protocol | Source Object| C Type | +------------------------+-----+-----+------------+--------------+--------------+ |s_axi_AXILiteS_AWVALID | in | 1| s_axi | AXILiteS | return void | |s_axi_AXILiteS_AWREADY | out | 1| s_axi | AXILiteS | return void | |s_axi_AXILiteS_AWADDR | in | 4| s_axi | AXILiteS | return void | |s_axi_AXILiteS_WVALID | in | 1| s_axi | AXILiteS | return void | |s_axi_AXILiteS_WREADY | out | 1| s_axi | AXILiteS | return void | |s_axi_AXILiteS_WDATA | in | 32| s_axi | AXILiteS | return void | |s_axi_AXILiteS_WSTRB | in | 4| s_axi | AXILiteS | return void | |s_axi_AXILiteS_ARVALID | in | 1| s_axi | AXILiteS | return void | |s_axi_AXILiteS_ARREADY | out | 1| s_axi | AXILiteS | return void | |s_axi_AXILiteS_ARADDR | in | 4| s_axi | AXILiteS | return void | |s_axi_AXILiteS_RVALID | out | 1| s_axi | AXILiteS | return void | |s_axi_AXILiteS_RREADY | in | 1| s_axi | AXILiteS | return void | |s_axi_AXILiteS_RDATA | out | 32| s_axi | AXILiteS | return void | |s_axi_AXILiteS_RRESP | out | 2| s_axi | AXILiteS | return void | |s_axi_AXILiteS_BVALID | out | 1| s_axi | AXILiteS | return void | |s_axi_AXILiteS_BREADY | in | 1| s_axi | AXILiteS | return void | |s_axi_AXILiteS_BRESP | out | 2| s_axi | AXILiteS | return void | |ap_clk | in | 1| ap_ctrl_hs | convolve | return value | |ap_rst_n | in | 1| ap_ctrl_hs | convolve | return value | |interrupt | out | 1| ap_ctrl_hs | convolve | return value | |in_V_dout | in | 32| ap_fifo | in_V | pointer | |in_V_empty_n | in | 1| ap_fifo | in_V | pointer | |in_V_read | out | 1| ap_fifo | in_V | pointer | |out_V_din | out | 32| ap_fifo | out_V | pointer | |out_V_full_n | in | 1| ap_fifo | out_V | pointer | |out_V_write | out | 1| ap_fifo | out_V | pointer | +------------------------+-----+-----+------------+--------------+--------------+