Folder Path
/
MSc
/
HLS-FPGA
/
edge_detection
/
solution1
/
impl
/
verilog
/
0
directories
10
files
451 KiB
total
List
Grid
Name
Size
Modified
Up
convolution.v
12 KiB
05/17/2022 08:15:54 PM +00:00
convolve.v
414 KiB
05/17/2022 08:15:54 PM +00:00
convolve_ap_fadd_3_full_dsp_32_ip.tcl
2.4 KiB
05/17/2022 08:15:54 PM +00:00
convolve_ap_fmul_2_max_dsp_32_ip.tcl
2.4 KiB
05/17/2022 08:15:54 PM +00:00
convolve_AXILiteS_s_axi.v
8.8 KiB
05/17/2022 08:15:54 PM +00:00
convolve_fadd_32ndEe.v
2.1 KiB
05/17/2022 08:15:54 PM +00:00
convolve_fmul_32neOg.v
2.1 KiB
05/17/2022 08:15:54 PM +00:00
convolve_temp_arrbkb.v
1.8 KiB
05/17/2022 08:15:54 PM +00:00
convolve_temp_arrcud.v
1.9 KiB
05/17/2022 08:15:54 PM +00:00
convolve_urem_12nfYi.v
4.3 KiB
05/17/2022 08:15:54 PM +00:00