================================================================
== Vivado HLS Report for 'convolution'
================================================================
* Date:           Fri May 25 13:57:07 2018

* Version:        2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017)
* Project:        edge_detection
* Solution:       solution1
* Product family: zynq
* Target device:  xc7z020clg484-1


================================================================
== Performance Estimates
================================================================
+ Timing (ns): 
    * Summary: 
    +--------+-------+----------+------------+
    |  Clock | Target| Estimated| Uncertainty|
    +--------+-------+----------+------------+
    |ap_clk  |  10.00|      8.51|        1.25|
    +--------+-------+----------+------------+

+ Latency (clock cycles): 
    * Summary: 
    +---------+---------+---------+---------+---------+
    |      Latency      |      Interval     | Pipeline|
    |   min   |   max   |   min   |   max   |   Type  |
    +---------+---------+---------+---------+---------+
    |  3494765|  3494765|  3494765|  3494765|   none  |
    +---------+---------+---------+---------+---------+

    + Detail: 
        * Instance: 
        N/A

        * Loop: 
        +---------------------+---------+---------+----------+-----------+-----------+------+----------+
        |                     |      Latency      | Iteration|  Initiation Interval  | Trip |          |
        |      Loop Name      |   min   |   max   |  Latency |  achieved |   target  | Count| Pipelined|
        +---------------------+---------+---------+----------+-----------+-----------+------+----------+
        |- Loop 1             |  3494764|  3494764|     38404|          -|          -|    91|    no    |
        | + Loop 1.1          |    38402|    38402|       422|          -|          -|    91|    no    |
        |  ++ Loop 1.1.1      |      420|      420|        42|          -|          -|    10|    no    |
        |   +++ Loop 1.1.1.1  |       40|       40|         4|          -|          -|    10|    no    |
        +---------------------+---------+---------+----------+-----------+-----------+------+----------+

============================================================
+ Verbose Summary: Synthesis Manager
============================================================
InlineROM: 1
ExposeGlobal: 0
============================================================
+ Verbose Summary: CDFG Model
============================================================
IsTopModel: 1
ResetActiveHigh: 1
IsCombinational: 0
IsDatapathOnly: 0
HasWiredReturn: 1
HasMFsm: 0
HasVarLatency: 1
IsPipeline: 0
IsRtlPipelined: 0
IsInstanceOverlapped: 0
IsDontTouch: 0
HasImplIP: 0
IsGatedGlobalClock: 0


============================================================
+ Verbose Summary: Schedule
============================================================
* Number of FSM states : 8
* Pipeline : 0
* Dataflow Pipeline: 0

* FSM state transitions: 
1 --> 
	2  / true
2 --> 
	3  / (!exitcond3)
3 --> 
	4  / (!exitcond2)
	2  / (exitcond2)
4 --> 
	5  / (!exitcond1)
	3  / (exitcond1)
5 --> 
	6  / (!exitcond)
	4  / (exitcond)
6 --> 
	7  / true
7 --> 
	8  / true
8 --> 
	5  / true

* FSM state operations: 

 <State 1> : 1.77ns
ST_1 : Operation 9 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecBitsMap([10000 x i32]* %A) nounwind, !map !7"
ST_1 : Operation 10 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecBitsMap([100 x i32]* %B) nounwind, !map !13"
ST_1 : Operation 11 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecBitsMap([8281 x i32]* %C) nounwind, !map !19"
ST_1 : Operation 12 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecTopModule([12 x i8]* @convolution_str) nounwind"
ST_1 : Operation 13 [1/1] (1.76ns)   --->   "br label %.loopexit1" [edge_detection/edge_detection.cpp:10]

 <State 2> : 2.04ns
ST_2 : Operation 14 [1/1] (0.00ns)   --->   "%i = phi i7 [ 0, %0 ], [ %i_1, %.loopexit1.loopexit ]"
ST_2 : Operation 15 [1/1] (0.00ns)   --->   "%phi_mul = phi i14 [ 0, %0 ], [ %next_mul, %.loopexit1.loopexit ]"
ST_2 : Operation 16 [1/1] (2.03ns)   --->   "%next_mul = add i14 %phi_mul, 91"   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.55> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_2 : Operation 17 [1/1] (1.48ns)   --->   "%exitcond3 = icmp eq i7 %i, -37" [edge_detection/edge_detection.cpp:10]   --->   Core 25 'Cmp' <Latency = 0> <II = 1> <Delay = 1.30> <FuncUnit> <Opcode : 'icmp'> <InPorts = 2> <OutPorts = 1>
ST_2 : Operation 18 [1/1] (0.00ns)   --->   "%empty = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 91, i64 91, i64 91) nounwind"
ST_2 : Operation 19 [1/1] (1.87ns)   --->   "%i_1 = add i7 %i, 1" [edge_detection/edge_detection.cpp:10]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.55> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_2 : Operation 20 [1/1] (0.00ns)   --->   "br i1 %exitcond3, label %3, label %.preheader4.preheader" [edge_detection/edge_detection.cpp:10]
ST_2 : Operation 21 [1/1] (1.76ns)   --->   "br label %.preheader4" [edge_detection/edge_detection.cpp:11]
ST_2 : Operation 22 [1/1] (0.00ns)   --->   "ret void" [edge_detection/edge_detection.cpp:20]

 <State 3> : 5.29ns
ST_3 : Operation 23 [1/1] (0.00ns)   --->   "%j = phi i7 [ %j_1, %.preheader4.loopexit ], [ 0, %.preheader4.preheader ]"
ST_3 : Operation 24 [1/1] (0.00ns)   --->   "%j_cast5 = zext i7 %j to i14" [edge_detection/edge_detection.cpp:11]
ST_3 : Operation 25 [1/1] (1.48ns)   --->   "%exitcond2 = icmp eq i7 %j, -37" [edge_detection/edge_detection.cpp:11]   --->   Core 25 'Cmp' <Latency = 0> <II = 1> <Delay = 1.30> <FuncUnit> <Opcode : 'icmp'> <InPorts = 2> <OutPorts = 1>
ST_3 : Operation 26 [1/1] (0.00ns)   --->   "%empty_2 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 91, i64 91, i64 91) nounwind"
ST_3 : Operation 27 [1/1] (1.87ns)   --->   "%j_1 = add i7 %j, 1" [edge_detection/edge_detection.cpp:11]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.55> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_3 : Operation 28 [1/1] (0.00ns)   --->   "br i1 %exitcond2, label %.loopexit1.loopexit, label %1" [edge_detection/edge_detection.cpp:11]
ST_3 : Operation 29 [1/1] (2.03ns)   --->   "%tmp_2 = add i14 %phi_mul, %j_cast5" [edge_detection/edge_detection.cpp:12]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.55> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_3 : Operation 30 [1/1] (0.00ns)   --->   "%tmp_3 = zext i14 %tmp_2 to i64" [edge_detection/edge_detection.cpp:12]
ST_3 : Operation 31 [1/1] (0.00ns)   --->   "%C_addr = getelementptr [8281 x i32]* %C, i64 0, i64 %tmp_3" [edge_detection/edge_detection.cpp:12]
ST_3 : Operation 32 [1/1] (3.25ns)   --->   "store i32 0, i32* %C_addr, align 4" [edge_detection/edge_detection.cpp:12]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 3.25> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 8281> <RAM>
ST_3 : Operation 33 [1/1] (1.76ns)   --->   "br label %.loopexit" [edge_detection/edge_detection.cpp:13]
ST_3 : Operation 34 [1/1] (0.00ns)   --->   "br label %.loopexit1"

 <State 4> : 6.04ns
ST_4 : Operation 35 [1/1] (0.00ns)   --->   "%k = phi i4 [ 0, %1 ], [ %k_1, %.loopexit.loopexit ]"
ST_4 : Operation 36 [1/1] (0.00ns)   --->   "%k_cast4 = zext i4 %k to i7" [edge_detection/edge_detection.cpp:13]
ST_4 : Operation 37 [1/1] (1.30ns)   --->   "%exitcond1 = icmp eq i4 %k, -6" [edge_detection/edge_detection.cpp:13]   --->   Core 25 'Cmp' <Latency = 0> <II = 1> <Delay = 1.30> <FuncUnit> <Opcode : 'icmp'> <InPorts = 2> <OutPorts = 1>
ST_4 : Operation 38 [1/1] (0.00ns)   --->   "%empty_3 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 10, i64 10, i64 10) nounwind"
ST_4 : Operation 39 [1/1] (1.73ns)   --->   "%k_1 = add i4 %k, 1" [edge_detection/edge_detection.cpp:13]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.55> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_4 : Operation 40 [1/1] (0.00ns)   --->   "br i1 %exitcond1, label %.preheader4.loopexit, label %.preheader.preheader" [edge_detection/edge_detection.cpp:13]
ST_4 : Operation 41 [1/1] (1.87ns)   --->   "%tmp_5 = add i7 %k_cast4, %i" [edge_detection/edge_detection.cpp:15]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.55> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_4 : Operation 42 [1/1] (0.00ns)   --->   "%tmp_5_cast_cast = zext i7 %tmp_5 to i14" [edge_detection/edge_detection.cpp:15]
ST_4 : Operation 43 [1/1] (4.17ns)   --->   "%tmp_6 = mul i14 %tmp_5_cast_cast, 100" [edge_detection/edge_detection.cpp:15]   --->   Core 16 'Mul' <Latency = 0> <II = 1> <Delay = 8.51> <FuncUnit> <Opcode : 'mul'> <InPorts = 2> <OutPorts = 1>
ST_4 : Operation 44 [1/1] (0.00ns)   --->   "%p_shl = call i7 @_ssdm_op_BitConcatenate.i7.i4.i3(i4 %k, i3 0)" [edge_detection/edge_detection.cpp:15]
ST_4 : Operation 45 [1/1] (0.00ns)   --->   "%p_shl8 = call i5 @_ssdm_op_BitConcatenate.i5.i4.i1(i4 %k, i1 false)" [edge_detection/edge_detection.cpp:15]
ST_4 : Operation 46 [1/1] (1.76ns)   --->   "br label %.preheader" [edge_detection/edge_detection.cpp:14]
ST_4 : Operation 47 [1/1] (0.00ns)   --->   "br label %.preheader4"

 <State 5> : 7.10ns
ST_5 : Operation 48 [1/1] (0.00ns)   --->   "%l = phi i4 [ %l_1, %2 ], [ 0, %.preheader.preheader ]"
ST_5 : Operation 49 [1/1] (0.00ns)   --->   "%l_cast3 = zext i4 %l to i14" [edge_detection/edge_detection.cpp:14]
ST_5 : Operation 50 [1/1] (0.00ns)   --->   "%l_cast = zext i4 %l to i5" [edge_detection/edge_detection.cpp:14]
ST_5 : Operation 51 [1/1] (1.30ns)   --->   "%exitcond = icmp eq i4 %l, -6" [edge_detection/edge_detection.cpp:14]   --->   Core 25 'Cmp' <Latency = 0> <II = 1> <Delay = 1.30> <FuncUnit> <Opcode : 'icmp'> <InPorts = 2> <OutPorts = 1>
ST_5 : Operation 52 [1/1] (0.00ns)   --->   "%empty_4 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 10, i64 10, i64 10) nounwind"
ST_5 : Operation 53 [1/1] (1.73ns)   --->   "%l_1 = add i4 %l, 1" [edge_detection/edge_detection.cpp:14]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.55> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_5 : Operation 54 [1/1] (0.00ns)   --->   "br i1 %exitcond, label %.loopexit.loopexit, label %2" [edge_detection/edge_detection.cpp:14]
ST_5 : Operation 55 [1/1] (0.00ns) (grouped into TernaryAdder)   --->   "%tmp1 = add i14 %tmp_6, %l_cast3" [edge_detection/edge_detection.cpp:15]   --->   Core 80 'TAddSub' <Latency = 0> <II = 1> <Delay = 1.92> <IPBlock> <Opcode : 'add' 'sub'> <InPorts = 3> <OutPorts = 1> <Sync> <CReg>
ST_5 : Operation 56 [1/1] (3.84ns) (root node of TernaryAdder)   --->   "%tmp_s = add i14 %tmp1, %j_cast5" [edge_detection/edge_detection.cpp:15]   --->   Core 80 'TAddSub' <Latency = 0> <II = 1> <Delay = 1.92> <IPBlock> <Opcode : 'add' 'sub'> <InPorts = 3> <OutPorts = 1> <Sync> <CReg>
ST_5 : Operation 57 [1/1] (0.00ns)   --->   "%tmp_1 = zext i14 %tmp_s to i64" [edge_detection/edge_detection.cpp:15]
ST_5 : Operation 58 [1/1] (0.00ns)   --->   "%A_addr = getelementptr [10000 x i32]* %A, i64 0, i64 %tmp_1" [edge_detection/edge_detection.cpp:15]
ST_5 : Operation 59 [2/2] (3.25ns)   --->   "%A_load = load i32* %A_addr, align 4" [edge_detection/edge_detection.cpp:15]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 3.25> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 8281> <RAM>
ST_5 : Operation 60 [1/1] (1.78ns)   --->   "%tmp2 = add i5 %p_shl8, %l_cast" [edge_detection/edge_detection.cpp:15]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.55> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_5 : Operation 61 [1/1] (0.00ns)   --->   "%tmp2_cast = zext i5 %tmp2 to i7" [edge_detection/edge_detection.cpp:15]
ST_5 : Operation 62 [1/1] (1.87ns)   --->   "%tmp_4 = add i7 %tmp2_cast, %p_shl" [edge_detection/edge_detection.cpp:15]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.55> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_5 : Operation 63 [1/1] (0.00ns)   --->   "%tmp_8 = zext i7 %tmp_4 to i64" [edge_detection/edge_detection.cpp:15]
ST_5 : Operation 64 [1/1] (0.00ns)   --->   "%B_addr = getelementptr [100 x i32]* %B, i64 0, i64 %tmp_8" [edge_detection/edge_detection.cpp:15]
ST_5 : Operation 65 [2/2] (3.25ns)   --->   "%B_load = load i32* %B_addr, align 4" [edge_detection/edge_detection.cpp:15]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 3.25> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 8281> <RAM>
ST_5 : Operation 66 [1/1] (0.00ns)   --->   "br label %.loopexit"

 <State 6> : 3.25ns
ST_6 : Operation 67 [1/2] (3.25ns)   --->   "%A_load = load i32* %A_addr, align 4" [edge_detection/edge_detection.cpp:15]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 3.25> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 8281> <RAM>
ST_6 : Operation 68 [1/2] (3.25ns)   --->   "%B_load = load i32* %B_addr, align 4" [edge_detection/edge_detection.cpp:15]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 3.25> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 8281> <RAM>
ST_6 : Operation 69 [2/2] (3.25ns)   --->   "%C_load = load i32* %C_addr, align 4" [edge_detection/edge_detection.cpp:15]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 3.25> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 8281> <RAM>

 <State 7> : 8.51ns
ST_7 : Operation 70 [1/1] (8.51ns)   --->   "%tmp_7 = mul nsw i32 %A_load, %B_load" [edge_detection/edge_detection.cpp:15]   --->   Core 16 'Mul' <Latency = 0> <II = 1> <Delay = 8.51> <FuncUnit> <Opcode : 'mul'> <InPorts = 2> <OutPorts = 1>
ST_7 : Operation 71 [1/2] (3.25ns)   --->   "%C_load = load i32* %C_addr, align 4" [edge_detection/edge_detection.cpp:15]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 3.25> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 8281> <RAM>

 <State 8> : 5.81ns
ST_8 : Operation 72 [1/1] (2.55ns)   --->   "%tmp_9 = add nsw i32 %C_load, %tmp_7" [edge_detection/edge_detection.cpp:15]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.55> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_8 : Operation 73 [1/1] (3.25ns)   --->   "store i32 %tmp_9, i32* %C_addr, align 4" [edge_detection/edge_detection.cpp:15]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 3.25> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 8281> <RAM>
ST_8 : Operation 74 [1/1] (0.00ns)   --->   "br label %.preheader" [edge_detection/edge_detection.cpp:14]


============================================================
+ Verbose Summary: Timing violations
============================================================
Target clock period: 10ns, clock uncertainty: 1.25ns.

 <State 1>: 1.77ns
The critical path consists of the following:
	multiplexor before 'phi' operation ('i') with incoming values : ('i', edge_detection/edge_detection.cpp:10) [10]  (1.77 ns)

 <State 2>: 2.04ns
The critical path consists of the following:
	'phi' operation ('phi_mul') with incoming values : ('next_mul') [11]  (0 ns)
	'add' operation ('next_mul') [12]  (2.04 ns)

 <State 3>: 5.29ns
The critical path consists of the following:
	'phi' operation ('j') with incoming values : ('j', edge_detection/edge_detection.cpp:11) [20]  (0 ns)
	'add' operation ('tmp_2', edge_detection/edge_detection.cpp:12) [27]  (2.04 ns)
	'getelementptr' operation ('C_addr', edge_detection/edge_detection.cpp:12) [29]  (0 ns)
	'store' operation (edge_detection/edge_detection.cpp:12) of constant 0 on array 'C' [30]  (3.25 ns)

 <State 4>: 6.04ns
The critical path consists of the following:
	'phi' operation ('k') with incoming values : ('k', edge_detection/edge_detection.cpp:13) [33]  (0 ns)
	'add' operation ('tmp_5', edge_detection/edge_detection.cpp:15) [40]  (1.87 ns)
	'mul' operation ('tmp_6', edge_detection/edge_detection.cpp:15) [42]  (4.17 ns)

 <State 5>: 7.1ns
The critical path consists of the following:
	'phi' operation ('l') with incoming values : ('l', edge_detection/edge_detection.cpp:14) [47]  (0 ns)
	'add' operation ('tmp1', edge_detection/edge_detection.cpp:15) [55]  (0 ns)
	'add' operation ('tmp_s', edge_detection/edge_detection.cpp:15) [56]  (3.84 ns)
	'getelementptr' operation ('A_addr', edge_detection/edge_detection.cpp:15) [58]  (0 ns)
	'load' operation ('A_load', edge_detection/edge_detection.cpp:15) on array 'A' [59]  (3.25 ns)

 <State 6>: 3.25ns
The critical path consists of the following:
	'load' operation ('A_load', edge_detection/edge_detection.cpp:15) on array 'A' [59]  (3.25 ns)

 <State 7>: 8.51ns
The critical path consists of the following:
	'mul' operation ('tmp_7', edge_detection/edge_detection.cpp:15) [66]  (8.51 ns)

 <State 8>: 5.81ns
The critical path consists of the following:
	'add' operation ('tmp_9', edge_detection/edge_detection.cpp:15) [68]  (2.55 ns)
	'store' operation (edge_detection/edge_detection.cpp:15) of variable 'tmp_9', edge_detection/edge_detection.cpp:15 on array 'C' [69]  (3.25 ns)


============================================================
+ Verbose Summary: Binding
============================================================
N/A
* FSMD analyzer results:
  - Output states:
 - Input state : 
  - Chain level:
	State 1
	State 2
	State 3
	State 4
	State 5
	State 6
	State 7
	State 8


============================================================
+ Verbose Summary: Datapath Resource usage 
============================================================
N/A