================================================================
== Vivado HLS Report for 'convolution'
================================================================
* Date:           Fri May 25 13:57:07 2018

* Version:        2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017)
* Project:        edge_detection
* Solution:       solution1
* Product family: zynq
* Target device:  xc7z020clg484-1


================================================================
== Performance Estimates
================================================================
+ Timing (ns): 
    * Summary: 
    +--------+-------+----------+------------+
    |  Clock | Target| Estimated| Uncertainty|
    +--------+-------+----------+------------+
    |ap_clk  |  10.00|      8.51|        1.25|
    +--------+-------+----------+------------+

+ Latency (clock cycles): 
    * Summary: 
    +---------+---------+---------+---------+---------+
    |      Latency      |      Interval     | Pipeline|
    |   min   |   max   |   min   |   max   |   Type  |
    +---------+---------+---------+---------+---------+
    |  3494765|  3494765|  3494765|  3494765|   none  |
    +---------+---------+---------+---------+---------+

    + Detail: 
        * Instance: 
        N/A

        * Loop: 
        +---------------------+---------+---------+----------+-----------+-----------+------+----------+
        |                     |      Latency      | Iteration|  Initiation Interval  | Trip |          |
        |      Loop Name      |   min   |   max   |  Latency |  achieved |   target  | Count| Pipelined|
        +---------------------+---------+---------+----------+-----------+-----------+------+----------+
        |- Loop 1             |  3494764|  3494764|     38404|          -|          -|    91|    no    |
        | + Loop 1.1          |    38402|    38402|       422|          -|          -|    91|    no    |
        |  ++ Loop 1.1.1      |      420|      420|        42|          -|          -|    10|    no    |
        |   +++ Loop 1.1.1.1  |       40|       40|         4|          -|          -|    10|    no    |
        +---------------------+---------+---------+----------+-----------+-----------+------+----------+

============================================================
+ Verbose Summary: Synthesis Manager
============================================================
InlineROM: 1
ExposeGlobal: 0
============================================================
+ Verbose Summary: CDFG Model
============================================================
IsTopModel: 1
ResetActiveHigh: 1
IsCombinational: 0
IsDatapathOnly: 0
HasWiredReturn: 1
HasMFsm: 0
HasVarLatency: 1
IsPipeline: 0
IsRtlPipelined: 0
IsInstanceOverlapped: 0
IsDontTouch: 0
HasImplIP: 0
IsGatedGlobalClock: 0


============================================================
+ Verbose Summary: Schedule
============================================================
* Number of FSM states : 8
* Pipeline : 0
* Dataflow Pipeline: 0

* FSM state transitions: 
1 --> 
	2  / true
2 --> 
	3  / (!exitcond3)
3 --> 
	4  / (!exitcond2)
	2  / (exitcond2)
4 --> 
	5  / (!exitcond1)
	3  / (exitcond1)
5 --> 
	6  / (!exitcond)
	4  / (exitcond)
6 --> 
	7  / true
7 --> 
	8  / true
8 --> 
	5  / true

* FSM state operations: 

 <State 1> : 1.77ns
ST_1 : Operation 9 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecBitsMap([10000 x i32]* %A) nounwind, !map !7"
ST_1 : Operation 10 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecBitsMap([100 x i32]* %B) nounwind, !map !13"
ST_1 : Operation 11 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecBitsMap([8281 x i32]* %C) nounwind, !map !19"
ST_1 : Operation 12 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecTopModule([12 x i8]* @convolution_str) nounwind"
ST_1 : Operation 13 [1/1] (1.76ns)   --->   "br label %.loopexit1" [edge_detection/edge_detection.cpp:10]

 <State 2> : 2.04ns
ST_2 : Operation 14 [1/1] (0.00ns)   --->   "%i = phi i7 [ 0, %0 ], [ %i_1, %.loopexit1.loopexit ]"
ST_2 : Operation 15 [1/1] (0.00ns)   --->   "%phi_mul = phi i14 [ 0, %0 ], [ %next_mul, %.loopexit1.loopexit ]"
ST_2 : Operation 16 [1/1] (2.03ns)   --->   "%next_mul = add i14 %phi_mul, 91"   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.55> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_2 : Operation 17 [1/1] (1.48ns)   --->   "%exitcond3 = icmp eq i7 %i, -37" [edge_detection/edge_detection.cpp:10]   --->   Core 25 'Cmp' <Latency = 0> <II = 1> <Delay = 1.30> <FuncUnit> <Opcode : 'icmp'> <InPorts = 2> <OutPorts = 1>
ST_2 : Operation 18 [1/1] (0.00ns)   --->   "%empty = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 91, i64 91, i64 91) nounwind"
ST_2 : Operation 19 [1/1] (1.87ns)   --->   "%i_1 = add i7 %i, 1" [edge_detection/edge_detection.cpp:10]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.55> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_2 : Operation 20 [1/1] (0.00ns)   --->   "br i1 %exitcond3, label %3, label %.preheader4.preheader" [edge_detection/edge_detection.cpp:10]
ST_2 : Operation 21 [1/1] (1.76ns)   --->   "br label %.preheader4" [edge_detection/edge_detection.cpp:11]
ST_2 : Operation 22 [1/1] (0.00ns)   --->   "ret void" [edge_detection/edge_detection.cpp:20]

 <State 3> : 5.29ns
ST_3 : Operation 23 [1/1] (0.00ns)   --->   "%j = phi i7 [ %j_1, %.preheader4.loopexit ], [ 0, %.preheader4.preheader ]"
ST_3 : Operation 24 [1/1] (0.00ns)   --->   "%j_cast5 = zext i7 %j to i14" [edge_detection/edge_detection.cpp:11]
ST_3 : Operation 25 [1/1] (1.48ns)   --->   "%exitcond2 = icmp eq i7 %j, -37" [edge_detection/edge_detection.cpp:11]   --->   Core 25 'Cmp' <Latency = 0> <II = 1> <Delay = 1.30> <FuncUnit> <Opcode : 'icmp'> <InPorts = 2> <OutPorts = 1>
ST_3 : Operation 26 [1/1] (0.00ns)   --->   "%empty_2 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 91, i64 91, i64 91) nounwind"
ST_3 : Operation 27 [1/1] (1.87ns)   --->   "%j_1 = add i7 %j, 1" [edge_detection/edge_detection.cpp:11]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.55> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_3 : Operation 28 [1/1] (0.00ns)   --->   "br i1 %exitcond2, label %.loopexit1.loopexit, label %1" [edge_detection/edge_detection.cpp:11]
ST_3 : Operation 29 [1/1] (2.03ns)   --->   "%tmp_2 = add i14 %phi_mul, %j_cast5" [edge_detection/edge_detection.cpp:12]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.55> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_3 : Operation 30 [1/1] (0.00ns)   --->   "%tmp_3 = zext i14 %tmp_2 to i64" [edge_detection/edge_detection.cpp:12]
ST_3 : Operation 31 [1/1] (0.00ns)   --->   "%C_addr = getelementptr [8281 x i32]* %C, i64 0, i64 %tmp_3" [edge_detection/edge_detection.cpp:12]
ST_3 : Operation 32 [1/1] (3.25ns)   --->   "store i32 0, i32* %C_addr, align 4" [edge_detection/edge_detection.cpp:12]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 3.25> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 8281> <RAM>
ST_3 : Operation 33 [1/1] (1.76ns)   --->   "br label %.loopexit" [edge_detection/edge_detection.cpp:13]
ST_3 : Operation 34 [1/1] (0.00ns)   --->   "br label %.loopexit1"

 <State 4> : 6.04ns
ST_4 : Operation 35 [1/1] (0.00ns)   --->   "%k = phi i4 [ 0, %1 ], [ %k_1, %.loopexit.loopexit ]"
ST_4 : Operation 36 [1/1] (0.00ns)   --->   "%k_cast4 = zext i4 %k to i7" [edge_detection/edge_detection.cpp:13]
ST_4 : Operation 37 [1/1] (1.30ns)   --->   "%exitcond1 = icmp eq i4 %k, -6" [edge_detection/edge_detection.cpp:13]   --->   Core 25 'Cmp' <Latency = 0> <II = 1> <Delay = 1.30> <FuncUnit> <Opcode : 'icmp'> <InPorts = 2> <OutPorts = 1>
ST_4 : Operation 38 [1/1] (0.00ns)   --->   "%empty_3 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 10, i64 10, i64 10) nounwind"
ST_4 : Operation 39 [1/1] (1.73ns)   --->   "%k_1 = add i4 %k, 1" [edge_detection/edge_detection.cpp:13]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.55> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_4 : Operation 40 [1/1] (0.00ns)   --->   "br i1 %exitcond1, label %.preheader4.loopexit, label %.preheader.preheader" [edge_detection/edge_detection.cpp:13]
ST_4 : Operation 41 [1/1] (1.87ns)   --->   "%tmp_5 = add i7 %k_cast4, %i" [edge_detection/edge_detection.cpp:15]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.55> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_4 : Operation 42 [1/1] (0.00ns)   --->   "%tmp_5_cast_cast = zext i7 %tmp_5 to i14" [edge_detection/edge_detection.cpp:15]
ST_4 : Operation 43 [1/1] (4.17ns)   --->   "%tmp_6 = mul i14 %tmp_5_cast_cast, 100" [edge_detection/edge_detection.cpp:15]   --->   Core 16 'Mul' <Latency = 0> <II = 1> <Delay = 8.51> <FuncUnit> <Opcode : 'mul'> <InPorts = 2> <OutPorts = 1>
ST_4 : Operation 44 [1/1] (0.00ns)   --->   "%p_shl = call i7 @_ssdm_op_BitConcatenate.i7.i4.i3(i4 %k, i3 0)" [edge_detection/edge_detection.cpp:15]
ST_4 : Operation 45 [1/1] (0.00ns)   --->   "%p_shl8 = call i5 @_ssdm_op_BitConcatenate.i5.i4.i1(i4 %k, i1 false)" [edge_detection/edge_detection.cpp:15]
ST_4 : Operation 46 [1/1] (1.76ns)   --->   "br label %.preheader" [edge_detection/edge_detection.cpp:14]
ST_4 : Operation 47 [1/1] (0.00ns)   --->   "br label %.preheader4"

 <State 5> : 7.10ns
ST_5 : Operation 48 [1/1] (0.00ns)   --->   "%l = phi i4 [ %l_1, %2 ], [ 0, %.preheader.preheader ]"
ST_5 : Operation 49 [1/1] (0.00ns)   --->   "%l_cast3 = zext i4 %l to i14" [edge_detection/edge_detection.cpp:14]
ST_5 : Operation 50 [1/1] (0.00ns)   --->   "%l_cast = zext i4 %l to i5" [edge_detection/edge_detection.cpp:14]
ST_5 : Operation 51 [1/1] (1.30ns)   --->   "%exitcond = icmp eq i4 %l, -6" [edge_detection/edge_detection.cpp:14]   --->   Core 25 'Cmp' <Latency = 0> <II = 1> <Delay = 1.30> <FuncUnit> <Opcode : 'icmp'> <InPorts = 2> <OutPorts = 1>
ST_5 : Operation 52 [1/1] (0.00ns)   --->   "%empty_4 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 10, i64 10, i64 10) nounwind"
ST_5 : Operation 53 [1/1] (1.73ns)   --->   "%l_1 = add i4 %l, 1" [edge_detection/edge_detection.cpp:14]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.55> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_5 : Operation 54 [1/1] (0.00ns)   --->   "br i1 %exitcond, label %.loopexit.loopexit, label %2" [edge_detection/edge_detection.cpp:14]
ST_5 : Operation 55 [1/1] (0.00ns) (grouped into TernaryAdder)   --->   "%tmp1 = add i14 %tmp_6, %l_cast3" [edge_detection/edge_detection.cpp:15]   --->   Core 80 'TAddSub' <Latency = 0> <II = 1> <Delay = 1.92> <IPBlock> <Opcode : 'add' 'sub'> <InPorts = 3> <OutPorts = 1> <Sync> <CReg>
ST_5 : Operation 56 [1/1] (3.84ns) (root node of TernaryAdder)   --->   "%tmp_s = add i14 %tmp1, %j_cast5" [edge_detection/edge_detection.cpp:15]   --->   Core 80 'TAddSub' <Latency = 0> <II = 1> <Delay = 1.92> <IPBlock> <Opcode : 'add' 'sub'> <InPorts = 3> <OutPorts = 1> <Sync> <CReg>
ST_5 : Operation 57 [1/1] (0.00ns)   --->   "%tmp_1 = zext i14 %tmp_s to i64" [edge_detection/edge_detection.cpp:15]
ST_5 : Operation 58 [1/1] (0.00ns)   --->   "%A_addr = getelementptr [10000 x i32]* %A, i64 0, i64 %tmp_1" [edge_detection/edge_detection.cpp:15]
ST_5 : Operation 59 [2/2] (3.25ns)   --->   "%A_load = load i32* %A_addr, align 4" [edge_detection/edge_detection.cpp:15]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 3.25> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 8281> <RAM>
ST_5 : Operation 60 [1/1] (1.78ns)   --->   "%tmp2 = add i5 %p_shl8, %l_cast" [edge_detection/edge_detection.cpp:15]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.55> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_5 : Operation 61 [1/1] (0.00ns)   --->   "%tmp2_cast = zext i5 %tmp2 to i7" [edge_detection/edge_detection.cpp:15]
ST_5 : Operation 62 [1/1] (1.87ns)   --->   "%tmp_4 = add i7 %tmp2_cast, %p_shl" [edge_detection/edge_detection.cpp:15]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.55> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_5 : Operation 63 [1/1] (0.00ns)   --->   "%tmp_8 = zext i7 %tmp_4 to i64" [edge_detection/edge_detection.cpp:15]
ST_5 : Operation 64 [1/1] (0.00ns)   --->   "%B_addr = getelementptr [100 x i32]* %B, i64 0, i64 %tmp_8" [edge_detection/edge_detection.cpp:15]
ST_5 : Operation 65 [2/2] (3.25ns)   --->   "%B_load = load i32* %B_addr, align 4" [edge_detection/edge_detection.cpp:15]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 3.25> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 8281> <RAM>
ST_5 : Operation 66 [1/1] (0.00ns)   --->   "br label %.loopexit"

 <State 6> : 3.25ns
ST_6 : Operation 67 [1/2] (3.25ns)   --->   "%A_load = load i32* %A_addr, align 4" [edge_detection/edge_detection.cpp:15]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 3.25> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 8281> <RAM>
ST_6 : Operation 68 [1/2] (3.25ns)   --->   "%B_load = load i32* %B_addr, align 4" [edge_detection/edge_detection.cpp:15]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 3.25> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 8281> <RAM>
ST_6 : Operation 69 [2/2] (3.25ns)   --->   "%C_load = load i32* %C_addr, align 4" [edge_detection/edge_detection.cpp:15]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 3.25> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 8281> <RAM>

 <State 7> : 8.51ns
ST_7 : Operation 70 [1/1] (8.51ns)   --->   "%tmp_7 = mul nsw i32 %A_load, %B_load" [edge_detection/edge_detection.cpp:15]   --->   Core 16 'Mul' <Latency = 0> <II = 1> <Delay = 8.51> <FuncUnit> <Opcode : 'mul'> <InPorts = 2> <OutPorts = 1>
ST_7 : Operation 71 [1/2] (3.25ns)   --->   "%C_load = load i32* %C_addr, align 4" [edge_detection/edge_detection.cpp:15]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 3.25> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 8281> <RAM>

 <State 8> : 5.81ns
ST_8 : Operation 72 [1/1] (2.55ns)   --->   "%tmp_9 = add nsw i32 %C_load, %tmp_7" [edge_detection/edge_detection.cpp:15]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 2.55> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_8 : Operation 73 [1/1] (3.25ns)   --->   "store i32 %tmp_9, i32* %C_addr, align 4" [edge_detection/edge_detection.cpp:15]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 3.25> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 8281> <RAM>
ST_8 : Operation 74 [1/1] (0.00ns)   --->   "br label %.preheader" [edge_detection/edge_detection.cpp:14]


============================================================
+ Verbose Summary: Binding
============================================================
STG Binding: 
---------------- STG Properties BEGIN ----------------
- Is combinational: 0
- Is one-state seq: 0
- Is datapath-only: 0
- Is pipelined: 0
- Is top level: 1
Port [ Return ] is wired: 1; IO mode=ap_ctrl_hs:ce=0
Port [ A]:  wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=1; pingpong=0; private_global=0; MemPort=[13]; IO mode=ap_memory:ce=0
Port [ B]:  wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=1; pingpong=0; private_global=0; MemPort=[13]; IO mode=ap_memory:ce=0
Port [ C]:  wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=2; type=1; pingpong=0; private_global=0; MemPort=[23]; IO mode=ap_memory:ce=0
---------------- STG Properties END ------------------

---------------- Datapath Model BEGIN ----------------

<LifeTime>
<method=bitvector/>
StgValue_9      (specbitsmap      ) [ 000000000]
StgValue_10     (specbitsmap      ) [ 000000000]
StgValue_11     (specbitsmap      ) [ 000000000]
StgValue_12     (spectopmodule    ) [ 000000000]
StgValue_13     (br               ) [ 011111111]
i               (phi              ) [ 001011111]
phi_mul         (phi              ) [ 001111111]
next_mul        (add              ) [ 011111111]
exitcond3       (icmp             ) [ 001111111]
empty           (speclooptripcount) [ 000000000]
i_1             (add              ) [ 011111111]
StgValue_20     (br               ) [ 000000000]
StgValue_21     (br               ) [ 001111111]
StgValue_22     (ret              ) [ 000000000]
j               (phi              ) [ 000100000]
j_cast5         (zext             ) [ 000011111]
exitcond2       (icmp             ) [ 001111111]
empty_2         (speclooptripcount) [ 000000000]
j_1             (add              ) [ 001111111]
StgValue_28     (br               ) [ 000000000]
tmp_2           (add              ) [ 000000000]
tmp_3           (zext             ) [ 000000000]
C_addr          (getelementptr    ) [ 000011111]
StgValue_32     (store            ) [ 000000000]
StgValue_33     (br               ) [ 001111111]
StgValue_34     (br               ) [ 011111111]
k               (phi              ) [ 000010000]
k_cast4         (zext             ) [ 000000000]
exitcond1       (icmp             ) [ 001111111]
empty_3         (speclooptripcount) [ 000000000]
k_1             (add              ) [ 001111111]
StgValue_40     (br               ) [ 000000000]
tmp_5           (add              ) [ 000000000]
tmp_5_cast_cast (zext             ) [ 000000000]
tmp_6           (mul              ) [ 000001111]
p_shl           (bitconcatenate   ) [ 000001111]
p_shl8          (bitconcatenate   ) [ 000001111]
StgValue_46     (br               ) [ 001111111]
StgValue_47     (br               ) [ 001111111]
l               (phi              ) [ 000001000]
l_cast3         (zext             ) [ 000000000]
l_cast          (zext             ) [ 000000000]
exitcond        (icmp             ) [ 001111111]
empty_4         (speclooptripcount) [ 000000000]
l_1             (add              ) [ 001111111]
StgValue_54     (br               ) [ 000000000]
tmp1            (add              ) [ 000000000]
tmp_s           (add              ) [ 000000000]
tmp_1           (zext             ) [ 000000000]
A_addr          (getelementptr    ) [ 000000100]
tmp2            (add              ) [ 000000000]
tmp2_cast       (zext             ) [ 000000000]
tmp_4           (add              ) [ 000000000]
tmp_8           (zext             ) [ 000000000]
B_addr          (getelementptr    ) [ 000000100]
StgValue_66     (br               ) [ 001111111]
A_load          (load             ) [ 000000010]
B_load          (load             ) [ 000000010]
tmp_7           (mul              ) [ 000000001]
C_load          (load             ) [ 000000001]
tmp_9           (add              ) [ 000000000]
StgValue_73     (store            ) [ 000000000]
StgValue_74     (br               ) [ 001111111]
</LifeTime>

<model>

<comp_list>
<comp id="0" class="1000" name="A">
<pin_list>
<pin id="1" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="A"/><MemPortTyVec>1 3 </MemPortTyVec>
</StgValue>
</bind>
</comp>

<comp id="2" class="1000" name="B">
<pin_list>
<pin id="3" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="B"/><MemPortTyVec>1 3 </MemPortTyVec>
</StgValue>
</bind>
</comp>

<comp id="4" class="1000" name="C">
<pin_list>
<pin id="5" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="C"/><MemPortTyVec>2 3 </MemPortTyVec>
</StgValue>
</bind>
</comp>

<comp id="6" class="1001" name="const_6">
<pin_list>
<pin id="7" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecBitsMap"/></StgValue>
</bind>
</comp>

<comp id="8" class="1001" name="const_8">
<pin_list>
<pin id="9" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecTopModule"/></StgValue>
</bind>
</comp>

<comp id="10" class="1001" name="const_10">
<pin_list>
<pin id="11" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="convolution_str"/></StgValue>
</bind>
</comp>

<comp id="12" class="1001" name="const_12">
<pin_list>
<pin id="13" dir="1" index="0" bw="1" slack="1"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="14" class="1001" name="const_14">
<pin_list>
<pin id="15" dir="1" index="0" bw="1" slack="1"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="16" class="1001" name="const_16">
<pin_list>
<pin id="17" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="18" class="1001" name="const_18">
<pin_list>
<pin id="19" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="20" class="1001" name="const_20">
<pin_list>
<pin id="21" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecLoopTripCount"/></StgValue>
</bind>
</comp>

<comp id="22" class="1001" name="const_22">
<pin_list>
<pin id="23" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="24" class="1001" name="const_24">
<pin_list>
<pin id="25" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="26" class="1001" name="const_26">
<pin_list>
<pin id="27" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="28" class="1001" name="const_28">
<pin_list>
<pin id="29" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="30" class="1001" name="const_30">
<pin_list>
<pin id="31" dir="1" index="0" bw="1" slack="1"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="32" class="1001" name="const_32">
<pin_list>
<pin id="33" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="34" class="1001" name="const_34">
<pin_list>
<pin id="35" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="36" class="1001" name="const_36">
<pin_list>
<pin id="37" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="38" class="1001" name="const_38">
<pin_list>
<pin id="39" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="40" class="1001" name="const_40">
<pin_list>
<pin id="41" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_BitConcatenate.i7.i4.i3"/></StgValue>
</bind>
</comp>

<comp id="42" class="1001" name="const_42">
<pin_list>
<pin id="43" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="44" class="1001" name="const_44">
<pin_list>
<pin id="45" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_BitConcatenate.i5.i4.i1"/></StgValue>
</bind>
</comp>

<comp id="46" class="1001" name="const_46">
<pin_list>
<pin id="47" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="48" class="1004" name="C_addr_gep_fu_48">
<pin_list>
<pin id="49" dir="0" index="0" bw="32" slack="0"/>
<pin id="50" dir="0" index="1" bw="1" slack="0"/>
<pin id="51" dir="0" index="2" bw="14" slack="0"/>
<pin id="52" dir="1" index="3" bw="14" slack="0"/>
</pin_list>
<bind>
<opcode="getelementptr(29) " fcode="getelementptr"/>
<opset="C_addr/3 "/>
</bind>
</comp>

<comp id="55" class="1004" name="grp_access_fu_55">
<pin_list>
<pin id="56" dir="0" index="0" bw="14" slack="0"/>
<pin id="57" dir="0" index="1" bw="32" slack="0"/>
<pin id="58" dir="1" index="2" bw="32" slack="1"/>
</pin_list>
<bind>
<opcode="load(27) store(28) " fcode="store"/>
<opset="StgValue_32/3 C_load/6 StgValue_73/8 "/>
</bind>
</comp>

<comp id="61" class="1004" name="A_addr_gep_fu_61">
<pin_list>
<pin id="62" dir="0" index="0" bw="32" slack="0"/>
<pin id="63" dir="0" index="1" bw="1" slack="0"/>
<pin id="64" dir="0" index="2" bw="14" slack="0"/>
<pin id="65" dir="1" index="3" bw="14" slack="0"/>
</pin_list>
<bind>
<opcode="getelementptr(29) " fcode="getelementptr"/>
<opset="A_addr/5 "/>
</bind>
</comp>

<comp id="68" class="1004" name="grp_access_fu_68">
<pin_list>
<pin id="69" dir="0" index="0" bw="14" slack="0"/>
<pin id="70" dir="0" index="1" bw="32" slack="2147483647"/>
<pin id="71" dir="1" index="2" bw="32" slack="1"/>
</pin_list>
<bind>
<opcode="load(27) " fcode="load"/>
<opset="A_load/5 "/>
</bind>
</comp>

<comp id="73" class="1004" name="B_addr_gep_fu_73">
<pin_list>
<pin id="74" dir="0" index="0" bw="32" slack="0"/>
<pin id="75" dir="0" index="1" bw="1" slack="0"/>
<pin id="76" dir="0" index="2" bw="7" slack="0"/>
<pin id="77" dir="1" index="3" bw="7" slack="0"/>
</pin_list>
<bind>
<opcode="getelementptr(29) " fcode="getelementptr"/>
<opset="B_addr/5 "/>
</bind>
</comp>

<comp id="80" class="1004" name="grp_access_fu_80">
<pin_list>
<pin id="81" dir="0" index="0" bw="7" slack="0"/>
<pin id="82" dir="0" index="1" bw="32" slack="2147483647"/>
<pin id="83" dir="1" index="2" bw="32" slack="1"/>
</pin_list>
<bind>
<opcode="load(27) " fcode="load"/>
<opset="B_load/5 "/>
</bind>
</comp>

<comp id="85" class="1005" name="i_reg_85">
<pin_list>
<pin id="86" dir="0" index="0" bw="7" slack="1"/>
<pin id="87" dir="1" index="1" bw="7" slack="1"/>
</pin_list>
<bind>
<opset="i (phireg) "/>
</bind>
</comp>

<comp id="89" class="1004" name="i_phi_fu_89">
<pin_list>
<pin id="90" dir="0" index="0" bw="1" slack="1"/>
<pin id="91" dir="0" index="1" bw="0" slack="2147483647"/>
<pin id="92" dir="0" index="2" bw="7" slack="0"/>
<pin id="93" dir="0" index="3" bw="0" slack="2147483647"/>
<pin id="94" dir="1" index="4" bw="7" slack="0"/>
</pin_list>
<bind>
<opcode="phi(47) " fcode="phi"/>
<opset="i/2 "/>
</bind>
</comp>

<comp id="97" class="1005" name="phi_mul_reg_97">
<pin_list>
<pin id="98" dir="0" index="0" bw="14" slack="1"/>
<pin id="99" dir="1" index="1" bw="14" slack="1"/>
</pin_list>
<bind>
<opset="phi_mul (phireg) "/>
</bind>
</comp>

<comp id="101" class="1004" name="phi_mul_phi_fu_101">
<pin_list>
<pin id="102" dir="0" index="0" bw="1" slack="1"/>
<pin id="103" dir="0" index="1" bw="0" slack="2147483647"/>
<pin id="104" dir="0" index="2" bw="14" slack="0"/>
<pin id="105" dir="0" index="3" bw="0" slack="2147483647"/>
<pin id="106" dir="1" index="4" bw="14" slack="0"/>
</pin_list>
<bind>
<opcode="phi(47) " fcode="phi"/>
<opset="phi_mul/2 "/>
</bind>
</comp>

<comp id="109" class="1005" name="j_reg_109">
<pin_list>
<pin id="110" dir="0" index="0" bw="7" slack="1"/>
<pin id="111" dir="1" index="1" bw="7" slack="1"/>
</pin_list>
<bind>
<opset="j (phireg) "/>
</bind>
</comp>

<comp id="113" class="1004" name="j_phi_fu_113">
<pin_list>
<pin id="114" dir="0" index="0" bw="7" slack="0"/>
<pin id="115" dir="0" index="1" bw="0" slack="2147483647"/>
<pin id="116" dir="0" index="2" bw="1" slack="1"/>
<pin id="117" dir="0" index="3" bw="0" slack="2147483647"/>
<pin id="118" dir="1" index="4" bw="7" slack="0"/>
</pin_list>
<bind>
<opcode="phi(47) " fcode="phi"/>
<opset="j/3 "/>
</bind>
</comp>

<comp id="120" class="1005" name="k_reg_120">
<pin_list>
<pin id="121" dir="0" index="0" bw="4" slack="1"/>
<pin id="122" dir="1" index="1" bw="4" slack="1"/>
</pin_list>
<bind>
<opset="k (phireg) "/>
</bind>
</comp>

<comp id="124" class="1004" name="k_phi_fu_124">
<pin_list>
<pin id="125" dir="0" index="0" bw="1" slack="1"/>
<pin id="126" dir="0" index="1" bw="0" slack="2147483647"/>
<pin id="127" dir="0" index="2" bw="4" slack="0"/>
<pin id="128" dir="0" index="3" bw="0" slack="2147483647"/>
<pin id="129" dir="1" index="4" bw="4" slack="0"/>
</pin_list>
<bind>
<opcode="phi(47) " fcode="phi"/>
<opset="k/4 "/>
</bind>
</comp>

<comp id="131" class="1005" name="l_reg_131">
<pin_list>
<pin id="132" dir="0" index="0" bw="4" slack="1"/>
<pin id="133" dir="1" index="1" bw="4" slack="1"/>
</pin_list>
<bind>
<opset="l (phireg) "/>
</bind>
</comp>

<comp id="135" class="1004" name="l_phi_fu_135">
<pin_list>
<pin id="136" dir="0" index="0" bw="4" slack="0"/>
<pin id="137" dir="0" index="1" bw="0" slack="2147483647"/>
<pin id="138" dir="0" index="2" bw="1" slack="1"/>
<pin id="139" dir="0" index="3" bw="0" slack="2147483647"/>
<pin id="140" dir="1" index="4" bw="4" slack="0"/>
</pin_list>
<bind>
<opcode="phi(47) " fcode="phi"/>
<opset="l/5 "/>
</bind>
</comp>

<comp id="142" class="1004" name="next_mul_fu_142">
<pin_list>
<pin id="143" dir="0" index="0" bw="14" slack="0"/>
<pin id="144" dir="0" index="1" bw="8" slack="0"/>
<pin id="145" dir="1" index="2" bw="14" slack="0"/>
</pin_list>
<bind>
<opcode="add(8) " fcode="add"/>
<opset="next_mul/2 "/>
</bind>
</comp>

<comp id="148" class="1004" name="exitcond3_fu_148">
<pin_list>
<pin id="149" dir="0" index="0" bw="7" slack="0"/>
<pin id="150" dir="0" index="1" bw="7" slack="0"/>
<pin id="151" dir="1" index="2" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<opcode="icmp(45) " fcode="icmp"/>
<opset="exitcond3/2 "/>
</bind>
</comp>

<comp id="154" class="1004" name="i_1_fu_154">
<pin_list>
<pin id="155" dir="0" index="0" bw="7" slack="0"/>
<pin id="156" dir="0" index="1" bw="1" slack="0"/>
<pin id="157" dir="1" index="2" bw="7" slack="0"/>
</pin_list>
<bind>
<opcode="add(8) " fcode="add"/>
<opset="i_1/2 "/>
</bind>
</comp>

<comp id="160" class="1004" name="j_cast5_fu_160">
<pin_list>
<pin id="161" dir="0" index="0" bw="7" slack="0"/>
<pin id="162" dir="1" index="1" bw="14" slack="0"/>
</pin_list>
<bind>
<opcode="zext(34) " fcode="zext"/>
<opset="j_cast5/3 "/>
</bind>
</comp>

<comp id="164" class="1004" name="exitcond2_fu_164">
<pin_list>
<pin id="165" dir="0" index="0" bw="7" slack="0"/>
<pin id="166" dir="0" index="1" bw="7" slack="0"/>
<pin id="167" dir="1" index="2" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<opcode="icmp(45) " fcode="icmp"/>
<opset="exitcond2/3 "/>
</bind>
</comp>

<comp id="170" class="1004" name="j_1_fu_170">
<pin_list>
<pin id="171" dir="0" index="0" bw="7" slack="0"/>
<pin id="172" dir="0" index="1" bw="1" slack="0"/>
<pin id="173" dir="1" index="2" bw="7" slack="0"/>
</pin_list>
<bind>
<opcode="add(8) " fcode="add"/>
<opset="j_1/3 "/>
</bind>
</comp>

<comp id="176" class="1004" name="tmp_2_fu_176">
<pin_list>
<pin id="177" dir="0" index="0" bw="14" slack="1"/>
<pin id="178" dir="0" index="1" bw="7" slack="0"/>
<pin id="179" dir="1" index="2" bw="14" slack="0"/>
</pin_list>
<bind>
<opcode="add(8) " fcode="add"/>
<opset="tmp_2/3 "/>
</bind>
</comp>

<comp id="182" class="1004" name="tmp_3_fu_182">
<pin_list>
<pin id="183" dir="0" index="0" bw="14" slack="0"/>
<pin id="184" dir="1" index="1" bw="64" slack="0"/>
</pin_list>
<bind>
<opcode="zext(34) " fcode="zext"/>
<opset="tmp_3/3 "/>
</bind>
</comp>

<comp id="187" class="1004" name="k_cast4_fu_187">
<pin_list>
<pin id="188" dir="0" index="0" bw="4" slack="0"/>
<pin id="189" dir="1" index="1" bw="7" slack="0"/>
</pin_list>
<bind>
<opcode="zext(34) " fcode="zext"/>
<opset="k_cast4/4 "/>
</bind>
</comp>

<comp id="191" class="1004" name="exitcond1_fu_191">
<pin_list>
<pin id="192" dir="0" index="0" bw="4" slack="0"/>
<pin id="193" dir="0" index="1" bw="4" slack="0"/>
<pin id="194" dir="1" index="2" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<opcode="icmp(45) " fcode="icmp"/>
<opset="exitcond1/4 "/>
</bind>
</comp>

<comp id="197" class="1004" name="k_1_fu_197">
<pin_list>
<pin id="198" dir="0" index="0" bw="4" slack="0"/>
<pin id="199" dir="0" index="1" bw="1" slack="0"/>
<pin id="200" dir="1" index="2" bw="4" slack="0"/>
</pin_list>
<bind>
<opcode="add(8) " fcode="add"/>
<opset="k_1/4 "/>
</bind>
</comp>

<comp id="203" class="1004" name="tmp_5_fu_203">
<pin_list>
<pin id="204" dir="0" index="0" bw="4" slack="0"/>
<pin id="205" dir="0" index="1" bw="7" slack="2"/>
<pin id="206" dir="1" index="2" bw="7" slack="0"/>
</pin_list>
<bind>
<opcode="add(8) " fcode="add"/>
<opset="tmp_5/4 "/>
</bind>
</comp>

<comp id="209" class="1004" name="tmp_5_cast_cast_fu_209">
<pin_list>
<pin id="210" dir="0" index="0" bw="7" slack="0"/>
<pin id="211" dir="1" index="1" bw="14" slack="0"/>
</pin_list>
<bind>
<opcode="zext(34) " fcode="zext"/>
<opset="tmp_5_cast_cast/4 "/>
</bind>
</comp>

<comp id="213" class="1004" name="tmp_6_fu_213">
<pin_list>
<pin id="214" dir="0" index="0" bw="7" slack="0"/>
<pin id="215" dir="0" index="1" bw="8" slack="0"/>
<pin id="216" dir="1" index="2" bw="14" slack="1"/>
</pin_list>
<bind>
<opcode="mul(12) " fcode="mul"/>
<opset="tmp_6/4 "/>
</bind>
</comp>

<comp id="219" class="1004" name="p_shl_fu_219">
<pin_list>
<pin id="220" dir="0" index="0" bw="7" slack="0"/>
<pin id="221" dir="0" index="1" bw="4" slack="0"/>
<pin id="222" dir="0" index="2" bw="1" slack="0"/>
<pin id="223" dir="1" index="3" bw="7" slack="1"/>
</pin_list>
<bind>
<opcode="bitconcatenate(1004) " fcode="bitconcatenate"/>
<opset="p_shl/4 "/>
</bind>
</comp>

<comp id="227" class="1004" name="p_shl8_fu_227">
<pin_list>
<pin id="228" dir="0" index="0" bw="5" slack="0"/>
<pin id="229" dir="0" index="1" bw="4" slack="0"/>
<pin id="230" dir="0" index="2" bw="1" slack="0"/>
<pin id="231" dir="1" index="3" bw="5" slack="1"/>
</pin_list>
<bind>
<opcode="bitconcatenate(1004) " fcode="bitconcatenate"/>
<opset="p_shl8/4 "/>
</bind>
</comp>

<comp id="235" class="1004" name="l_cast3_fu_235">
<pin_list>
<pin id="236" dir="0" index="0" bw="4" slack="0"/>
<pin id="237" dir="1" index="1" bw="14" slack="0"/>
</pin_list>
<bind>
<opcode="zext(34) " fcode="zext"/>
<opset="l_cast3/5 "/>
</bind>
</comp>

<comp id="239" class="1004" name="l_cast_fu_239">
<pin_list>
<pin id="240" dir="0" index="0" bw="4" slack="0"/>
<pin id="241" dir="1" index="1" bw="5" slack="0"/>
</pin_list>
<bind>
<opcode="zext(34) " fcode="zext"/>
<opset="l_cast/5 "/>
</bind>
</comp>

<comp id="243" class="1004" name="exitcond_fu_243">
<pin_list>
<pin id="244" dir="0" index="0" bw="4" slack="0"/>
<pin id="245" dir="0" index="1" bw="4" slack="0"/>
<pin id="246" dir="1" index="2" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<opcode="icmp(45) " fcode="icmp"/>
<opset="exitcond/5 "/>
</bind>
</comp>

<comp id="249" class="1004" name="l_1_fu_249">
<pin_list>
<pin id="250" dir="0" index="0" bw="4" slack="0"/>
<pin id="251" dir="0" index="1" bw="1" slack="0"/>
<pin id="252" dir="1" index="2" bw="4" slack="0"/>
</pin_list>
<bind>
<opcode="add(8) " fcode="add"/>
<opset="l_1/5 "/>
</bind>
</comp>

<comp id="255" class="1004" name="tmp1_fu_255">
<pin_list>
<pin id="256" dir="0" index="0" bw="14" slack="1"/>
<pin id="257" dir="0" index="1" bw="4" slack="0"/>
<pin id="258" dir="1" index="2" bw="14" slack="0"/>
</pin_list>
<bind>
<opcode="add(8) " fcode="add"/>
<opset="tmp1/5 "/>
</bind>
</comp>

<comp id="260" class="1004" name="tmp_s_fu_260">
<pin_list>
<pin id="261" dir="0" index="0" bw="14" slack="0"/>
<pin id="262" dir="0" index="1" bw="7" slack="2"/>
<pin id="263" dir="1" index="2" bw="14" slack="0"/>
</pin_list>
<bind>
<opcode="add(8) " fcode="add"/>
<opset="tmp_s/5 "/>
</bind>
</comp>

<comp id="265" class="1004" name="tmp_1_fu_265">
<pin_list>
<pin id="266" dir="0" index="0" bw="14" slack="0"/>
<pin id="267" dir="1" index="1" bw="64" slack="0"/>
</pin_list>
<bind>
<opcode="zext(34) " fcode="zext"/>
<opset="tmp_1/5 "/>
</bind>
</comp>

<comp id="270" class="1004" name="tmp2_fu_270">
<pin_list>
<pin id="271" dir="0" index="0" bw="5" slack="1"/>
<pin id="272" dir="0" index="1" bw="4" slack="0"/>
<pin id="273" dir="1" index="2" bw="5" slack="0"/>
</pin_list>
<bind>
<opcode="add(8) " fcode="add"/>
<opset="tmp2/5 "/>
</bind>
</comp>

<comp id="275" class="1004" name="tmp2_cast_fu_275">
<pin_list>
<pin id="276" dir="0" index="0" bw="5" slack="0"/>
<pin id="277" dir="1" index="1" bw="7" slack="0"/>
</pin_list>
<bind>
<opcode="zext(34) " fcode="zext"/>
<opset="tmp2_cast/5 "/>
</bind>
</comp>

<comp id="279" class="1004" name="tmp_4_fu_279">
<pin_list>
<pin id="280" dir="0" index="0" bw="5" slack="0"/>
<pin id="281" dir="0" index="1" bw="7" slack="1"/>
<pin id="282" dir="1" index="2" bw="7" slack="0"/>
</pin_list>
<bind>
<opcode="add(8) " fcode="add"/>
<opset="tmp_4/5 "/>
</bind>
</comp>

<comp id="284" class="1004" name="tmp_8_fu_284">
<pin_list>
<pin id="285" dir="0" index="0" bw="7" slack="0"/>
<pin id="286" dir="1" index="1" bw="64" slack="0"/>
</pin_list>
<bind>
<opcode="zext(34) " fcode="zext"/>
<opset="tmp_8/5 "/>
</bind>
</comp>

<comp id="289" class="1004" name="tmp_7_fu_289">
<pin_list>
<pin id="290" dir="0" index="0" bw="32" slack="1"/>
<pin id="291" dir="0" index="1" bw="32" slack="1"/>
<pin id="292" dir="1" index="2" bw="32" slack="1"/>
</pin_list>
<bind>
<opcode="mul(12) " fcode="mul"/>
<opset="tmp_7/7 "/>
</bind>
</comp>

<comp id="293" class="1004" name="tmp_9_fu_293">
<pin_list>
<pin id="294" dir="0" index="0" bw="32" slack="1"/>
<pin id="295" dir="0" index="1" bw="32" slack="1"/>
<pin id="296" dir="1" index="2" bw="32" slack="0"/>
</pin_list>
<bind>
<opcode="add(8) " fcode="add"/>
<opset="tmp_9/8 "/>
</bind>
</comp>

<comp id="298" class="1005" name="next_mul_reg_298">
<pin_list>
<pin id="299" dir="0" index="0" bw="14" slack="0"/>
<pin id="300" dir="1" index="1" bw="14" slack="0"/>
</pin_list>
<bind>
<opset="next_mul "/>
</bind>
</comp>

<comp id="306" class="1005" name="i_1_reg_306">
<pin_list>
<pin id="307" dir="0" index="0" bw="7" slack="0"/>
<pin id="308" dir="1" index="1" bw="7" slack="0"/>
</pin_list>
<bind>
<opset="i_1 "/>
</bind>
</comp>

<comp id="311" class="1005" name="j_cast5_reg_311">
<pin_list>
<pin id="312" dir="0" index="0" bw="14" slack="2"/>
<pin id="313" dir="1" index="1" bw="14" slack="2"/>
</pin_list>
<bind>
<opset="j_cast5 "/>
</bind>
</comp>

<comp id="319" class="1005" name="j_1_reg_319">
<pin_list>
<pin id="320" dir="0" index="0" bw="7" slack="0"/>
<pin id="321" dir="1" index="1" bw="7" slack="0"/>
</pin_list>
<bind>
<opset="j_1 "/>
</bind>
</comp>

<comp id="324" class="1005" name="C_addr_reg_324">
<pin_list>
<pin id="325" dir="0" index="0" bw="14" slack="3"/>
<pin id="326" dir="1" index="1" bw="14" slack="3"/>
</pin_list>
<bind>
<opset="C_addr "/>
</bind>
</comp>

<comp id="332" class="1005" name="k_1_reg_332">
<pin_list>
<pin id="333" dir="0" index="0" bw="4" slack="0"/>
<pin id="334" dir="1" index="1" bw="4" slack="0"/>
</pin_list>
<bind>
<opset="k_1 "/>
</bind>
</comp>

<comp id="337" class="1005" name="tmp_6_reg_337">
<pin_list>
<pin id="338" dir="0" index="0" bw="14" slack="1"/>
<pin id="339" dir="1" index="1" bw="14" slack="1"/>
</pin_list>
<bind>
<opset="tmp_6 "/>
</bind>
</comp>

<comp id="342" class="1005" name="p_shl_reg_342">
<pin_list>
<pin id="343" dir="0" index="0" bw="7" slack="1"/>
<pin id="344" dir="1" index="1" bw="7" slack="1"/>
</pin_list>
<bind>
<opset="p_shl "/>
</bind>
</comp>

<comp id="347" class="1005" name="p_shl8_reg_347">
<pin_list>
<pin id="348" dir="0" index="0" bw="5" slack="1"/>
<pin id="349" dir="1" index="1" bw="5" slack="1"/>
</pin_list>
<bind>
<opset="p_shl8 "/>
</bind>
</comp>

<comp id="355" class="1005" name="l_1_reg_355">
<pin_list>
<pin id="356" dir="0" index="0" bw="4" slack="0"/>
<pin id="357" dir="1" index="1" bw="4" slack="0"/>
</pin_list>
<bind>
<opset="l_1 "/>
</bind>
</comp>

<comp id="360" class="1005" name="A_addr_reg_360">
<pin_list>
<pin id="361" dir="0" index="0" bw="14" slack="1"/>
<pin id="362" dir="1" index="1" bw="14" slack="1"/>
</pin_list>
<bind>
<opset="A_addr "/>
</bind>
</comp>

<comp id="365" class="1005" name="B_addr_reg_365">
<pin_list>
<pin id="366" dir="0" index="0" bw="7" slack="1"/>
<pin id="367" dir="1" index="1" bw="7" slack="1"/>
</pin_list>
<bind>
<opset="B_addr "/>
</bind>
</comp>

<comp id="370" class="1005" name="A_load_reg_370">
<pin_list>
<pin id="371" dir="0" index="0" bw="32" slack="1"/>
<pin id="372" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="A_load "/>
</bind>
</comp>

<comp id="375" class="1005" name="B_load_reg_375">
<pin_list>
<pin id="376" dir="0" index="0" bw="32" slack="1"/>
<pin id="377" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="B_load "/>
</bind>
</comp>

<comp id="380" class="1005" name="tmp_7_reg_380">
<pin_list>
<pin id="381" dir="0" index="0" bw="32" slack="1"/>
<pin id="382" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="tmp_7 "/>
</bind>
</comp>

<comp id="385" class="1005" name="C_load_reg_385">
<pin_list>
<pin id="386" dir="0" index="0" bw="32" slack="1"/>
<pin id="387" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="C_load "/>
</bind>
</comp>

</comp_list>

<net_list>
<net id="53"><net_src comp="4" pin="0"/><net_sink comp="48" pin=0"/></net>

<net id="54"><net_src comp="26" pin="0"/><net_sink comp="48" pin=1"/></net>

<net id="59"><net_src comp="28" pin="0"/><net_sink comp="55" pin=1"/></net>

<net id="60"><net_src comp="48" pin="3"/><net_sink comp="55" pin=0"/></net>

<net id="66"><net_src comp="0" pin="0"/><net_sink comp="61" pin=0"/></net>

<net id="67"><net_src comp="26" pin="0"/><net_sink comp="61" pin=1"/></net>

<net id="72"><net_src comp="61" pin="3"/><net_sink comp="68" pin=0"/></net>

<net id="78"><net_src comp="2" pin="0"/><net_sink comp="73" pin=0"/></net>

<net id="79"><net_src comp="26" pin="0"/><net_sink comp="73" pin=1"/></net>

<net id="84"><net_src comp="73" pin="3"/><net_sink comp="80" pin=0"/></net>

<net id="88"><net_src comp="12" pin="0"/><net_sink comp="85" pin=0"/></net>

<net id="95"><net_src comp="85" pin="1"/><net_sink comp="89" pin=0"/></net>

<net id="96"><net_src comp="89" pin="4"/><net_sink comp="85" pin=0"/></net>

<net id="100"><net_src comp="14" pin="0"/><net_sink comp="97" pin=0"/></net>

<net id="107"><net_src comp="97" pin="1"/><net_sink comp="101" pin=0"/></net>

<net id="108"><net_src comp="101" pin="4"/><net_sink comp="97" pin=0"/></net>

<net id="112"><net_src comp="12" pin="0"/><net_sink comp="109" pin=0"/></net>

<net id="119"><net_src comp="109" pin="1"/><net_sink comp="113" pin=2"/></net>

<net id="123"><net_src comp="30" pin="0"/><net_sink comp="120" pin=0"/></net>

<net id="130"><net_src comp="120" pin="1"/><net_sink comp="124" pin=0"/></net>

<net id="134"><net_src comp="30" pin="0"/><net_sink comp="131" pin=0"/></net>

<net id="141"><net_src comp="131" pin="1"/><net_sink comp="135" pin=2"/></net>

<net id="146"><net_src comp="101" pin="4"/><net_sink comp="142" pin=0"/></net>

<net id="147"><net_src comp="16" pin="0"/><net_sink comp="142" pin=1"/></net>

<net id="152"><net_src comp="89" pin="4"/><net_sink comp="148" pin=0"/></net>

<net id="153"><net_src comp="18" pin="0"/><net_sink comp="148" pin=1"/></net>

<net id="158"><net_src comp="89" pin="4"/><net_sink comp="154" pin=0"/></net>

<net id="159"><net_src comp="24" pin="0"/><net_sink comp="154" pin=1"/></net>

<net id="163"><net_src comp="113" pin="4"/><net_sink comp="160" pin=0"/></net>

<net id="168"><net_src comp="113" pin="4"/><net_sink comp="164" pin=0"/></net>

<net id="169"><net_src comp="18" pin="0"/><net_sink comp="164" pin=1"/></net>

<net id="174"><net_src comp="113" pin="4"/><net_sink comp="170" pin=0"/></net>

<net id="175"><net_src comp="24" pin="0"/><net_sink comp="170" pin=1"/></net>

<net id="180"><net_src comp="97" pin="1"/><net_sink comp="176" pin=0"/></net>

<net id="181"><net_src comp="160" pin="1"/><net_sink comp="176" pin=1"/></net>

<net id="185"><net_src comp="176" pin="2"/><net_sink comp="182" pin=0"/></net>

<net id="186"><net_src comp="182" pin="1"/><net_sink comp="48" pin=2"/></net>

<net id="190"><net_src comp="124" pin="4"/><net_sink comp="187" pin=0"/></net>

<net id="195"><net_src comp="124" pin="4"/><net_sink comp="191" pin=0"/></net>

<net id="196"><net_src comp="32" pin="0"/><net_sink comp="191" pin=1"/></net>

<net id="201"><net_src comp="124" pin="4"/><net_sink comp="197" pin=0"/></net>

<net id="202"><net_src comp="36" pin="0"/><net_sink comp="197" pin=1"/></net>

<net id="207"><net_src comp="187" pin="1"/><net_sink comp="203" pin=0"/></net>

<net id="208"><net_src comp="85" pin="1"/><net_sink comp="203" pin=1"/></net>

<net id="212"><net_src comp="203" pin="2"/><net_sink comp="209" pin=0"/></net>

<net id="217"><net_src comp="209" pin="1"/><net_sink comp="213" pin=0"/></net>

<net id="218"><net_src comp="38" pin="0"/><net_sink comp="213" pin=1"/></net>

<net id="224"><net_src comp="40" pin="0"/><net_sink comp="219" pin=0"/></net>

<net id="225"><net_src comp="124" pin="4"/><net_sink comp="219" pin=1"/></net>

<net id="226"><net_src comp="42" pin="0"/><net_sink comp="219" pin=2"/></net>

<net id="232"><net_src comp="44" pin="0"/><net_sink comp="227" pin=0"/></net>

<net id="233"><net_src comp="124" pin="4"/><net_sink comp="227" pin=1"/></net>

<net id="234"><net_src comp="46" pin="0"/><net_sink comp="227" pin=2"/></net>

<net id="238"><net_src comp="135" pin="4"/><net_sink comp="235" pin=0"/></net>

<net id="242"><net_src comp="135" pin="4"/><net_sink comp="239" pin=0"/></net>

<net id="247"><net_src comp="135" pin="4"/><net_sink comp="243" pin=0"/></net>

<net id="248"><net_src comp="32" pin="0"/><net_sink comp="243" pin=1"/></net>

<net id="253"><net_src comp="135" pin="4"/><net_sink comp="249" pin=0"/></net>

<net id="254"><net_src comp="36" pin="0"/><net_sink comp="249" pin=1"/></net>

<net id="259"><net_src comp="235" pin="1"/><net_sink comp="255" pin=1"/></net>

<net id="264"><net_src comp="255" pin="2"/><net_sink comp="260" pin=0"/></net>

<net id="268"><net_src comp="260" pin="2"/><net_sink comp="265" pin=0"/></net>

<net id="269"><net_src comp="265" pin="1"/><net_sink comp="61" pin=2"/></net>

<net id="274"><net_src comp="239" pin="1"/><net_sink comp="270" pin=1"/></net>

<net id="278"><net_src comp="270" pin="2"/><net_sink comp="275" pin=0"/></net>

<net id="283"><net_src comp="275" pin="1"/><net_sink comp="279" pin=0"/></net>

<net id="287"><net_src comp="279" pin="2"/><net_sink comp="284" pin=0"/></net>

<net id="288"><net_src comp="284" pin="1"/><net_sink comp="73" pin=2"/></net>

<net id="297"><net_src comp="293" pin="2"/><net_sink comp="55" pin=1"/></net>

<net id="301"><net_src comp="142" pin="2"/><net_sink comp="298" pin=0"/></net>

<net id="302"><net_src comp="298" pin="1"/><net_sink comp="101" pin=2"/></net>

<net id="309"><net_src comp="154" pin="2"/><net_sink comp="306" pin=0"/></net>

<net id="310"><net_src comp="306" pin="1"/><net_sink comp="89" pin=2"/></net>

<net id="314"><net_src comp="160" pin="1"/><net_sink comp="311" pin=0"/></net>

<net id="315"><net_src comp="311" pin="1"/><net_sink comp="260" pin=1"/></net>

<net id="322"><net_src comp="170" pin="2"/><net_sink comp="319" pin=0"/></net>

<net id="323"><net_src comp="319" pin="1"/><net_sink comp="113" pin=0"/></net>

<net id="327"><net_src comp="48" pin="3"/><net_sink comp="324" pin=0"/></net>

<net id="328"><net_src comp="324" pin="1"/><net_sink comp="55" pin=0"/></net>

<net id="335"><net_src comp="197" pin="2"/><net_sink comp="332" pin=0"/></net>

<net id="336"><net_src comp="332" pin="1"/><net_sink comp="124" pin=2"/></net>

<net id="340"><net_src comp="213" pin="2"/><net_sink comp="337" pin=0"/></net>

<net id="341"><net_src comp="337" pin="1"/><net_sink comp="255" pin=0"/></net>

<net id="345"><net_src comp="219" pin="3"/><net_sink comp="342" pin=0"/></net>

<net id="346"><net_src comp="342" pin="1"/><net_sink comp="279" pin=1"/></net>

<net id="350"><net_src comp="227" pin="3"/><net_sink comp="347" pin=0"/></net>

<net id="351"><net_src comp="347" pin="1"/><net_sink comp="270" pin=0"/></net>

<net id="358"><net_src comp="249" pin="2"/><net_sink comp="355" pin=0"/></net>

<net id="359"><net_src comp="355" pin="1"/><net_sink comp="135" pin=0"/></net>

<net id="363"><net_src comp="61" pin="3"/><net_sink comp="360" pin=0"/></net>

<net id="364"><net_src comp="360" pin="1"/><net_sink comp="68" pin=0"/></net>

<net id="368"><net_src comp="73" pin="3"/><net_sink comp="365" pin=0"/></net>

<net id="369"><net_src comp="365" pin="1"/><net_sink comp="80" pin=0"/></net>

<net id="373"><net_src comp="68" pin="2"/><net_sink comp="370" pin=0"/></net>

<net id="374"><net_src comp="370" pin="1"/><net_sink comp="289" pin=0"/></net>

<net id="378"><net_src comp="80" pin="2"/><net_sink comp="375" pin=0"/></net>

<net id="379"><net_src comp="375" pin="1"/><net_sink comp="289" pin=1"/></net>

<net id="383"><net_src comp="289" pin="2"/><net_sink comp="380" pin=0"/></net>

<net id="384"><net_src comp="380" pin="1"/><net_sink comp="293" pin=1"/></net>

<net id="388"><net_src comp="55" pin="2"/><net_sink comp="385" pin=0"/></net>

<net id="389"><net_src comp="385" pin="1"/><net_sink comp="293" pin=0"/></net>

</net_list>

</model> 
---------------- Datapath Model END ------------------

* FSMD analyzer results:
  - Output states:
	Port: C | {3 8 }
 - Input state : 
	Port: convolution : A | {5 6 }
	Port: convolution : B | {5 6 }
	Port: convolution : C | {6 7 }
  - Chain level:
	State 1
	State 2
		next_mul : 1
		exitcond3 : 1
		i_1 : 1
		StgValue_20 : 2
	State 3
		j_cast5 : 1
		exitcond2 : 1
		j_1 : 1
		StgValue_28 : 2
		tmp_2 : 2
		tmp_3 : 3
		C_addr : 4
		StgValue_32 : 5
	State 4
		k_cast4 : 1
		exitcond1 : 1
		k_1 : 1
		StgValue_40 : 2
		tmp_5 : 2
		tmp_5_cast_cast : 3
		tmp_6 : 4
		p_shl : 1
		p_shl8 : 1
	State 5
		l_cast3 : 1
		l_cast : 1
		exitcond : 1
		l_1 : 1
		StgValue_54 : 2
		tmp1 : 2
		tmp_s : 3
		tmp_1 : 4
		A_addr : 5
		A_load : 6
		tmp2 : 2
		tmp2_cast : 3
		tmp_4 : 4
		tmp_8 : 5
		B_addr : 6
		B_load : 7
	State 6
	State 7
	State 8
		StgValue_73 : 1


============================================================
+ Verbose Summary: Datapath Resource usage 
============================================================

* Functional unit list:
|----------|------------------------|---------|---------|---------|
| Operation|     Functional Unit    |  DSP48E |    FF   |   LUT   |
|----------|------------------------|---------|---------|---------|
|          |     next_mul_fu_142    |    0    |    0    |    21   |
|          |       i_1_fu_154       |    0    |    0    |    15   |
|          |       j_1_fu_170       |    0    |    0    |    15   |
|          |      tmp_2_fu_176      |    0    |    0    |    21   |
|          |       k_1_fu_197       |    0    |    0    |    13   |
|    add   |      tmp_5_fu_203      |    0    |    0    |    15   |
|          |       l_1_fu_249       |    0    |    0    |    13   |
|          |       tmp1_fu_255      |    0    |    0    |    14   |
|          |      tmp_s_fu_260      |    0    |    0    |    14   |
|          |       tmp2_fu_270      |    0    |    0    |    15   |
|          |      tmp_4_fu_279      |    0    |    0    |    15   |
|          |      tmp_9_fu_293      |    0    |    0    |    39   |
|----------|------------------------|---------|---------|---------|
|    mul   |      tmp_6_fu_213      |    0    |    0    |    41   |
|          |      tmp_7_fu_289      |    3    |    0    |    20   |
|----------|------------------------|---------|---------|---------|
|          |    exitcond3_fu_148    |    0    |    0    |    11   |
|   icmp   |    exitcond2_fu_164    |    0    |    0    |    11   |
|          |    exitcond1_fu_191    |    0    |    0    |    9    |
|          |     exitcond_fu_243    |    0    |    0    |    9    |
|----------|------------------------|---------|---------|---------|
|          |     j_cast5_fu_160     |    0    |    0    |    0    |
|          |      tmp_3_fu_182      |    0    |    0    |    0    |
|          |     k_cast4_fu_187     |    0    |    0    |    0    |
|          | tmp_5_cast_cast_fu_209 |    0    |    0    |    0    |
|   zext   |     l_cast3_fu_235     |    0    |    0    |    0    |
|          |      l_cast_fu_239     |    0    |    0    |    0    |
|          |      tmp_1_fu_265      |    0    |    0    |    0    |
|          |    tmp2_cast_fu_275    |    0    |    0    |    0    |
|          |      tmp_8_fu_284      |    0    |    0    |    0    |
|----------|------------------------|---------|---------|---------|
|bitconcatenate|      p_shl_fu_219      |    0    |    0    |    0    |
|          |      p_shl8_fu_227     |    0    |    0    |    0    |
|----------|------------------------|---------|---------|---------|
|   Total  |                        |    3    |    0    |   311   |
|----------|------------------------|---------|---------|---------|

Memories:
N/A

* Register list:
+----------------+--------+
|                |   FF   |
+----------------+--------+
| A_addr_reg_360 |   14   |
| A_load_reg_370 |   32   |
| B_addr_reg_365 |    7   |
| B_load_reg_375 |   32   |
| C_addr_reg_324 |   14   |
| C_load_reg_385 |   32   |
|   i_1_reg_306  |    7   |
|    i_reg_85    |    7   |
|   j_1_reg_319  |    7   |
| j_cast5_reg_311|   14   |
|    j_reg_109   |    7   |
|   k_1_reg_332  |    4   |
|    k_reg_120   |    4   |
|   l_1_reg_355  |    4   |
|    l_reg_131   |    4   |
|next_mul_reg_298|   14   |
| p_shl8_reg_347 |    5   |
|  p_shl_reg_342 |    7   |
| phi_mul_reg_97 |   14   |
|  tmp_6_reg_337 |   14   |
|  tmp_7_reg_380 |   32   |
+----------------+--------+
|      Total     |   275  |
+----------------+--------+

* Multiplexer (MUX) list: 
|------------------|------|------|------|--------||---------||---------|
|       Comp       |  Pin | Size |  BW  | S x BW ||  Delay  ||   LUT   |
|------------------|------|------|------|--------||---------||---------|
| grp_access_fu_55 |  p0  |   2  |  14  |   28   ||    9    |
| grp_access_fu_55 |  p1  |   2  |  32  |   64   ||    9    |
| grp_access_fu_68 |  p0  |   2  |  14  |   28   ||    9    |
| grp_access_fu_80 |  p0  |   2  |   7  |   14   ||    9    |
|     i_reg_85     |  p0  |   2  |   7  |   14   ||    9    |
|  phi_mul_reg_97  |  p0  |   2  |  14  |   28   ||    9    |
|------------------|------|------|------|--------||---------||---------|
|       Total      |      |      |      |   176  ||  10.614 ||    54   |
|------------------|------|------|------|--------||---------||---------|



* Summary:
+-----------+--------+--------+--------+--------+
|           | DSP48E |  Delay |   FF   |   LUT  |
+-----------+--------+--------+--------+--------+
|  Function |    3   |    -   |    0   |   311  |
|   Memory  |    -   |    -   |    -   |    -   |
|Multiplexer|    -   |   10   |    -   |   54   |
|  Register |    -   |    -   |   275  |    -   |
+-----------+--------+--------+--------+--------+
|   Total   |    3   |   10   |   275  |   365  |
+-----------+--------+--------+--------+--------+