Folder Path

/MSc/HLS-FPGA/edge_detection/solution0/syn/vhdl/

0 directories 16 files 541 KiB total
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Name
Size Modified
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conv_stream.vhd
63 KiB
conv_stream_ap_fadd_3_full_dsp_32_ip.tcl
2.4 KiB
conv_stream_ap_fmul_2_max_dsp_32_ip.tcl
2.4 KiB
conv_stream_AXILiteS_s_axi.vhd
14 KiB
conv_stream_fadd_dEe.vhd
3.5 KiB
conv_stream_fmul_eOg.vhd
3.5 KiB
conv_stream_in_array_m_axi.vhd
123 KiB
conv_stream_out_array_m_axi.vhd
123 KiB
convolve.vhd
129 KiB
convolve_temp_arrbkb.vhd
3.4 KiB
fifo_w32_d2_A.vhd
4.3 KiB
fifo_w32_d32_A.vhd
4.3 KiB
read_pixel13.vhd
28 KiB
start_for_convolvfYi.vhd
4.4 KiB
start_for_write_pg8j.vhd
4.4 KiB
write_pixel.vhd
28 KiB