Folder Path

/MSc/HLS-FPGA/edge_detection/solution0/sim/vhdl/xsim.dir/xil_defaultlib/

0 directories 41 files 2.2 MiB total
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Name
Size Modified
Up
aesl_axi_master_in_array.vdb
168 KiB
aesl_axi_master_out_array.vdb
187 KiB
aesl_axi_slave_axilites.vdb
119 KiB
aesl_sim_components.vdb
29 KiB
apatb_conv_stream_top.vdb
192 KiB
conv_stream.vdb
198 KiB
conv_stream_ap_fadd_3_full_dsp_32.vdb
30 KiB
conv_stream_ap_fmul_2_max_dsp_32.vdb
30 KiB
conv_stream_axilites_s_axi.vdb
36 KiB
conv_stream_fadd_dee.vdb
9.5 KiB
conv_stream_fmul_eog.vdb
9.5 KiB
conv_stream_in_array_m_axi.vdb
62 KiB
conv_stream_in_array_m_axi_buffer.vdb
19 KiB
conv_stream_in_array_m_axi_decoder.vdb
2.7 KiB
conv_stream_in_array_m_axi_fifo.vdb
13 KiB
conv_stream_in_array_m_axi_read.vdb
100 KiB
conv_stream_in_array_m_axi_reg_slice.vdb
11 KiB
conv_stream_in_array_m_axi_throttl.vdb
7.7 KiB
conv_stream_in_array_m_axi_write.vdb
123 KiB
conv_stream_out_array_m_axi.vdb
62 KiB
conv_stream_out_array_m_axi_buffer.vdb
19 KiB
conv_stream_out_array_m_axi_decoder.vdb
2.7 KiB
conv_stream_out_array_m_axi_fifo.vdb
13 KiB
conv_stream_out_array_m_axi_read.vdb
100 KiB
conv_stream_out_array_m_axi_reg_slice.vdb
11 KiB
conv_stream_out_array_m_axi_throttl.vdb
7.7 KiB
conv_stream_out_array_m_axi_write.vdb
123 KiB
convolve.vdb
332 KiB
convolve_temp_arrbkb.vdb
4.8 KiB
convolve_temp_arrbkb_ram.vdb
7.0 KiB
fifo_w32_d2_a.vdb
11 KiB
fifo_w32_d2_a_shiftreg.vdb
4.5 KiB
fifo_w32_d32_a.vdb
11 KiB
fifo_w32_d32_a_shiftreg.vdb
4.6 KiB
read_pixel13.vdb
76 KiB
start_for_convolvfyi.vdb
11 KiB
start_for_convolvfyi_shiftreg.vdb
4.6 KiB
start_for_write_pg8j.vdb
11 KiB
start_for_write_pg8j_shiftreg.vdb
4.6 KiB
write_pixel.vdb
75 KiB
xil_defaultlib.rlx
8.2 KiB