Folder Path

/MSc/HLS-FPGA/edge_detection/solution0/sim/vhdl/

3 directories 40 files 1.5 MiB total
List Grid
Name
Size Modified
Up
.Xil/ —
ip/ —
xsim.dir/ —
.run_sim.tcl
9.8 KiB
.sim.status.tcl
1.3 KiB
AESL_axi_master_in_array.vhd
56 KiB
AESL_axi_master_out_array.vhd
62 KiB
AESL_axi_slave_AXILiteS.vhd
41 KiB
AESL_sim_pkg.vhd
8.5 KiB
check_sim.tcl
4.1 KiB
conv_stream.autotb.vhd
62 KiB
conv_stream.performance.result.transaction.xml
105 B
conv_stream.prj
1.0 KiB
conv_stream.result.lat.rb
131 B
conv_stream.tcl
14 KiB
conv_stream.vhd
63 KiB
conv_stream.wcfg
49 KiB
conv_stream.wdb
558 KiB
conv_stream_AXILiteS_s_axi.vhd
14 KiB
conv_stream_fadd_dEe.vhd
3.5 KiB
conv_stream_fmul_eOg.vhd
3.5 KiB
conv_stream_in_array_m_axi.vhd
123 KiB
conv_stream_out_array_m_axi.vhd
123 KiB
convolve.vhd
129 KiB
convolve_temp_arrbkb.vhd
3.4 KiB
fifo_w32_d2_A.vhd
4.3 KiB
fifo_w32_d32_A.vhd
4.3 KiB
glbl.v
1.4 KiB
read_pixel13.vhd
28 KiB
run_sim.tcl
2.5 KiB
run_xsim.sh
501 B
sim.sh
413 B
start_for_convolvfYi.vhd
4.4 KiB
start_for_write_pg8j.vhd
4.4 KiB
webtalk.jou
830 B
webtalk.log
1.2 KiB
webtalk_3941.backup.jou
830 B
webtalk_3941.backup.log
1.2 KiB
write_pixel.vhd
28 KiB
xelab.log
33 KiB
xelab.pb
52 KiB
xsim.jou
695 B
xsim.log
19 KiB