Folder Path
/
MSc
/
HLS-FPGA
/
edge_detection
/
solution0
/
impl
/
vhdl
/
sim_tbs
/
2
directories
4
files
224 KiB
total
List
Grid
Name
Size
Modified
Up
cdatafile/
—
05/17/2022 08:16:26 PM +00:00
rtldatafile/
—
05/17/2022 08:16:26 PM +00:00
AESL_axi_master_in_array.vhd
56 KiB
05/17/2022 08:16:26 PM +00:00
AESL_axi_master_out_array.vhd
62 KiB
05/17/2022 08:16:26 PM +00:00
AESL_axi_slave_AXILiteS.vhd
41 KiB
05/17/2022 08:16:26 PM +00:00
conv_stream.autotb.vhd
65 KiB
05/17/2022 08:16:26 PM +00:00