Folder Path

/MSc/HLS-FPGA/edge_detection/solution0/impl/vhdl/

6 directories 22 files 619 KiB total
List Grid
Name
Size Modified
Up
.Xil/ —
project.cache/ —
project.hw/ —
project.ip_user_files/ —
project.srcs/ —
sim_tbs/ —
conv_stream.vhd
63 KiB
conv_stream.xdc
176 B
conv_stream_ap_fadd_3_full_dsp_32_ip.tcl
2.4 KiB
conv_stream_ap_fmul_2_max_dsp_32_ip.tcl
2.4 KiB
conv_stream_AXILiteS_s_axi.vhd
14 KiB
conv_stream_fadd_dEe.vhd
3.5 KiB
conv_stream_fmul_eOg.vhd
3.5 KiB
conv_stream_in_array_m_axi.vhd
123 KiB
conv_stream_out_array_m_axi.vhd
123 KiB
convolve.vhd
129 KiB
convolve_temp_arrbkb.vhd
3.4 KiB
extraction.tcl
62 KiB
fifo_w32_d2_A.vhd
4.3 KiB
fifo_w32_d32_A.vhd
4.3 KiB
impl.sh
399 B
project.xpr
12 KiB
read_pixel13.vhd
28 KiB
run_vivado.tcl
2.3 KiB
settings.tcl
569 B
start_for_convolvfYi.vhd
4.4 KiB
start_for_write_pg8j.vhd
4.4 KiB
write_pixel.vhd
28 KiB