Folder Path

/MSc/HLS-FPGA/edge_detection/solution0/impl/verilog/

5 directories 22 files 434 KiB total
List Grid
Name
Size Modified
Up
.Xil/ —
project.cache/ —
project.hw/ —
project.ip_user_files/ —
project.srcs/ —
conv_stream.v
36 KiB
conv_stream.xdc
176 B
conv_stream_ap_fadd_3_full_dsp_32_ip.tcl
2.4 KiB
conv_stream_ap_fmul_2_max_dsp_32_ip.tcl
2.4 KiB
conv_stream_AXILiteS_s_axi.v
11 KiB
conv_stream_fadd_dEe.v
2.1 KiB
conv_stream_fmul_eOg.v
2.1 KiB
conv_stream_in_array_m_axi.v
83 KiB
conv_stream_out_array_m_axi.v
83 KiB
convolve.v
88 KiB
convolve_temp_arrbkb.v
1.5 KiB
extraction.tcl
62 KiB
fifo_w32_d2_A.v
2.9 KiB
fifo_w32_d32_A.v
2.9 KiB
impl.sh
399 B
project.xpr
10 KiB
read_pixel13.v
18 KiB
run_vivado.tcl
2.1 KiB
settings.tcl
572 B
start_for_convolvfYi.v
2.9 KiB
start_for_write_pg8j.v
2.9 KiB
write_pixel.v
18 KiB