Folder Path

/MSc/HLS-FPGA/edge_detection/solution0/impl/ip/

15 directories 10 files 449 KiB total

	Name	Size	Modified
	Up
	.cache/	—	05/17/2022 08:14:53 PM +00:00
	.Xil/	—	05/17/2022 08:14:53 PM +00:00
	bd/	—	05/17/2022 08:14:53 PM +00:00
	constraints/	—	05/17/2022 08:16:18 PM +00:00
	doc/	—	05/17/2022 08:16:18 PM +00:00
	drivers/	—	05/17/2022 08:16:18 PM +00:00
	example/	—	05/17/2022 08:16:18 PM +00:00
	hdl/	—	05/17/2022 08:16:18 PM +00:00
	misc/	—	05/17/2022 08:16:18 PM +00:00
	subcore/	—	05/17/2022 08:16:19 PM +00:00
	tmp.cache/	—	05/17/2022 08:16:19 PM +00:00
	tmp.hw/	—	05/17/2022 08:16:19 PM +00:00
	tmp.ip_user_files/	—	05/17/2022 08:14:55 PM +00:00
	tmp.srcs/	—	05/17/2022 08:16:19 PM +00:00
	xgui/	—	05/17/2022 08:16:19 PM +00:00
	autoimpl.log	1.5 KiB	05/17/2022 08:16:18 PM +00:00
	auxiliary.xml	1.5 KiB	05/17/2022 08:16:18 PM +00:00
	component.xml	207 KiB	05/17/2022 08:16:18 PM +00:00
	conv_stream_info.xml	1.0 KiB	05/17/2022 08:16:18 PM +00:00
	pack.sh	377 B	05/17/2022 08:16:18 PM +00:00
	run_ippack.tcl	77 KiB	05/17/2022 08:16:18 PM +00:00
	tmp.xpr	6.7 KiB	05/17/2022 08:16:18 PM +00:00
	vivado.jou	651 B	05/17/2022 08:16:17 PM +00:00
	vivado.log	1.9 KiB	05/17/2022 08:16:17 PM +00:00
	xilinx_com_hls_conv_stream_1_0.zip	151 KiB	05/17/2022 08:16:18 PM +00:00