================================================================
== Vivado HLS Report for 'write_pixel'
================================================================
* Date:           Wed May 30 18:59:16 2018

* Version:        2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017)
* Project:        edge_detection
* Solution:       solution0
* Product family: zynq
* Target device:  xc7z020clg484-1


================================================================
== Performance Estimates
================================================================
+ Timing (ns): 
    * Summary: 
    +--------+-------+----------+------------+
    |  Clock | Target| Estimated| Uncertainty|
    +--------+-------+----------+------------+
    |ap_clk  |  10.00|      8.75|        1.25|
    +--------+-------+----------+------------+

+ Latency (clock cycles): 
    * Summary: 
    +-----+-----+-----+-----+---------+
    |  Latency  |  Interval | Pipeline|
    | min | max | min | max |   Type  |
    +-----+-----+-----+-----+---------+
    |  332|  332|  332|  332|   none  |
    +-----+-----+-----+-----+---------+

    + Detail: 
        * Instance: 
        N/A

        * Loop: 
        +--------------+-----+-----+----------+-----------+-----------+------+----------+
        |              |  Latency  | Iteration|  Initiation Interval  | Trip |          |
        |   Loop Name  | min | max |  Latency |  achieved |   target  | Count| Pipelined|
        +--------------+-----+-----+----------+-----------+-----------+------+----------+
        |- write_loop  |  325|  325|         3|          1|          1|   324|    yes   |
        +--------------+-----+-----+----------+-----------+-----------+------+----------+



================================================================
== Utilization Estimates
================================================================
* Summary: 
+-----------------+---------+-------+--------+-------+
|       Name      | BRAM_18K| DSP48E|   FF   |  LUT  |
+-----------------+---------+-------+--------+-------+
|DSP              |        -|      -|       -|      -|
|Expression       |        -|      -|       0|     85|
|FIFO             |        -|      -|       -|      -|
|Instance         |        -|      -|       -|      -|
|Memory           |        -|      -|       -|      -|
|Multiplexer      |        -|      -|       -|    143|
|Register         |        -|      -|      87|      -|
+-----------------+---------+-------+--------+-------+
|Total            |        0|      0|      87|    228|
+-----------------+---------+-------+--------+-------+
|Available        |      280|    220|  106400|  53200|
+-----------------+---------+-------+--------+-------+
|Utilization (%)  |        0|      0|   ~0   |   ~0  |
+-----------------+---------+-------+--------+-------+

+ Detail: 
    * Instance: 
    N/A

    * DSP48: 
    N/A

    * Memory: 
    N/A

    * FIFO: 
    N/A

    * Expression: 
    +----------------------------------+----------+-------+---+----+------------+------------+
    |           Variable Name          | Operation| DSP48E| FF| LUT| Bitwidth P0| Bitwidth P1|
    +----------------------------------+----------+-------+---+----+------------+------------+
    |i_fu_157_p2                       |     +    |      0|  0|  16|           9|           1|
    |ap_block_pp0_stage0_01001         |    and   |      0|  0|   8|           1|           1|
    |ap_block_state4_pp0_stage0_iter1  |    and   |      0|  0|   8|           1|           1|
    |ap_block_state5_io                |    and   |      0|  0|   8|           1|           1|
    |exitcond_i_fu_151_p2              |   icmp   |      0|  0|  13|           9|           9|
    |ap_block_pp0_stage0_11001         |    or    |      0|  0|   8|           1|           1|
    |ap_block_state1                   |    or    |      0|  0|   8|           1|           1|
    |ap_enable_pp0                     |    xor   |      0|  0|   8|           1|           2|
    |ap_enable_reg_pp0_iter1           |    xor   |      0|  0|   8|           2|           1|
    +----------------------------------+----------+-------+---+----+------------+------------+
    |Total                             |          |      0|  0|  85|          26|          18|
    +----------------------------------+----------+-------+---+----+------------+------------+

    * Multiplexer: 
    +----------------------------------------+----+-----------+-----+-----------+
    |                  Name                  | LUT| Input Size| Bits| Total Bits|
    +----------------------------------------+----+-----------+-----+-----------+
    |ap_NS_fsm                               |  44|          9|    1|          9|
    |ap_done                                 |   9|          2|    1|          2|
    |ap_enable_reg_pp0_iter1                 |   9|          2|    1|          2|
    |ap_enable_reg_pp0_iter2                 |   9|          2|    1|          2|
    |ap_sig_ioackin_m_axi_out_array_AWREADY  |   9|          2|    1|          2|
    |ap_sig_ioackin_m_axi_out_array_WREADY   |   9|          2|    1|          2|
    |i_i_reg_120                             |   9|          2|    9|         18|
    |out_array_blk_n_AW                      |   9|          2|    1|          2|
    |out_array_blk_n_B                       |   9|          2|    1|          2|
    |out_array_blk_n_W                       |   9|          2|    1|          2|
    |out_array_offset_blk_n                  |   9|          2|    1|          2|
    |out_stream_V_blk_n                      |   9|          2|    1|          2|
    +----------------------------------------+----+-----------+-----+-----------+
    |Total                                   | 143|         31|   20|         47|
    +----------------------------------------+----+-----------+-----+-----------+

    * Register: 
    +----------------------------------------+----+----+-----+-----------+
    |                  Name                  | FF | LUT| Bits| Const Bits|
    +----------------------------------------+----+----+-----+-----------+
    |ap_CS_fsm                               |   8|   0|    8|          0|
    |ap_done_reg                             |   1|   0|    1|          0|
    |ap_enable_reg_pp0_iter0                 |   1|   0|    1|          0|
    |ap_enable_reg_pp0_iter1                 |   1|   0|    1|          0|
    |ap_enable_reg_pp0_iter2                 |   1|   0|    1|          0|
    |ap_reg_ioackin_m_axi_out_array_AWREADY  |   1|   0|    1|          0|
    |ap_reg_ioackin_m_axi_out_array_WREADY   |   1|   0|    1|          0|
    |ap_reg_pp0_iter1_exitcond_i_reg_174     |   1|   0|    1|          0|
    |exitcond_i_reg_174                      |   1|   0|    1|          0|
    |i_i_reg_120                             |   9|   0|    9|          0|
    |out_array_offset1_i_reg_163             |  30|   0|   30|          0|
    |tmp_reg_183                             |  32|   0|   32|          0|
    +----------------------------------------+----+----+-----+-----------+
    |Total                                   |  87|   0|   87|          0|
    +----------------------------------------+----+----+-----+-----------+



================================================================
== Interface
================================================================
* Summary: 
+--------------------------+-----+-----+------------+------------------+--------------+
|         RTL Ports        | Dir | Bits|  Protocol  |   Source Object  |    C Type    |
+--------------------------+-----+-----+------------+------------------+--------------+
|ap_clk                    |  in |    1| ap_ctrl_hs |    write_pixel   | return value |
|ap_rst                    |  in |    1| ap_ctrl_hs |    write_pixel   | return value |
|ap_start                  |  in |    1| ap_ctrl_hs |    write_pixel   | return value |
|ap_done                   | out |    1| ap_ctrl_hs |    write_pixel   | return value |
|ap_continue               |  in |    1| ap_ctrl_hs |    write_pixel   | return value |
|ap_idle                   | out |    1| ap_ctrl_hs |    write_pixel   | return value |
|ap_ready                  | out |    1| ap_ctrl_hs |    write_pixel   | return value |
|out_stream_V_dout         |  in |   32|   ap_fifo  |   out_stream_V   |    pointer   |
|out_stream_V_empty_n      |  in |    1|   ap_fifo  |   out_stream_V   |    pointer   |
|out_stream_V_read         | out |    1|   ap_fifo  |   out_stream_V   |    pointer   |
|m_axi_out_array_AWVALID   | out |    1|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_AWREADY   |  in |    1|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_AWADDR    | out |   32|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_AWID      | out |    1|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_AWLEN     | out |   32|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_AWSIZE    | out |    3|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_AWBURST   | out |    2|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_AWLOCK    | out |    2|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_AWCACHE   | out |    4|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_AWPROT    | out |    3|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_AWQOS     | out |    4|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_AWREGION  | out |    4|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_AWUSER    | out |    1|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_WVALID    | out |    1|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_WREADY    |  in |    1|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_WDATA     | out |   32|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_WSTRB     | out |    4|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_WLAST     | out |    1|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_WID       | out |    1|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_WUSER     | out |    1|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_ARVALID   | out |    1|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_ARREADY   |  in |    1|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_ARADDR    | out |   32|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_ARID      | out |    1|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_ARLEN     | out |   32|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_ARSIZE    | out |    3|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_ARBURST   | out |    2|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_ARLOCK    | out |    2|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_ARCACHE   | out |    4|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_ARPROT    | out |    3|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_ARQOS     | out |    4|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_ARREGION  | out |    4|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_ARUSER    | out |    1|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_RVALID    |  in |    1|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_RREADY    | out |    1|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_RDATA     |  in |   32|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_RLAST     |  in |    1|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_RID       |  in |    1|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_RUSER     |  in |    1|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_RRESP     |  in |    2|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_BVALID    |  in |    1|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_BREADY    | out |    1|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_BRESP     |  in |    2|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_BID       |  in |    1|    m_axi   |     out_array    |    pointer   |
|m_axi_out_array_BUSER     |  in |    1|    m_axi   |     out_array    |    pointer   |
|out_array_offset_dout     |  in |   32|   ap_fifo  | out_array_offset |    pointer   |
|out_array_offset_empty_n  |  in |    1|   ap_fifo  | out_array_offset |    pointer   |
|out_array_offset_read     | out |    1|   ap_fifo  | out_array_offset |    pointer   |
+--------------------------+-----+-----+------------+------------------+--------------+

============================================================
+ Verbose Summary: Synthesis Manager
============================================================
InlineROM: 1
ExposeGlobal: 0
============================================================
+ Verbose Summary: CDFG Model
============================================================
IsTopModel: 0
ResetActiveHigh: 1
IsCombinational: 2
IsDatapathOnly: 0
HasWiredReturn: 1
HasMFsm: 0
HasVarLatency: 1
IsPipeline: 0
IsRtlPipelined: 0
IsInstanceOverlapped: 0
IsDontTouch: 0
HasImplIP: 0
IsGatedGlobalClock: 0

+ Individual pipeline summary: 
  * Pipeline-0: initiation interval (II) = 1, depth = 3


============================================================
+ Verbose Summary: Schedule
============================================================
* Number of FSM states : 10
* Pipeline : 1
  Pipeline-0 : II = 1, D = 3, States = { 3 4 5 }
* Dataflow Pipeline: 0

* FSM state transitions: 
1 --> 
	2  / true
2 --> 
	3  / true
3 --> 
	6  / (exitcond_i)
	4  / (!exitcond_i)
4 --> 
	5  / true
5 --> 
	3  / true
6 --> 
	7  / true
7 --> 
	8  / true
8 --> 
	9  / true
9 --> 
	10  / true
10 --> 

* FSM state operations: 

 <State 1> : 3.63ns
ST_1 : Operation 11 [1/1] (3.63ns)   --->   "%out_array_offset_rea = call i32 @_ssdm_op_Read.ap_fifo.i32P(i32* %out_array_offset)"   --->   Core 32 'FIFO' <Latency = 0> <II = 1> <Delay = 3.63> <Storage> <Opcode : 'read' 'write' 'nbread' 'nbwrite'> <Ports = 0> <Width = 32> <Depth = 2> <FIFO>
ST_1 : Operation 12 [1/1] (0.00ns)   --->   "%out_array_offset1_i = call i30 @_ssdm_op_PartSelect.i30.i32.i32.i32(i32 %out_array_offset_rea, i32 2, i32 31)"

 <State 2> : 8.75ns
ST_2 : Operation 13 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(float* %out_stream_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str44, i32 0, i32 0, [1 x i8]* @p_str45, [1 x i8]* @p_str46, [1 x i8]* @p_str47, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str48, [1 x i8]* @p_str49)"
ST_2 : Operation 14 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(float* %out_array, [6 x i8]* @p_str6, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 400, [10 x i8]* @p_str7, [6 x i8]* @p_str8, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)"
ST_2 : Operation 15 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(i32* %out_array_offset, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str29, i32 0, i32 0, [1 x i8]* @p_str30, [1 x i8]* @p_str31, [1 x i8]* @p_str32, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str33, [1 x i8]* @p_str34)"
ST_2 : Operation 16 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(float* %out_stream_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str44, i32 0, i32 0, [1 x i8]* @p_str45, [1 x i8]* @p_str46, [1 x i8]* @p_str47, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str48, [1 x i8]* @p_str49)"
ST_2 : Operation 17 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(float* %out_array, [6 x i8]* @p_str6, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 400, [10 x i8]* @p_str7, [6 x i8]* @p_str8, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)"
ST_2 : Operation 18 [1/1] (0.00ns)   --->   "%sext_i = zext i30 %out_array_offset1_i to i64"
ST_2 : Operation 19 [1/1] (0.00ns)   --->   "%out_array_addr = getelementptr float* %out_array, i64 %sext_i"
ST_2 : Operation 20 [1/1] (8.75ns)   --->   "%out_array_addr_i_wr_s = call i1 @_ssdm_op_WriteReq.m_axi.floatP(float* %out_array_addr, i32 324)" [edge_detection/edge_detection.cpp:72]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_2 : Operation 21 [1/1] (1.76ns)   --->   "br label %0" [edge_detection/edge_detection.cpp:69]

 <State 3> : 1.94ns
ST_3 : Operation 22 [1/1] (0.00ns)   --->   "%i_i = phi i9 [ 0, %entry ], [ %i, %1 ]"
ST_3 : Operation 23 [1/1] (1.66ns)   --->   "%exitcond_i = icmp eq i9 %i_i, -188" [edge_detection/edge_detection.cpp:69]   --->   Core 25 'Cmp' <Latency = 0> <II = 1> <Delay = 1.66> <FuncUnit> <Opcode : 'icmp'> <InPorts = 2> <OutPorts = 1>
ST_3 : Operation 24 [1/1] (1.93ns)   --->   "%i = add i9 %i_i, 1" [edge_detection/edge_detection.cpp:69]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 1.93> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_3 : Operation 25 [1/1] (0.00ns)   --->   "br i1 %exitcond_i, label %.exit, label %1" [edge_detection/edge_detection.cpp:69]

 <State 4> : 3.63ns
ST_4 : Operation 26 [1/1] (3.63ns)   --->   "%tmp = call float @_ssdm_op_Read.ap_fifo.volatile.floatP(float* %out_stream_V)" [edge_detection/edge_detection.cpp:71]   --->   Core 32 'FIFO' <Latency = 0> <II = 1> <Delay = 3.63> <Storage> <Opcode : 'read' 'write' 'nbread' 'nbwrite'> <Ports = 0> <Width = 32> <Depth = 2> <FIFO>

 <State 5> : 8.75ns
ST_5 : Operation 27 [1/1] (0.00ns)   --->   "%empty = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 324, i64 324, i64 324)"
ST_5 : Operation 28 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecLoopName([11 x i8]* @p_str2) nounwind" [edge_detection/edge_detection.cpp:69]
ST_5 : Operation 29 [1/1] (0.00ns)   --->   "%tmp_2_i = call i32 (...)* @_ssdm_op_SpecRegionBegin([11 x i8]* @p_str2)" [edge_detection/edge_detection.cpp:69]
ST_5 : Operation 30 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind" [edge_detection/edge_detection.cpp:70]
ST_5 : Operation 31 [1/1] (8.75ns)   --->   "call void @_ssdm_op_Write.m_axi.floatP(float* %out_array_addr, float %tmp, i4 -1)" [edge_detection/edge_detection.cpp:72]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_5 : Operation 32 [1/1] (0.00ns)   --->   "%empty_9 = call i32 (...)* @_ssdm_op_SpecRegionEnd([11 x i8]* @p_str2, i32 %tmp_2_i)" [edge_detection/edge_detection.cpp:73]
ST_5 : Operation 33 [1/1] (0.00ns)   --->   "br label %0" [edge_detection/edge_detection.cpp:69]

 <State 6> : 8.75ns
ST_6 : Operation 34 [5/5] (8.75ns)   --->   "%out_array_addr_i_wr_1 = call i1 @_ssdm_op_WriteResp.m_axi.floatP(float* %out_array_addr)" [edge_detection/edge_detection.cpp:72]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 7> : 8.75ns
ST_7 : Operation 35 [4/5] (8.75ns)   --->   "%out_array_addr_i_wr_1 = call i1 @_ssdm_op_WriteResp.m_axi.floatP(float* %out_array_addr)" [edge_detection/edge_detection.cpp:72]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 8> : 8.75ns
ST_8 : Operation 36 [3/5] (8.75ns)   --->   "%out_array_addr_i_wr_1 = call i1 @_ssdm_op_WriteResp.m_axi.floatP(float* %out_array_addr)" [edge_detection/edge_detection.cpp:72]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 9> : 8.75ns
ST_9 : Operation 37 [2/5] (8.75ns)   --->   "%out_array_addr_i_wr_1 = call i1 @_ssdm_op_WriteResp.m_axi.floatP(float* %out_array_addr)" [edge_detection/edge_detection.cpp:72]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 10> : 8.75ns
ST_10 : Operation 38 [1/5] (8.75ns)   --->   "%out_array_addr_i_wr_1 = call i1 @_ssdm_op_WriteResp.m_axi.floatP(float* %out_array_addr)" [edge_detection/edge_detection.cpp:72]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_10 : Operation 39 [1/1] (0.00ns)   --->   "ret void"


============================================================
+ Verbose Summary: Binding
============================================================
STG Binding: 
---------------- STG Properties BEGIN ----------------
- Is combinational: 0
- Is one-state seq: 0
- Is datapath-only: 0
- Is pipelined: 0
- Is top level: 0
Port [ Return ] is wired: 1; IO mode=ap_ctrl_hs:ce=0
Port [ out_stream_V]:  wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
Port [ out_array]:  wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=1; type=4; pingpong=0; private_global=0; IO mode=m_axi:ce=0
Port [ out_array_offset]:  wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
---------------- STG Properties END ------------------

---------------- Datapath Model BEGIN ----------------

<LifeTime>
<method=bitvector/>
out_array_offset_rea  (read             ) [ 00000000000]
out_array_offset1_i   (partselect       ) [ 00100000000]
StgValue_13           (specinterface    ) [ 00000000000]
StgValue_14           (specinterface    ) [ 00000000000]
StgValue_15           (specinterface    ) [ 00000000000]
StgValue_16           (specinterface    ) [ 00000000000]
StgValue_17           (specinterface    ) [ 00000000000]
sext_i                (zext             ) [ 00000000000]
out_array_addr        (getelementptr    ) [ 00011111111]
out_array_addr_i_wr_s (writereq         ) [ 00000000000]
StgValue_21           (br               ) [ 00111100000]
i_i                   (phi              ) [ 00010000000]
exitcond_i            (icmp             ) [ 00011100000]
i                     (add              ) [ 00111100000]
StgValue_25           (br               ) [ 00000000000]
tmp                   (read             ) [ 00010100000]
empty                 (speclooptripcount) [ 00000000000]
StgValue_28           (specloopname     ) [ 00000000000]
tmp_2_i               (specregionbegin  ) [ 00000000000]
StgValue_30           (specpipeline     ) [ 00000000000]
StgValue_31           (write            ) [ 00000000000]
empty_9               (specregionend    ) [ 00000000000]
StgValue_33           (br               ) [ 00111100000]
out_array_addr_i_wr_1 (writeresp        ) [ 00000000000]
StgValue_39           (ret              ) [ 00000000000]
</LifeTime>

<model>

<comp_list>
<comp id="0" class="1000" name="out_stream_V">
<pin_list>
<pin id="1" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="out_stream_V"/></StgValue>
</bind>
</comp>

<comp id="2" class="1000" name="out_array">
<pin_list>
<pin id="3" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="out_array"/></StgValue>
</bind>
</comp>

<comp id="4" class="1000" name="out_array_offset">
<pin_list>
<pin id="5" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="out_array_offset"/></StgValue>
</bind>
</comp>

<comp id="6" class="1001" name="const_6">
<pin_list>
<pin id="7" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_Read.ap_fifo.i32P"/></StgValue>
</bind>
</comp>

<comp id="8" class="1001" name="const_8">
<pin_list>
<pin id="9" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_PartSelect.i30.i32.i32.i32"/></StgValue>
</bind>
</comp>

<comp id="10" class="1001" name="const_10">
<pin_list>
<pin id="11" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="12" class="1001" name="const_12">
<pin_list>
<pin id="13" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="14" class="1001" name="const_14">
<pin_list>
<pin id="15" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecInterface"/></StgValue>
</bind>
</comp>

<comp id="16" class="1001" name="const_16">
<pin_list>
<pin id="17" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="ap_fifo_str"/></StgValue>
</bind>
</comp>

<comp id="18" class="1001" name="const_18">
<pin_list>
<pin id="19" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="20" class="1001" name="const_20">
<pin_list>
<pin id="21" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str44"/></StgValue>
</bind>
</comp>

<comp id="22" class="1001" name="const_22">
<pin_list>
<pin id="23" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str45"/></StgValue>
</bind>
</comp>

<comp id="24" class="1001" name="const_24">
<pin_list>
<pin id="25" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str46"/></StgValue>
</bind>
</comp>

<comp id="26" class="1001" name="const_26">
<pin_list>
<pin id="27" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str47"/></StgValue>
</bind>
</comp>

<comp id="28" class="1001" name="const_28">
<pin_list>
<pin id="29" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="30" class="1001" name="const_30">
<pin_list>
<pin id="31" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str48"/></StgValue>
</bind>
</comp>

<comp id="32" class="1001" name="const_32">
<pin_list>
<pin id="33" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str49"/></StgValue>
</bind>
</comp>

<comp id="34" class="1001" name="const_34">
<pin_list>
<pin id="35" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str6"/></StgValue>
</bind>
</comp>

<comp id="36" class="1001" name="const_36">
<pin_list>
<pin id="37" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str1"/></StgValue>
</bind>
</comp>

<comp id="38" class="1001" name="const_38">
<pin_list>
<pin id="39" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="40" class="1001" name="const_40">
<pin_list>
<pin id="41" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str7"/></StgValue>
</bind>
</comp>

<comp id="42" class="1001" name="const_42">
<pin_list>
<pin id="43" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str8"/></StgValue>
</bind>
</comp>

<comp id="44" class="1001" name="const_44">
<pin_list>
<pin id="45" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str29"/></StgValue>
</bind>
</comp>

<comp id="46" class="1001" name="const_46">
<pin_list>
<pin id="47" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str30"/></StgValue>
</bind>
</comp>

<comp id="48" class="1001" name="const_48">
<pin_list>
<pin id="49" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str31"/></StgValue>
</bind>
</comp>

<comp id="50" class="1001" name="const_50">
<pin_list>
<pin id="51" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str32"/></StgValue>
</bind>
</comp>

<comp id="52" class="1001" name="const_52">
<pin_list>
<pin id="53" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str33"/></StgValue>
</bind>
</comp>

<comp id="54" class="1001" name="const_54">
<pin_list>
<pin id="55" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str34"/></StgValue>
</bind>
</comp>

<comp id="56" class="1001" name="const_56">
<pin_list>
<pin id="57" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_WriteReq.m_axi.floatP"/></StgValue>
</bind>
</comp>

<comp id="58" class="1001" name="const_58">
<pin_list>
<pin id="59" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="60" class="1001" name="const_60">
<pin_list>
<pin id="61" dir="1" index="0" bw="1" slack="1"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="62" class="1001" name="const_62">
<pin_list>
<pin id="63" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="64" class="1001" name="const_64">
<pin_list>
<pin id="65" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="66" class="1001" name="const_66">
<pin_list>
<pin id="67" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_Read.ap_fifo.volatile.floatP"/></StgValue>
</bind>
</comp>

<comp id="68" class="1001" name="const_68">
<pin_list>
<pin id="69" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecLoopTripCount"/></StgValue>
</bind>
</comp>

<comp id="70" class="1001" name="const_70">
<pin_list>
<pin id="71" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="72" class="1001" name="const_72">
<pin_list>
<pin id="73" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecLoopName"/></StgValue>
</bind>
</comp>

<comp id="74" class="1001" name="const_74">
<pin_list>
<pin id="75" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str2"/></StgValue>
</bind>
</comp>

<comp id="76" class="1001" name="const_76">
<pin_list>
<pin id="77" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecRegionBegin"/></StgValue>
</bind>
</comp>

<comp id="78" class="1001" name="const_78">
<pin_list>
<pin id="79" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecPipeline"/></StgValue>
</bind>
</comp>

<comp id="80" class="1001" name="const_80">
<pin_list>
<pin id="81" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="82" class="1001" name="const_82">
<pin_list>
<pin id="83" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="84" class="1001" name="const_84">
<pin_list>
<pin id="85" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_Write.m_axi.floatP"/></StgValue>
</bind>
</comp>

<comp id="86" class="1001" name="const_86">
<pin_list>
<pin id="87" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="88" class="1001" name="const_88">
<pin_list>
<pin id="89" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecRegionEnd"/></StgValue>
</bind>
</comp>

<comp id="90" class="1001" name="const_90">
<pin_list>
<pin id="91" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_WriteResp.m_axi.floatP"/></StgValue>
</bind>
</comp>

<comp id="92" class="1004" name="out_array_offset_rea_read_fu_92">
<pin_list>
<pin id="93" dir="0" index="0" bw="32" slack="0"/>
<pin id="94" dir="0" index="1" bw="32" slack="0"/>
<pin id="95" dir="1" index="2" bw="32" slack="0"/>
</pin_list>
<bind>
<opcode="read(1150) " fcode="read"/>
<opset="out_array_offset_rea/1 "/>
</bind>
</comp>

<comp id="98" class="1004" name="grp_writeresp_fu_98">
<pin_list>
<pin id="99" dir="0" index="0" bw="1" slack="0"/>
<pin id="100" dir="0" index="1" bw="32" slack="0"/>
<pin id="101" dir="0" index="2" bw="10" slack="0"/>
<pin id="102" dir="1" index="3" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<opcode="writereq(1155) writeresp(1158) " fcode="writeresp"/>
<opset="out_array_addr_i_wr_s/2 out_array_addr_i_wr_1/6 "/>
</bind>
</comp>

<comp id="105" class="1004" name="tmp_read_fu_105">
<pin_list>
<pin id="106" dir="0" index="0" bw="32" slack="0"/>
<pin id="107" dir="0" index="1" bw="32" slack="0"/>
<pin id="108" dir="1" index="2" bw="32" slack="1"/>
</pin_list>
<bind>
<opcode="read(1150) " fcode="read"/>
<opset="tmp/4 "/>
</bind>
</comp>

<comp id="111" class="1004" name="StgValue_31_write_fu_111">
<pin_list>
<pin id="112" dir="0" index="0" bw="0" slack="0"/>
<pin id="113" dir="0" index="1" bw="32" slack="3"/>
<pin id="114" dir="0" index="2" bw="32" slack="1"/>
<pin id="115" dir="0" index="3" bw="1" slack="0"/>
<pin id="116" dir="1" index="4" bw="0" slack="2147483647"/>
</pin_list>
<bind>
<opcode="write(1151) " fcode="write"/>
<opset="StgValue_31/5 "/>
</bind>
</comp>

<comp id="120" class="1005" name="i_i_reg_120">
<pin_list>
<pin id="121" dir="0" index="0" bw="9" slack="1"/>
<pin id="122" dir="1" index="1" bw="9" slack="1"/>
</pin_list>
<bind>
<opset="i_i (phireg) "/>
</bind>
</comp>

<comp id="124" class="1004" name="i_i_phi_fu_124">
<pin_list>
<pin id="125" dir="0" index="0" bw="1" slack="1"/>
<pin id="126" dir="0" index="1" bw="0" slack="2147483647"/>
<pin id="127" dir="0" index="2" bw="9" slack="0"/>
<pin id="128" dir="0" index="3" bw="0" slack="2147483647"/>
<pin id="129" dir="1" index="4" bw="9" slack="0"/>
</pin_list>
<bind>
<opcode="phi(47) " fcode="phi"/>
<opset="i_i/3 "/>
</bind>
</comp>

<comp id="131" class="1004" name="out_array_offset1_i_fu_131">
<pin_list>
<pin id="132" dir="0" index="0" bw="30" slack="0"/>
<pin id="133" dir="0" index="1" bw="32" slack="0"/>
<pin id="134" dir="0" index="2" bw="3" slack="0"/>
<pin id="135" dir="0" index="3" bw="6" slack="0"/>
<pin id="136" dir="1" index="4" bw="30" slack="1"/>
</pin_list>
<bind>
<opcode="partselect(1002) " fcode="partselect"/>
<opset="out_array_offset1_i/1 "/>
</bind>
</comp>

<comp id="141" class="1004" name="sext_i_fu_141">
<pin_list>
<pin id="142" dir="0" index="0" bw="30" slack="1"/>
<pin id="143" dir="1" index="1" bw="64" slack="0"/>
</pin_list>
<bind>
<opcode="zext(34) " fcode="zext"/>
<opset="sext_i/2 "/>
</bind>
</comp>

<comp id="144" class="1004" name="out_array_addr_fu_144">
<pin_list>
<pin id="145" dir="0" index="0" bw="32" slack="0"/>
<pin id="146" dir="0" index="1" bw="32" slack="0"/>
<pin id="147" dir="1" index="2" bw="32" slack="0"/>
</pin_list>
<bind>
<opcode="getelementptr(29) " fcode="getelementptr"/>
<opset="out_array_addr/2 "/>
</bind>
</comp>

<comp id="151" class="1004" name="exitcond_i_fu_151">
<pin_list>
<pin id="152" dir="0" index="0" bw="9" slack="0"/>
<pin id="153" dir="0" index="1" bw="9" slack="0"/>
<pin id="154" dir="1" index="2" bw="1" slack="1"/>
</pin_list>
<bind>
<opcode="icmp(45) " fcode="icmp"/>
<opset="exitcond_i/3 "/>
</bind>
</comp>

<comp id="157" class="1004" name="i_fu_157">
<pin_list>
<pin id="158" dir="0" index="0" bw="9" slack="0"/>
<pin id="159" dir="0" index="1" bw="1" slack="0"/>
<pin id="160" dir="1" index="2" bw="9" slack="0"/>
</pin_list>
<bind>
<opcode="add(8) " fcode="add"/>
<opset="i/3 "/>
</bind>
</comp>

<comp id="163" class="1005" name="out_array_offset1_i_reg_163">
<pin_list>
<pin id="164" dir="0" index="0" bw="30" slack="1"/>
<pin id="165" dir="1" index="1" bw="30" slack="1"/>
</pin_list>
<bind>
<opset="out_array_offset1_i "/>
</bind>
</comp>

<comp id="168" class="1005" name="out_array_addr_reg_168">
<pin_list>
<pin id="169" dir="0" index="0" bw="32" slack="2"/>
<pin id="170" dir="1" index="1" bw="32" slack="2"/>
</pin_list>
<bind>
<opset="out_array_addr "/>
</bind>
</comp>

<comp id="174" class="1005" name="exitcond_i_reg_174">
<pin_list>
<pin id="175" dir="0" index="0" bw="1" slack="1"/>
<pin id="176" dir="1" index="1" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<opset="exitcond_i "/>
</bind>
</comp>

<comp id="178" class="1005" name="i_reg_178">
<pin_list>
<pin id="179" dir="0" index="0" bw="9" slack="0"/>
<pin id="180" dir="1" index="1" bw="9" slack="0"/>
</pin_list>
<bind>
<opset="i "/>
</bind>
</comp>

<comp id="183" class="1005" name="tmp_reg_183">
<pin_list>
<pin id="184" dir="0" index="0" bw="32" slack="1"/>
<pin id="185" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="tmp "/>
</bind>
</comp>

</comp_list>

<net_list>
<net id="96"><net_src comp="6" pin="0"/><net_sink comp="92" pin=0"/></net>

<net id="97"><net_src comp="4" pin="0"/><net_sink comp="92" pin=1"/></net>

<net id="103"><net_src comp="56" pin="0"/><net_sink comp="98" pin=0"/></net>

<net id="104"><net_src comp="58" pin="0"/><net_sink comp="98" pin=2"/></net>

<net id="109"><net_src comp="66" pin="0"/><net_sink comp="105" pin=0"/></net>

<net id="110"><net_src comp="0" pin="0"/><net_sink comp="105" pin=1"/></net>

<net id="117"><net_src comp="84" pin="0"/><net_sink comp="111" pin=0"/></net>

<net id="118"><net_src comp="86" pin="0"/><net_sink comp="111" pin=3"/></net>

<net id="119"><net_src comp="90" pin="0"/><net_sink comp="98" pin=0"/></net>

<net id="123"><net_src comp="60" pin="0"/><net_sink comp="120" pin=0"/></net>

<net id="130"><net_src comp="120" pin="1"/><net_sink comp="124" pin=0"/></net>

<net id="137"><net_src comp="8" pin="0"/><net_sink comp="131" pin=0"/></net>

<net id="138"><net_src comp="92" pin="2"/><net_sink comp="131" pin=1"/></net>

<net id="139"><net_src comp="10" pin="0"/><net_sink comp="131" pin=2"/></net>

<net id="140"><net_src comp="12" pin="0"/><net_sink comp="131" pin=3"/></net>

<net id="148"><net_src comp="2" pin="0"/><net_sink comp="144" pin=0"/></net>

<net id="149"><net_src comp="141" pin="1"/><net_sink comp="144" pin=1"/></net>

<net id="150"><net_src comp="144" pin="2"/><net_sink comp="98" pin=1"/></net>

<net id="155"><net_src comp="124" pin="4"/><net_sink comp="151" pin=0"/></net>

<net id="156"><net_src comp="62" pin="0"/><net_sink comp="151" pin=1"/></net>

<net id="161"><net_src comp="124" pin="4"/><net_sink comp="157" pin=0"/></net>

<net id="162"><net_src comp="64" pin="0"/><net_sink comp="157" pin=1"/></net>

<net id="166"><net_src comp="131" pin="4"/><net_sink comp="163" pin=0"/></net>

<net id="167"><net_src comp="163" pin="1"/><net_sink comp="141" pin=0"/></net>

<net id="171"><net_src comp="144" pin="2"/><net_sink comp="168" pin=0"/></net>

<net id="172"><net_src comp="168" pin="1"/><net_sink comp="111" pin=1"/></net>

<net id="173"><net_src comp="168" pin="1"/><net_sink comp="98" pin=1"/></net>

<net id="177"><net_src comp="151" pin="2"/><net_sink comp="174" pin=0"/></net>

<net id="181"><net_src comp="157" pin="2"/><net_sink comp="178" pin=0"/></net>

<net id="182"><net_src comp="178" pin="1"/><net_sink comp="124" pin=2"/></net>

<net id="186"><net_src comp="105" pin="2"/><net_sink comp="183" pin=0"/></net>

<net id="187"><net_src comp="183" pin="1"/><net_sink comp="111" pin=2"/></net>

</net_list>

</model> 
---------------- Datapath Model END ------------------

* FSMD analyzer results:
  - Output states:
	Port: out_array | {2 5 6 7 8 9 10 }
 - Input state : 
	Port: write_pixel : out_stream_V | {4 }
	Port: write_pixel : out_array | {}
	Port: write_pixel : out_array_offset | {1 }
  - Chain level:
	State 1
	State 2
		out_array_addr : 1
		out_array_addr_i_wr_s : 2
	State 3
		exitcond_i : 1
		i : 1
		StgValue_25 : 2
	State 4
	State 5
		empty_9 : 1
	State 6
	State 7
	State 8
	State 9
	State 10


============================================================
+ Verbose Summary: Datapath Resource usage 
============================================================

* Functional unit list:
|----------|---------------------------------|---------|---------|
| Operation|         Functional Unit         |    FF   |   LUT   |
|----------|---------------------------------|---------|---------|
|    add   |             i_fu_157            |    0    |    16   |
|----------|---------------------------------|---------|---------|
|   icmp   |        exitcond_i_fu_151        |    0    |    13   |
|----------|---------------------------------|---------|---------|
|   read   | out_array_offset_rea_read_fu_92 |    0    |    0    |
|          |         tmp_read_fu_105         |    0    |    0    |
|----------|---------------------------------|---------|---------|
| writeresp|       grp_writeresp_fu_98       |    0    |    0    |
|----------|---------------------------------|---------|---------|
|   write  |     StgValue_31_write_fu_111    |    0    |    0    |
|----------|---------------------------------|---------|---------|
|partselect|    out_array_offset1_i_fu_131   |    0    |    0    |
|----------|---------------------------------|---------|---------|
|   zext   |          sext_i_fu_141          |    0    |    0    |
|----------|---------------------------------|---------|---------|
|   Total  |                                 |    0    |    29   |
|----------|---------------------------------|---------|---------|

Memories:
N/A

* Register list:
+---------------------------+--------+
|                           |   FF   |
+---------------------------+--------+
|     exitcond_i_reg_174    |    1   |
|        i_i_reg_120        |    9   |
|         i_reg_178         |    9   |
|   out_array_addr_reg_168  |   32   |
|out_array_offset1_i_reg_163|   30   |
|        tmp_reg_183        |   32   |
+---------------------------+--------+
|           Total           |   113  |
+---------------------------+--------+

* Multiplexer (MUX) list: 
|---------------------|------|------|------|--------||---------||---------|
|         Comp        |  Pin | Size |  BW  | S x BW ||  Delay  ||   LUT   |
|---------------------|------|------|------|--------||---------||---------|
| grp_writeresp_fu_98 |  p0  |   2  |   1  |    2   |
| grp_writeresp_fu_98 |  p1  |   2  |  32  |   64   ||    9    |
|---------------------|------|------|------|--------||---------||---------|
|        Total        |      |      |      |   66   ||  3.538  ||    9    |
|---------------------|------|------|------|--------||---------||---------|



* Summary:
+-----------+--------+--------+--------+
|           |  Delay |   FF   |   LUT  |
+-----------+--------+--------+--------+
|  Function |    -   |    0   |   29   |
|   Memory  |    -   |    -   |    -   |
|Multiplexer|    3   |    -   |    9   |
|  Register |    -   |   113  |    -   |
+-----------+--------+--------+--------+
|   Total   |    3   |   113  |   38   |
+-----------+--------+--------+--------+