================================================================
== Vivado HLS Report for 'conv_stream'
================================================================
* Date:           Wed May 30 18:59:15 2018

* Version:        2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017)
* Project:        edge_detection
* Solution:       solution0
* Product family: zynq
* Target device:  xc7z020clg484-1


================================================================
== Performance Estimates
================================================================
+ Timing (ns): 
    * Summary: 
    +--------+-------+----------+------------+
    |  Clock | Target| Estimated| Uncertainty|
    +--------+-------+----------+------------+
    |ap_clk  |  10.00|      8.75|        1.25|
    +--------+-------+----------+------------+

+ Latency (clock cycles): 
    * Summary: 
    +-----+-----+-----+-----+----------+
    |  Latency  |  Interval | Pipeline |
    | min | max | min | max |   Type   |
    +-----+-----+-----+-----+----------+
    |  465|  465|  452|  452| dataflow |
    +-----+-----+-----+-----+----------+

    + Detail: 
        * Instance: 
        +-------------------------+--------------+-----+-----+-----+-----+---------+
        |                         |              |  Latency  |  Interval | Pipeline|
        |         Instance        |    Module    | min | max | min | max |   Type  |
        +-------------------------+--------------+-----+-----+-----+-----+---------+
        |grp_convolve_fu_138      |convolve      |  451|  451|  451|  451|   none  |
        |grp_write_pixel_fu_144   |write_pixel   |  332|  332|  332|  332|   none  |
        |grp_read_pixel13_fu_152  |read_pixel13  |  409|  409|  409|  409|   none  |
        +-------------------------+--------------+-----+-----+-----+-----+---------+

        * Loop: 
        N/A

============================================================
+ Verbose Summary: Synthesis Manager
============================================================
InlineROM: 1
ExposeGlobal: 0
============================================================
+ Verbose Summary: CDFG Model
============================================================
IsTopModel: 1
ResetActiveHigh: 1
IsCombinational: 2
IsDatapathOnly: 0
HasWiredReturn: 1
HasMFsm: 0
HasVarLatency: 1
IsPipeline: 0
IsRtlPipelined: 0
IsInstanceOverlapped: 0
IsDontTouch: 0
HasImplIP: 0
IsGatedGlobalClock: 0


============================================================
+ Verbose Summary: Schedule
============================================================
* Number of FSM states : 6
* Pipeline : 0
* Dataflow Pipeline: 1
  DF-Pipeline-0: Size = 6, States = { 1 2 3 4 5 6 }

* FSM state transitions: 
1 --> 
	2  / true
2 --> 
	3  / true
3 --> 
	4  / true
4 --> 
	5  / true
5 --> 
	6  / true
6 --> 

* FSM state operations: 

 <State 1> : 4.63ns
ST_1 : Operation 7 [1/1] (1.00ns)   --->   "%out_array_offset_rea = call i32 @_ssdm_op_Read.s_axilite.i32(i32 %out_array_offset)"   --->   Core 10 's_axilite' <Latency = 0> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write'>
ST_1 : Operation 8 [1/1] (1.00ns)   --->   "%in_array_offset_read = call i32 @_ssdm_op_Read.s_axilite.i32(i32 %in_array_offset)"   --->   Core 10 's_axilite' <Latency = 0> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write'>
ST_1 : Operation 9 [1/1] (0.00ns)   --->   "%out_array_offset_c = alloca i32, align 4"   --->   Core 32 'FIFO' <Latency = 0> <II = 1> <Delay = 3.63> <Storage> <Opcode : 'read' 'write' 'nbread' 'nbwrite'> <Ports = 0> <Width = 32> <Depth = 2> <FIFO>
ST_1 : Operation 10 [1/1] (0.00ns)   --->   "%in_stream_V = alloca float, align 4" [edge_detection/edge_detection.cpp:107]   --->   Core 32 'FIFO' <Latency = 0> <II = 1> <Delay = 3.63> <Storage> <Opcode : 'read' 'write' 'nbread' 'nbwrite'> <Ports = 0> <Width = 32> <Depth = 2> <FIFO>
ST_1 : Operation 11 [1/1] (0.00ns)   --->   "%out_stream_V = alloca float, align 4" [edge_detection/edge_detection.cpp:108]   --->   Core 32 'FIFO' <Latency = 0> <II = 1> <Delay = 3.63> <Storage> <Opcode : 'read' 'write' 'nbread' 'nbwrite'> <Ports = 0> <Width = 32> <Depth = 2> <FIFO>
ST_1 : Operation 12 [2/2] (3.63ns)   --->   "call fastcc void @read_pixel13(float* %in_stream_V, float* %in_array, i32 %in_array_offset_read, i32 %out_array_offset_rea, i32* %out_array_offset_c)"   --->   Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >

 <State 2> : 0.00ns
ST_2 : Operation 13 [1/2] (0.00ns)   --->   "call fastcc void @read_pixel13(float* %in_stream_V, float* %in_array, i32 %in_array_offset_read, i32 %out_array_offset_rea, i32* %out_array_offset_c)"   --->   Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >

 <State 3> : 0.00ns
ST_3 : Operation 14 [2/2] (0.00ns)   --->   "call fastcc void @convolve(float* %in_stream_V, float* %out_stream_V) nounwind" [edge_detection/edge_detection.cpp:110]   --->   Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >

 <State 4> : 0.00ns
ST_4 : Operation 15 [1/2] (0.00ns)   --->   "call fastcc void @convolve(float* %in_stream_V, float* %out_stream_V) nounwind" [edge_detection/edge_detection.cpp:110]   --->   Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >

 <State 5> : 0.00ns
ST_5 : Operation 16 [2/2] (0.00ns)   --->   "call fastcc void @write_pixel(float* %out_stream_V, float* %out_array, i32* nocapture %out_array_offset_c)" [edge_detection/edge_detection.cpp:111]   --->   Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >

 <State 6> : 0.00ns
ST_6 : Operation 17 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecBitsMap(float* %out_array), !map !47"
ST_6 : Operation 18 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecBitsMap(float* %in_array), !map !53"
ST_6 : Operation 19 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecDataflowPipeline(i32 -1, [1 x i8]* @p_str1) nounwind" [edge_detection/edge_detection.cpp:107]
ST_6 : Operation 20 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecTopModule([12 x i8]* @conv_stream_str) nounwind"
ST_6 : Operation 21 [1/1] (0.00ns)   --->   "%empty = call i32 (...)* @_ssdm_op_SpecChannel([12 x i8]* @in_stream_OC_V_str, i32 1, [1 x i8]* @p_str36, [1 x i8]* @p_str36, i32 32, i32 32, float* %in_stream_V, float* %in_stream_V) nounwind"
ST_6 : Operation 22 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(float* %in_stream_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str37, i32 0, i32 0, [1 x i8]* @p_str38, [1 x i8]* @p_str39, [1 x i8]* @p_str40, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str41, [1 x i8]* @p_str42)"
ST_6 : Operation 23 [1/1] (0.00ns)   --->   "%empty_12 = call i32 (...)* @_ssdm_op_SpecChannel([13 x i8]* @out_stream_OC_V_str, i32 1, [1 x i8]* @p_str43, [1 x i8]* @p_str43, i32 32, i32 32, float* %out_stream_V, float* %out_stream_V) nounwind"
ST_6 : Operation 24 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(float* %out_stream_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str44, i32 0, i32 0, [1 x i8]* @p_str45, [1 x i8]* @p_str46, [1 x i8]* @p_str47, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str48, [1 x i8]* @p_str49)"
ST_6 : Operation 25 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(float* %out_array, [6 x i8]* @p_str6, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 400, [10 x i8]* @p_str7, [6 x i8]* @p_str8, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)"
ST_6 : Operation 26 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(i32 %out_array_offset, [10 x i8]* @mode7, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 400, [1 x i8]* @bundle8, [6 x i8]* @p_str8, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)"
ST_6 : Operation 27 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(float* %in_array, [6 x i8]* @p_str6, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 400, [9 x i8]* @p_str9, [6 x i8]* @p_str8, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)"
ST_6 : Operation 28 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(i32 %in_array_offset, [10 x i8]* @mode, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 400, [1 x i8]* @bundle, [6 x i8]* @p_str8, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)"
ST_6 : Operation 29 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(i32 0, [10 x i8]* @p_str10, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1, [1 x i8]* @p_str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1) nounwind" [edge_detection/edge_detection.cpp:107]
ST_6 : Operation 30 [1/1] (0.00ns)   --->   "%empty_13 = call i32 (...)* @_ssdm_op_SpecChannel([19 x i8]* @out_array_offset_c_s, i32 1, [1 x i8]* @p_str21, [1 x i8]* @p_str21, i32 2, i32 0, i32* %out_array_offset_c, i32* %out_array_offset_c)"
ST_6 : Operation 31 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(i32* %out_array_offset_c, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str22, i32 0, i32 0, [1 x i8]* @p_str23, [1 x i8]* @p_str24, [1 x i8]* @p_str25, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str26, [1 x i8]* @p_str27)"
ST_6 : Operation 32 [1/2] (0.00ns)   --->   "call fastcc void @write_pixel(float* %out_stream_V, float* %out_array, i32* nocapture %out_array_offset_c)" [edge_detection/edge_detection.cpp:111]   --->   Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >
ST_6 : Operation 33 [1/1] (0.00ns)   --->   "ret void" [edge_detection/edge_detection.cpp:112]


============================================================
+ Verbose Summary: Binding
============================================================
STG Binding: 
---------------- STG Properties BEGIN ----------------
- Is combinational: 0
- Is one-state seq: 0
- Is datapath-only: 0
- Is pipelined: 0
- Is top level: 1
Port [ Return ] is wired: 1; IO mode=ap_ctrl_hs:ce=0
Port [ in_array]:  wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=4; pingpong=0; private_global=0; IO mode=m_axi:ce=0
Port [ out_array]:  wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=1; type=4; pingpong=0; private_global=0; IO mode=m_axi:ce=0
Port [ in_array_offset]:  wired=1; compound=0; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=0; pingpong=0; private_global=0; IO mode=ap_none:ce=0
Port [ out_array_offset]:  wired=1; compound=0; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=0; pingpong=0; private_global=0; IO mode=ap_none:ce=0
---------------- STG Properties END ------------------

---------------- Datapath Model BEGIN ----------------

<LifeTime>
<method=bitvector/>
out_array_offset_rea (read                ) [ 0010000]
in_array_offset_read (read                ) [ 0010000]
out_array_offset_c   (alloca              ) [ 0111111]
in_stream_V          (alloca              ) [ 0111111]
out_stream_V         (alloca              ) [ 0011111]
StgValue_13          (call                ) [ 0000000]
StgValue_15          (call                ) [ 0000000]
StgValue_17          (specbitsmap         ) [ 0000000]
StgValue_18          (specbitsmap         ) [ 0000000]
StgValue_19          (specdataflowpipeline) [ 0000000]
StgValue_20          (spectopmodule       ) [ 0000000]
empty                (specchannel         ) [ 0000000]
StgValue_22          (specinterface       ) [ 0000000]
empty_12             (specchannel         ) [ 0000000]
StgValue_24          (specinterface       ) [ 0000000]
StgValue_25          (specinterface       ) [ 0000000]
StgValue_26          (specinterface       ) [ 0000000]
StgValue_27          (specinterface       ) [ 0000000]
StgValue_28          (specinterface       ) [ 0000000]
StgValue_29          (specinterface       ) [ 0000000]
empty_13             (specchannel         ) [ 0000000]
StgValue_31          (specinterface       ) [ 0000000]
StgValue_32          (call                ) [ 0000000]
StgValue_33          (ret                 ) [ 0000000]
</LifeTime>

<model>

<comp_list>
<comp id="0" class="1000" name="in_array">
<pin_list>
<pin id="1" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="in_array"/></StgValue>
</bind>
</comp>

<comp id="2" class="1000" name="out_array">
<pin_list>
<pin id="3" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="out_array"/></StgValue>
</bind>
</comp>

<comp id="4" class="1000" name="in_array_offset">
<pin_list>
<pin id="5" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="in_array_offset"/></StgValue>
</bind>
</comp>

<comp id="6" class="1000" name="out_array_offset">
<pin_list>
<pin id="7" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="out_array_offset"/></StgValue>
</bind>
</comp>

<comp id="8" class="1001" name="const_8">
<pin_list>
<pin id="9" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_Read.s_axilite.i32"/></StgValue>
</bind>
</comp>

<comp id="10" class="1001" name="const_10">
<pin_list>
<pin id="11" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="12" class="1001" name="const_12">
<pin_list>
<pin id="13" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="read_pixel13"/></StgValue>
</bind>
</comp>

<comp id="14" class="1001" name="const_14">
<pin_list>
<pin id="15" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="convolve"/></StgValue>
</bind>
</comp>

<comp id="16" class="1001" name="const_16">
<pin_list>
<pin id="17" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="write_pixel"/></StgValue>
</bind>
</comp>

<comp id="18" class="1001" name="const_18">
<pin_list>
<pin id="19" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecBitsMap"/></StgValue>
</bind>
</comp>

<comp id="20" class="1001" name="const_20">
<pin_list>
<pin id="21" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecDataflowPipeline"/></StgValue>
</bind>
</comp>

<comp id="22" class="1001" name="const_22">
<pin_list>
<pin id="23" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="24" class="1001" name="const_24">
<pin_list>
<pin id="25" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str1"/></StgValue>
</bind>
</comp>

<comp id="26" class="1001" name="const_26">
<pin_list>
<pin id="27" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecTopModule"/></StgValue>
</bind>
</comp>

<comp id="28" class="1001" name="const_28">
<pin_list>
<pin id="29" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="conv_stream_str"/></StgValue>
</bind>
</comp>

<comp id="30" class="1001" name="const_30">
<pin_list>
<pin id="31" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecChannel"/></StgValue>
</bind>
</comp>

<comp id="32" class="1001" name="const_32">
<pin_list>
<pin id="33" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="in_stream_OC_V_str"/></StgValue>
</bind>
</comp>

<comp id="34" class="1001" name="const_34">
<pin_list>
<pin id="35" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="36" class="1001" name="const_36">
<pin_list>
<pin id="37" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str36"/></StgValue>
</bind>
</comp>

<comp id="38" class="1001" name="const_38">
<pin_list>
<pin id="39" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="40" class="1001" name="const_40">
<pin_list>
<pin id="41" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecInterface"/></StgValue>
</bind>
</comp>

<comp id="42" class="1001" name="const_42">
<pin_list>
<pin id="43" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="ap_fifo_str"/></StgValue>
</bind>
</comp>

<comp id="44" class="1001" name="const_44">
<pin_list>
<pin id="45" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="46" class="1001" name="const_46">
<pin_list>
<pin id="47" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str37"/></StgValue>
</bind>
</comp>

<comp id="48" class="1001" name="const_48">
<pin_list>
<pin id="49" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str38"/></StgValue>
</bind>
</comp>

<comp id="50" class="1001" name="const_50">
<pin_list>
<pin id="51" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str39"/></StgValue>
</bind>
</comp>

<comp id="52" class="1001" name="const_52">
<pin_list>
<pin id="53" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str40"/></StgValue>
</bind>
</comp>

<comp id="54" class="1001" name="const_54">
<pin_list>
<pin id="55" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="56" class="1001" name="const_56">
<pin_list>
<pin id="57" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="58" class="1001" name="const_58">
<pin_list>
<pin id="59" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str41"/></StgValue>
</bind>
</comp>

<comp id="60" class="1001" name="const_60">
<pin_list>
<pin id="61" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str42"/></StgValue>
</bind>
</comp>

<comp id="62" class="1001" name="const_62">
<pin_list>
<pin id="63" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="out_stream_OC_V_str"/></StgValue>
</bind>
</comp>

<comp id="64" class="1001" name="const_64">
<pin_list>
<pin id="65" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str43"/></StgValue>
</bind>
</comp>

<comp id="66" class="1001" name="const_66">
<pin_list>
<pin id="67" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str44"/></StgValue>
</bind>
</comp>

<comp id="68" class="1001" name="const_68">
<pin_list>
<pin id="69" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str45"/></StgValue>
</bind>
</comp>

<comp id="70" class="1001" name="const_70">
<pin_list>
<pin id="71" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str46"/></StgValue>
</bind>
</comp>

<comp id="72" class="1001" name="const_72">
<pin_list>
<pin id="73" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str47"/></StgValue>
</bind>
</comp>

<comp id="74" class="1001" name="const_74">
<pin_list>
<pin id="75" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str48"/></StgValue>
</bind>
</comp>

<comp id="76" class="1001" name="const_76">
<pin_list>
<pin id="77" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str49"/></StgValue>
</bind>
</comp>

<comp id="78" class="1001" name="const_78">
<pin_list>
<pin id="79" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str6"/></StgValue>
</bind>
</comp>

<comp id="80" class="1001" name="const_80">
<pin_list>
<pin id="81" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="82" class="1001" name="const_82">
<pin_list>
<pin id="83" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str7"/></StgValue>
</bind>
</comp>

<comp id="84" class="1001" name="const_84">
<pin_list>
<pin id="85" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str8"/></StgValue>
</bind>
</comp>

<comp id="86" class="1001" name="const_86">
<pin_list>
<pin id="87" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="mode7"/></StgValue>
</bind>
</comp>

<comp id="88" class="1001" name="const_88">
<pin_list>
<pin id="89" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="bundle8"/></StgValue>
</bind>
</comp>

<comp id="90" class="1001" name="const_90">
<pin_list>
<pin id="91" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str9"/></StgValue>
</bind>
</comp>

<comp id="92" class="1001" name="const_92">
<pin_list>
<pin id="93" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="mode"/></StgValue>
</bind>
</comp>

<comp id="94" class="1001" name="const_94">
<pin_list>
<pin id="95" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="bundle"/></StgValue>
</bind>
</comp>

<comp id="96" class="1001" name="const_96">
<pin_list>
<pin id="97" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str10"/></StgValue>
</bind>
</comp>

<comp id="98" class="1001" name="const_98">
<pin_list>
<pin id="99" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="out_array_offset_c_s"/></StgValue>
</bind>
</comp>

<comp id="100" class="1001" name="const_100">
<pin_list>
<pin id="101" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str21"/></StgValue>
</bind>
</comp>

<comp id="102" class="1001" name="const_102">
<pin_list>
<pin id="103" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str22"/></StgValue>
</bind>
</comp>

<comp id="104" class="1001" name="const_104">
<pin_list>
<pin id="105" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str23"/></StgValue>
</bind>
</comp>

<comp id="106" class="1001" name="const_106">
<pin_list>
<pin id="107" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str24"/></StgValue>
</bind>
</comp>

<comp id="108" class="1001" name="const_108">
<pin_list>
<pin id="109" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str25"/></StgValue>
</bind>
</comp>

<comp id="110" class="1001" name="const_110">
<pin_list>
<pin id="111" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str26"/></StgValue>
</bind>
</comp>

<comp id="112" class="1001" name="const_112">
<pin_list>
<pin id="113" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str27"/></StgValue>
</bind>
</comp>

<comp id="114" class="1004" name="out_array_offset_c_fu_114">
<pin_list>
<pin id="115" dir="0" index="0" bw="1" slack="0"/>
<pin id="116" dir="1" index="1" bw="32" slack="0"/>
</pin_list>
<bind>
<opcode="alloca(26) " fcode="alloca"/>
<opset="out_array_offset_c/1 "/>
</bind>
</comp>

<comp id="118" class="1004" name="in_stream_V_fu_118">
<pin_list>
<pin id="119" dir="0" index="0" bw="1" slack="0"/>
<pin id="120" dir="1" index="1" bw="32" slack="0"/>
</pin_list>
<bind>
<opcode="alloca(26) " fcode="alloca"/>
<opset="in_stream_V/1 "/>
</bind>
</comp>

<comp id="122" class="1004" name="out_stream_V_fu_122">
<pin_list>
<pin id="123" dir="0" index="0" bw="1" slack="0"/>
<pin id="124" dir="1" index="1" bw="32" slack="2"/>
</pin_list>
<bind>
<opcode="alloca(26) " fcode="alloca"/>
<opset="out_stream_V/1 "/>
</bind>
</comp>

<comp id="126" class="1004" name="out_array_offset_rea_read_fu_126">
<pin_list>
<pin id="127" dir="0" index="0" bw="32" slack="0"/>
<pin id="128" dir="0" index="1" bw="32" slack="0"/>
<pin id="129" dir="1" index="2" bw="32" slack="0"/>
</pin_list>
<bind>
<opcode="read(1150) " fcode="read"/>
<opset="out_array_offset_rea/1 "/>
</bind>
</comp>

<comp id="132" class="1004" name="in_array_offset_read_read_fu_132">
<pin_list>
<pin id="133" dir="0" index="0" bw="32" slack="0"/>
<pin id="134" dir="0" index="1" bw="32" slack="0"/>
<pin id="135" dir="1" index="2" bw="32" slack="0"/>
</pin_list>
<bind>
<opcode="read(1150) " fcode="read"/>
<opset="in_array_offset_read/1 "/>
</bind>
</comp>

<comp id="138" class="1004" name="grp_convolve_fu_138">
<pin_list>
<pin id="139" dir="0" index="0" bw="0" slack="0"/>
<pin id="140" dir="0" index="1" bw="32" slack="2"/>
<pin id="141" dir="0" index="2" bw="32" slack="2"/>
<pin id="142" dir="1" index="3" bw="0" slack="2147483647"/>
</pin_list>
<bind>
<opcode="call(48) " fcode="call"/>
<opset="StgValue_14/3 "/>
</bind>
</comp>

<comp id="144" class="1004" name="grp_write_pixel_fu_144">
<pin_list>
<pin id="145" dir="0" index="0" bw="0" slack="0"/>
<pin id="146" dir="0" index="1" bw="32" slack="4"/>
<pin id="147" dir="0" index="2" bw="32" slack="0"/>
<pin id="148" dir="0" index="3" bw="32" slack="4"/>
<pin id="149" dir="1" index="4" bw="0" slack="2147483647"/>
</pin_list>
<bind>
<opcode="call(48) " fcode="call"/>
<opset="StgValue_16/5 "/>
</bind>
</comp>

<comp id="152" class="1004" name="grp_read_pixel13_fu_152">
<pin_list>
<pin id="153" dir="0" index="0" bw="0" slack="0"/>
<pin id="154" dir="0" index="1" bw="32" slack="0"/>
<pin id="155" dir="0" index="2" bw="32" slack="0"/>
<pin id="156" dir="0" index="3" bw="32" slack="0"/>
<pin id="157" dir="0" index="4" bw="32" slack="0"/>
<pin id="158" dir="0" index="5" bw="32" slack="0"/>
<pin id="159" dir="1" index="6" bw="0" slack="2147483647"/>
</pin_list>
<bind>
<opcode="call(48) " fcode="call"/>
<opset="StgValue_12/1 "/>
</bind>
</comp>

<comp id="164" class="1005" name="out_array_offset_rea_reg_164">
<pin_list>
<pin id="165" dir="0" index="0" bw="32" slack="1"/>
<pin id="166" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="out_array_offset_rea "/>
</bind>
</comp>

<comp id="169" class="1005" name="in_array_offset_read_reg_169">
<pin_list>
<pin id="170" dir="0" index="0" bw="32" slack="1"/>
<pin id="171" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="in_array_offset_read "/>
</bind>
</comp>

<comp id="174" class="1005" name="out_array_offset_c_reg_174">
<pin_list>
<pin id="175" dir="0" index="0" bw="32" slack="0"/>
<pin id="176" dir="1" index="1" bw="32" slack="0"/>
</pin_list>
<bind>
<opset="out_array_offset_c "/>
</bind>
</comp>

<comp id="180" class="1005" name="in_stream_V_reg_180">
<pin_list>
<pin id="181" dir="0" index="0" bw="32" slack="0"/>
<pin id="182" dir="1" index="1" bw="32" slack="0"/>
</pin_list>
<bind>
<opset="in_stream_V "/>
</bind>
</comp>

<comp id="186" class="1005" name="out_stream_V_reg_186">
<pin_list>
<pin id="187" dir="0" index="0" bw="32" slack="2"/>
<pin id="188" dir="1" index="1" bw="32" slack="2"/>
</pin_list>
<bind>
<opset="out_stream_V "/>
</bind>
</comp>

</comp_list>

<net_list>
<net id="117"><net_src comp="10" pin="0"/><net_sink comp="114" pin=0"/></net>

<net id="121"><net_src comp="10" pin="0"/><net_sink comp="118" pin=0"/></net>

<net id="125"><net_src comp="10" pin="0"/><net_sink comp="122" pin=0"/></net>

<net id="130"><net_src comp="8" pin="0"/><net_sink comp="126" pin=0"/></net>

<net id="131"><net_src comp="6" pin="0"/><net_sink comp="126" pin=1"/></net>

<net id="136"><net_src comp="8" pin="0"/><net_sink comp="132" pin=0"/></net>

<net id="137"><net_src comp="4" pin="0"/><net_sink comp="132" pin=1"/></net>

<net id="143"><net_src comp="14" pin="0"/><net_sink comp="138" pin=0"/></net>

<net id="150"><net_src comp="16" pin="0"/><net_sink comp="144" pin=0"/></net>

<net id="151"><net_src comp="2" pin="0"/><net_sink comp="144" pin=2"/></net>

<net id="160"><net_src comp="12" pin="0"/><net_sink comp="152" pin=0"/></net>

<net id="161"><net_src comp="0" pin="0"/><net_sink comp="152" pin=2"/></net>

<net id="162"><net_src comp="132" pin="2"/><net_sink comp="152" pin=3"/></net>

<net id="163"><net_src comp="126" pin="2"/><net_sink comp="152" pin=4"/></net>

<net id="167"><net_src comp="126" pin="2"/><net_sink comp="164" pin=0"/></net>

<net id="168"><net_src comp="164" pin="1"/><net_sink comp="152" pin=4"/></net>

<net id="172"><net_src comp="132" pin="2"/><net_sink comp="169" pin=0"/></net>

<net id="173"><net_src comp="169" pin="1"/><net_sink comp="152" pin=3"/></net>

<net id="177"><net_src comp="114" pin="1"/><net_sink comp="174" pin=0"/></net>

<net id="178"><net_src comp="174" pin="1"/><net_sink comp="152" pin=5"/></net>

<net id="179"><net_src comp="174" pin="1"/><net_sink comp="144" pin=3"/></net>

<net id="183"><net_src comp="118" pin="1"/><net_sink comp="180" pin=0"/></net>

<net id="184"><net_src comp="180" pin="1"/><net_sink comp="152" pin=1"/></net>

<net id="185"><net_src comp="180" pin="1"/><net_sink comp="138" pin=1"/></net>

<net id="189"><net_src comp="122" pin="1"/><net_sink comp="186" pin=0"/></net>

<net id="190"><net_src comp="186" pin="1"/><net_sink comp="138" pin=2"/></net>

<net id="191"><net_src comp="186" pin="1"/><net_sink comp="144" pin=1"/></net>

</net_list>

</model> 
---------------- Datapath Model END ------------------

* FSMD analyzer results:
  - Output states:
	Port: out_array | {5 6 }
 - Input state : 
	Port: conv_stream : in_array | {1 2 }
	Port: conv_stream : in_array_offset | {1 }
	Port: conv_stream : out_array_offset | {1 }
  - Chain level:
	State 1
		StgValue_12 : 1
	State 2
	State 3
	State 4
	State 5
	State 6


============================================================
+ Verbose Summary: Datapath Resource usage 
============================================================

* Functional unit list:
|----------|----------------------------------|---------|---------|---------|---------|---------|
| Operation|          Functional Unit         |   BRAM  |  DSP48E |  Delay  |    FF   |   LUT   |
|----------|----------------------------------|---------|---------|---------|---------|---------|
|          |        grp_convolve_fu_138       |    0    |    33   |  5.307  |   3666  |   5279  |
|   call   |      grp_write_pixel_fu_144      |    0    |    0    |  3.538  |   113   |    38   |
|          |      grp_read_pixel13_fu_152     |    0    |    0    |  1.769  |    83   |    38   |
|----------|----------------------------------|---------|---------|---------|---------|---------|
|   read   | out_array_offset_rea_read_fu_126 |    0    |    0    |    0    |    0    |    0    |
|          | in_array_offset_read_read_fu_132 |    0    |    0    |    0    |    0    |    0    |
|----------|----------------------------------|---------|---------|---------|---------|---------|
|   Total  |                                  |    0    |    33   |  10.614 |   3862  |   5355  |
|----------|----------------------------------|---------|---------|---------|---------|---------|

Memories:
N/A

* Register list:
+----------------------------+--------+
|                            |   FF   |
+----------------------------+--------+
|in_array_offset_read_reg_169|   32   |
|     in_stream_V_reg_180    |   32   |
| out_array_offset_c_reg_174 |   32   |
|out_array_offset_rea_reg_164|   32   |
|    out_stream_V_reg_186    |   32   |
+----------------------------+--------+
|            Total           |   160  |
+----------------------------+--------+

* Multiplexer (MUX) list: 
|-------------------------|------|------|------|--------||---------||---------|
|           Comp          |  Pin | Size |  BW  | S x BW ||  Delay  ||   LUT   |
|-------------------------|------|------|------|--------||---------||---------|
| grp_read_pixel13_fu_152 |  p3  |   2  |  32  |   64   ||    9    |
| grp_read_pixel13_fu_152 |  p4  |   2  |  32  |   64   ||    9    |
|-------------------------|------|------|------|--------||---------||---------|
|          Total          |      |      |      |   128  ||  3.538  ||    18   |
|-------------------------|------|------|------|--------||---------||---------|



* Summary:
+-----------+--------+--------+--------+--------+--------+
|           |  BRAM  | DSP48E |  Delay |   FF   |   LUT  |
+-----------+--------+--------+--------+--------+--------+
|  Function |    0   |   33   |   10   |  3862  |  5355  |
|   Memory  |    -   |    -   |    -   |    -   |    -   |
|Multiplexer|    -   |    -   |    3   |    -   |   18   |
|  Register |    -   |    -   |    -   |   160  |    -   |
+-----------+--------+--------+--------+--------+--------+
|   Total   |    0   |   33   |   14   |  4022  |  5373  |
+-----------+--------+--------+--------+--------+--------+