================================================================
== Vivado HLS Report for 'move_data'
================================================================
* Date:           Tue May 29 19:06:49 2018

* Version:        2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017)
* Project:        edge_detection
* Solution:       axi_port_only
* Product family: zynq
* Target device:  xc7z020clg484-1


================================================================
== Performance Estimates
================================================================
+ Timing (ns): 
    * Summary: 
    +--------+-------+----------+------------+
    |  Clock | Target| Estimated| Uncertainty|
    +--------+-------+----------+------------+
    |ap_clk  |  10.00|      4.64|        1.25|
    +--------+-------+----------+------------+

+ Latency (clock cycles): 
    * Summary: 
    +-----+-----+-----+-----+----------+
    |  Latency  |  Interval | Pipeline |
    | min | max | min | max |   Type   |
    +-----+-----+-----+-----+----------+
    |    7|    7|    8|    8| function |
    +-----+-----+-----+-----+----------+

    + Detail: 
        * Instance: 
        N/A

        * Loop: 
        N/A



================================================================
== Utilization Estimates
================================================================
* Summary: 
+-----------------+---------+-------+--------+-------+
|       Name      | BRAM_18K| DSP48E|   FF   |  LUT  |
+-----------------+---------+-------+--------+-------+
|DSP              |        -|      -|       -|      -|
|Expression       |        -|      -|       -|      -|
|FIFO             |        -|      -|       -|      -|
|Instance         |        -|      -|       -|      -|
|Memory           |        -|      -|       -|      -|
|Multiplexer      |        -|      -|       -|    207|
|Register         |        -|      -|     184|      -|
+-----------------+---------+-------+--------+-------+
|Total            |        0|      0|     184|    207|
+-----------------+---------+-------+--------+-------+
|Available        |      280|    220|  106400|  53200|
+-----------------+---------+-------+--------+-------+
|Utilization (%)  |        0|      0|   ~0   |   ~0  |
+-----------------+---------+-------+--------+-------+

+ Detail: 
    * Instance: 
    N/A

    * DSP48: 
    N/A

    * Memory: 
    N/A

    * FIFO: 
    N/A

    * Expression: 
    N/A

    * Multiplexer: 
    +-----------------------+----+-----------+-----+-----------+
    |          Name         | LUT| Input Size| Bits| Total Bits|
    +-----------------------+----+-----------+-----+-----------+
    |ap_NS_fsm              |  44|          9|    1|          9|
    |crop_address0          |  44|          9|    4|         36|
    |crop_address1          |  41|          8|    4|         32|
    |crop_d0                |  27|          5|   32|        160|
    |crop_d1                |  21|          4|   32|        128|
    |temp_array_0_address0  |  15|          3|    5|         15|
    |temp_array_1_address0  |  15|          3|    5|         15|
    +-----------------------+----+-----------+-----+-----------+
    |Total                  | 207|         41|   83|        395|
    +-----------------------+----+-----------+-----+-----------+

    * Register: 
    +---------------------------+----+----+-----+-----------+
    |            Name           | FF | LUT| Bits| Const Bits|
    +---------------------------+----+----+-----+-----------+
    |ap_CS_fsm                  |   8|   0|    8|          0|
    |ap_port_reg_new_data       |  32|   0|   32|          0|
    |ap_port_reg_pos_y          |   6|   0|    6|          0|
    |crop_load_2_reg_212        |  32|   0|   32|          0|
    |crop_load_3_reg_217        |  32|   0|   32|          0|
    |reg_161                    |  32|   0|   32|          0|
    |reg_166                    |  32|   0|   32|          0|
    |temp_array_0_addr_reg_222  |   5|   0|    5|          0|
    |temp_array_1_addr_reg_227  |   5|   0|    5|          0|
    +---------------------------+----+----+-----+-----------+
    |Total                      | 184|   0|  184|          0|
    +---------------------------+----+----+-----+-----------+



================================================================
== Interface
================================================================
* Summary: 
+-----------------------+-----+-----+------------+--------------+--------------+
|       RTL Ports       | Dir | Bits|  Protocol  | Source Object|    C Type    |
+-----------------------+-----+-----+------------+--------------+--------------+
|ap_clk                 |  in |    1| ap_ctrl_hs |   move_data  | return value |
|ap_rst                 |  in |    1| ap_ctrl_hs |   move_data  | return value |
|ap_start               |  in |    1| ap_ctrl_hs |   move_data  | return value |
|ap_done                | out |    1| ap_ctrl_hs |   move_data  | return value |
|ap_idle                | out |    1| ap_ctrl_hs |   move_data  | return value |
|ap_ready               | out |    1| ap_ctrl_hs |   move_data  | return value |
|ap_ce                  |  in |    1| ap_ctrl_hs |   move_data  | return value |
|new_data               |  in |   32|   ap_none  |   new_data   |    scalar    |
|temp_array_0_address0  | out |    5|  ap_memory | temp_array_0 |     array    |
|temp_array_0_ce0       | out |    1|  ap_memory | temp_array_0 |     array    |
|temp_array_0_we0       | out |    1|  ap_memory | temp_array_0 |     array    |
|temp_array_0_d0        | out |   32|  ap_memory | temp_array_0 |     array    |
|temp_array_0_q0        |  in |   32|  ap_memory | temp_array_0 |     array    |
|temp_array_1_address0  | out |    5|  ap_memory | temp_array_1 |     array    |
|temp_array_1_ce0       | out |    1|  ap_memory | temp_array_1 |     array    |
|temp_array_1_we0       | out |    1|  ap_memory | temp_array_1 |     array    |
|temp_array_1_d0        | out |   32|  ap_memory | temp_array_1 |     array    |
|temp_array_1_q0        |  in |   32|  ap_memory | temp_array_1 |     array    |
|crop_address0          | out |    4|  ap_memory |     crop     |     array    |
|crop_ce0               | out |    1|  ap_memory |     crop     |     array    |
|crop_we0               | out |    1|  ap_memory |     crop     |     array    |
|crop_d0                | out |   32|  ap_memory |     crop     |     array    |
|crop_q0                |  in |   32|  ap_memory |     crop     |     array    |
|crop_address1          | out |    4|  ap_memory |     crop     |     array    |
|crop_ce1               | out |    1|  ap_memory |     crop     |     array    |
|crop_we1               | out |    1|  ap_memory |     crop     |     array    |
|crop_d1                | out |   32|  ap_memory |     crop     |     array    |
|crop_q1                |  in |   32|  ap_memory |     crop     |     array    |
|pos_y                  |  in |    6|   ap_none  |     pos_y    |    scalar    |
+-----------------------+-----+-----+------------+--------------+--------------+