================================================================ == Vivado HLS Report for 'convolve' ================================================================ * Date: Wed May 30 11:44:03 2018 * Version: 2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017) * Project: edge_detection * Solution: axi_port_only * Product family: zynq * Target device: xc7z020clg484-1 ================================================================ == Performance Estimates ================================================================ + Timing (ns): * Summary: +--------+-------+----------+------------+ | Clock | Target| Estimated| Uncertainty| +--------+-------+----------+------------+ |ap_clk | 10.00| 7.26| 1.25| +--------+-------+----------+------------+ + Latency (clock cycles): * Summary: +-----+-----+-----+-----+---------+ | Latency | Interval | Pipeline| | min | max | min | max | Type | +-----+-----+-----+-----+---------+ | 451| 451| 451| 451| none | +-----+-----+-----+-----+---------+ + Detail: * Instance: N/A * Loop: +-----------------------+-----+-----+----------+-----------+-----------+------+----------+ | | Latency | Iteration| Initiation Interval | Trip | | | Loop Name | min | max | Latency | achieved | target | Count| Pipelined| +-----------------------+-----+-----+----------+-----------+-----------+------+----------+ |- conv_rows_conv_cols | 449| 449| 51| 1| 1| 400| yes | +-----------------------+-----+-----+----------+-----------+-----------+------+----------+ ================================================================ == Utilization Estimates ================================================================ * Summary: +-----------------+---------+-------+--------+-------+ | Name | BRAM_18K| DSP48E| FF | LUT | +-----------------+---------+-------+--------+-------+ |DSP | -| -| -| -| |Expression | -| -| 0| 157| |FIFO | -| -| -| -| |Instance | -| 33| 2560| 5115| |Memory | 0| -| 128| 20| |Multiplexer | -| -| -| 93| |Register | 0| -| 1622| 448| +-----------------+---------+-------+--------+-------+ |Total | 0| 33| 4310| 5833| +-----------------+---------+-------+--------+-------+ |Available | 280| 220| 106400| 53200| +-----------------+---------+-------+--------+-------+ |Utilization (%) | 0| 15| 4| 10| +-----------------+---------+-------+--------+-------+ + Detail: * Instance: +--------------------------+----------------------+---------+-------+-----+-----+ | Instance | Module | BRAM_18K| DSP48E| FF | LUT | +--------------------------+----------------------+---------+-------+-----+-----+ |conv_stream_fadd_dEe_U6 |conv_stream_fadd_dEe | 0| 2| 205| 390| |conv_stream_fadd_dEe_U7 |conv_stream_fadd_dEe | 0| 2| 205| 390| |conv_stream_fadd_dEe_U8 |conv_stream_fadd_dEe | 0| 2| 205| 390| |conv_stream_fadd_dEe_U9 |conv_stream_fadd_dEe | 0| 2| 205| 390| |conv_stream_fadd_dEe_U10 |conv_stream_fadd_dEe | 0| 2| 205| 390| |conv_stream_fadd_dEe_U11 |conv_stream_fadd_dEe | 0| 2| 205| 390| |conv_stream_fadd_dEe_U12 |conv_stream_fadd_dEe | 0| 2| 205| 390| |conv_stream_fadd_dEe_U13 |conv_stream_fadd_dEe | 0| 2| 205| 390| |conv_stream_fadd_dEe_U14 |conv_stream_fadd_dEe | 0| 2| 205| 390| |conv_stream_fmul_eOg_U15 |conv_stream_fmul_eOg | 0| 3| 143| 321| |conv_stream_fmul_eOg_U16 |conv_stream_fmul_eOg | 0| 3| 143| 321| |conv_stream_fmul_eOg_U17 |conv_stream_fmul_eOg | 0| 3| 143| 321| |conv_stream_fmul_eOg_U18 |conv_stream_fmul_eOg | 0| 3| 143| 321| |conv_stream_fmul_eOg_U19 |conv_stream_fmul_eOg | 0| 3| 143| 321| +--------------------------+----------------------+---------+-------+-----+-----+ |Total | | 0| 33| 2560| 5115| +--------------------------+----------------------+---------+-------+-----+-----+ * DSP48: N/A * Memory: +-----------------------+----------------------+---------+----+----+------+-----+------+-------------+ | Memory | Module | BRAM_18K| FF | LUT| Words| Bits| Banks| W*Bits*Banks| +-----------------------+----------------------+---------+----+----+------+-----+------+-------------+ |temp_array_0_assign_U |convolve_temp_arrbkb | 0| 64| 10| 20| 32| 1| 640| |temp_array_1_assign_U |convolve_temp_arrbkb | 0| 64| 10| 20| 32| 1| 640| +-----------------------+----------------------+---------+----+----+------+-----+------+-------------+ |Total | | 0| 128| 20| 40| 64| 2| 1280| +-----------------------+----------------------+---------+----+----+------+-----+------+-------------+ * FIFO: N/A * Expression: +------------------------------------+----------+-------+---+----+------------+------------+ | Variable Name | Operation| DSP48E| FF| LUT| Bitwidth P0| Bitwidth P1| +------------------------------------+----------+-------+---+----+------------+------------+ |i_s_fu_286_p2 | + | 0| 0| 15| 5| 1| |indvar_flatten_next_fu_266_p2 | + | 0| 0| 16| 9| 1| |j_fu_368_p2 | + | 0| 0| 15| 5| 1| |ap_block_state3_pp0_stage0_iter1 | and | 0| 0| 8| 1| 1| |ap_block_state52_pp0_stage0_iter50 | and | 0| 0| 8| 1| 1| |or_cond_fu_362_p2 | and | 0| 0| 8| 1| 1| |exitcond_flatten_fu_260_p2 | icmp | 0| 0| 13| 9| 8| |exitcond_fu_272_p2 | icmp | 0| 0| 11| 5| 5| |icmp1_fu_318_p2 | icmp | 0| 0| 9| 4| 1| |icmp2_fu_356_p2 | icmp | 0| 0| 9| 4| 1| |icmp_fu_302_p2 | icmp | 0| 0| 9| 4| 1| |ap_block_pp0_stage0_01001 | or | 0| 0| 8| 1| 1| |ap_block_state1 | or | 0| 0| 8| 1| 1| |i_mid2_fu_332_p3 | select | 0| 0| 5| 1| 5| |pos_y_assign_mid2_fu_278_p3 | select | 0| 0| 5| 1| 1| |tmp_mid2_fu_324_p3 | select | 0| 0| 2| 1| 1| |ap_enable_pp0 | xor | 0| 0| 8| 1| 2| +------------------------------------+----------+-------+---+----+------------+------------+ |Total | | 0| 0| 157| 54| 33| +------------------------------------+----------+-------+---+----+------------+------------+ * Multiplexer: +--------------------------+----+-----------+-----+-----------+ | Name | LUT| Input Size| Bits| Total Bits| +--------------------------+----+-----------+-----+-----------+ |ap_NS_fsm | 21| 4| 1| 4| |ap_done | 9| 2| 1| 2| |ap_enable_reg_pp0_iter2 | 9| 2| 1| 2| |ap_enable_reg_pp0_iter50 | 9| 2| 1| 2| |i_reg_176 | 9| 2| 5| 10| |in_stream_V_blk_n | 9| 2| 1| 2| |indvar_flatten_reg_165 | 9| 2| 9| 18| |out_stream_V_blk_n | 9| 2| 1| 2| |pos_y_assign_reg_187 | 9| 2| 5| 10| +--------------------------+----+-----------+-----+-----------+ |Total | 93| 20| 25| 52| +--------------------------+----+-----------+-----+-----------+ * Register: +-------------------------------+----+----+-----+-----------+ | Name | FF | LUT| Bits| Const Bits| +-------------------------------+----+----+-----+-----------+ |ap_CS_fsm | 3| 0| 3| 0| |ap_done_reg | 1| 0| 1| 0| |ap_enable_reg_pp0_iter0 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter1 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter10 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter11 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter12 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter13 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter14 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter15 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter16 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter17 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter18 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter19 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter2 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter20 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter21 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter22 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter23 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter24 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter25 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter26 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter27 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter28 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter29 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter3 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter30 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter31 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter32 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter33 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter34 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter35 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter36 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter37 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter38 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter39 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter4 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter40 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter41 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter42 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter43 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter44 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter45 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter46 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter47 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter48 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter49 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter5 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter50 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter6 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter7 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter8 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter9 | 1| 0| 1| 0| |crop_0_0_fu_90 | 32| 0| 32| 0| |crop_0_1_fu_94 | 32| 0| 32| 0| |crop_0_1_load_reg_521 | 32| 0| 32| 0| |crop_0_2_reg_541 | 32| 0| 32| 0| |crop_1_0_fu_98 | 32| 0| 32| 0| |crop_1_0_load_reg_511 | 32| 0| 32| 0| |crop_1_1_fu_102 | 32| 0| 32| 0| |crop_1_1_load_reg_526 | 32| 0| 32| 0| |crop_1_2_reg_546 | 32| 0| 32| 0| |crop_2_0_fu_106 | 32| 0| 32| 0| |crop_2_0_load_reg_516 | 32| 0| 32| 0| |crop_2_1_fu_110 | 32| 0| 32| 0| |crop_2_1_load_reg_531 | 32| 0| 32| 0| |exitcond_flatten_reg_471 | 1| 0| 1| 0| |i_reg_176 | 5| 0| 5| 0| |indvar_flatten_reg_165 | 9| 0| 9| 0| |or_cond_reg_497 | 1| 0| 1| 0| |pos_y_assign_reg_187 | 5| 0| 5| 0| |result_2_0_1_i_reg_561 | 32| 0| 32| 0| |result_2_0_2_i_reg_571 | 32| 0| 32| 0| |result_2_0_i_reg_556 | 32| 0| 32| 0| |result_2_1_1_i_reg_586 | 32| 0| 32| 0| |result_2_1_2_i_reg_591 | 32| 0| 32| 0| |result_2_1_i_reg_576 | 32| 0| 32| 0| |result_2_2_1_i_reg_606 | 32| 0| 32| 0| |result_2_2_i_reg_601 | 32| 0| 32| 0| |temp_array_0_assign_1_reg_485 | 5| 0| 5| 0| |temp_array_1_assign_1_reg_491 | 5| 0| 5| 0| |tmp_4_0_2_i_reg_566 | 32| 0| 32| 0| |tmp_4_0_i_reg_551 | 32| 0| 32| 0| |tmp_4_1_1_i_reg_581 | 32| 0| 32| 0| |tmp_4_2_2_i_reg_611 | 32| 0| 32| 0| |tmp_4_2_i_reg_596 | 32| 0| 32| 0| |tmp_4_reg_616 | 32| 0| 32| 0| |tmp_5_reg_536 | 32| 0| 32| 0| |crop_0_1_load_reg_521 | 64| 32| 32| 0| |crop_0_2_reg_541 | 64| 32| 32| 0| |crop_1_0_load_reg_511 | 64| 32| 32| 0| |crop_1_1_load_reg_526 | 64| 32| 32| 0| |crop_1_2_reg_546 | 64| 32| 32| 0| |crop_2_0_load_reg_516 | 64| 32| 32| 0| |crop_2_1_load_reg_531 | 64| 64| 32| 0| |exitcond_flatten_reg_471 | 64| 64| 1| 0| |or_cond_reg_497 | 64| 64| 1| 0| |tmp_5_reg_536 | 64| 64| 32| 0| +-------------------------------+----+----+-----+-----------+ |Total |1622| 448| 1240| 0| +-------------------------------+----+----+-----+-----------+ ================================================================ == Interface ================================================================ * Summary: +---------------------+-----+-----+------------+--------------+--------------+ | RTL Ports | Dir | Bits| Protocol | Source Object| C Type | +---------------------+-----+-----+------------+--------------+--------------+ |ap_clk | in | 1| ap_ctrl_hs | convolve | return value | |ap_rst | in | 1| ap_ctrl_hs | convolve | return value | |ap_start | in | 1| ap_ctrl_hs | convolve | return value | |ap_done | out | 1| ap_ctrl_hs | convolve | return value | |ap_continue | in | 1| ap_ctrl_hs | convolve | return value | |ap_idle | out | 1| ap_ctrl_hs | convolve | return value | |ap_ready | out | 1| ap_ctrl_hs | convolve | return value | |in_stream_V_dout | in | 32| ap_fifo | in_stream_V | pointer | |in_stream_V_empty_n | in | 1| ap_fifo | in_stream_V | pointer | |in_stream_V_read | out | 1| ap_fifo | in_stream_V | pointer | |out_stream_V_din | out | 32| ap_fifo | out_stream_V | pointer | |out_stream_V_full_n | in | 1| ap_fifo | out_stream_V | pointer | |out_stream_V_write | out | 1| ap_fifo | out_stream_V | pointer | +---------------------+-----+-----+------------+--------------+--------------+