================================================================ == Vivado HLS Report for 'conv_stream' ================================================================ * Date: Wed May 30 11:44:03 2018 * Version: 2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017) * Project: edge_detection * Solution: axi_port_only * Product family: zynq * Target device: xc7z020clg484-1 ================================================================ == Performance Estimates ================================================================ + Timing (ns): * Summary: +--------+-------+----------+------------+ | Clock | Target| Estimated| Uncertainty| +--------+-------+----------+------------+ |ap_clk | 10.00| 8.75| 1.25| +--------+-------+----------+------------+ + Latency (clock cycles): * Summary: +-----+-----+-----+-----+----------+ | Latency | Interval | Pipeline | | min | max | min | max | Type | +-----+-----+-----+-----+----------+ | 465| 465| 452| 452| dataflow | +-----+-----+-----+-----+----------+ + Detail: * Instance: +-----------------+--------------+-----+-----+-----+-----+---------+ | | | Latency | Interval | Pipeline| | Instance | Module | min | max | min | max | Type | +-----------------+--------------+-----+-----+-----+-----+---------+ |convolve_U0 |convolve | 451| 451| 451| 451| none | |write_pixel_U0 |write_pixel | 332| 332| 332| 332| none | |read_pixel13_U0 |read_pixel13 | 409| 409| 409| 409| none | +-----------------+--------------+-----+-----+-----+-----+---------+ * Loop: N/A ================================================================ == Utilization Estimates ================================================================ * Summary: +-----------------+---------+-------+--------+-------+ | Name | BRAM_18K| DSP48E| FF | LUT | +-----------------+---------+-------+--------+-------+ |DSP | -| -| -| -| |Expression | -| -| 0| 16| |FIFO | 4| -| 105| 132| |Instance | 4| 33| 5591| 7611| |Memory | -| -| -| -| |Multiplexer | -| -| -| -| |Register | -| -| -| -| +-----------------+---------+-------+--------+-------+ |Total | 8| 33| 5696| 7759| +-----------------+---------+-------+--------+-------+ |Available | 280| 220| 106400| 53200| +-----------------+---------+-------+--------+-------+ |Utilization (%) | 2| 15| 5| 14| +-----------------+---------+-------+--------+-------+ + Detail: * Instance: +-------------------------------+-----------------------------+---------+-------+------+------+ | Instance | Module | BRAM_18K| DSP48E| FF | LUT | +-------------------------------+-----------------------------+---------+-------+------+------+ |conv_stream_AXILiteS_s_axi_U |conv_stream_AXILiteS_s_axi | 0| 0| 112| 168| |conv_stream_in_array_m_axi_U |conv_stream_in_array_m_axi | 2| 0| 512| 580| |conv_stream_out_array_m_axi_U |conv_stream_out_array_m_axi | 2| 0| 512| 580| |convolve_U0 |convolve | 0| 33| 4310| 5833| |read_pixel13_U0 |read_pixel13 | 0| 0| 58| 222| |write_pixel_U0 |write_pixel | 0| 0| 87| 228| +-------------------------------+-----------------------------+---------+-------+------+------+ |Total | | 4| 33| 5591| 7611| +-------------------------------+-----------------------------+---------+-------+------+------+ * DSP48: N/A * Memory: N/A * FIFO: +----------------------+---------+----+----+------+-----+---------+ | Name | BRAM_18K| FF | LUT| Depth| Bits| Size:D*B| +----------------------+---------+----+----+------+-----+---------+ |in_stream_V_U | 2| 50| 44| 32| 32| 1024| |out_array_offset_c_U | 0| 5| 44| 2| 32| 64| |out_stream_V_U | 2| 50| 44| 32| 32| 1024| +----------------------+---------+----+----+------+-----+---------+ |Total | 4| 105| 132| 66| 96| 2112| +----------------------+---------+----+----+------+-----+---------+ * Expression: +------------------------------+----------+-------+---+----+------------+------------+ | Variable Name | Operation| DSP48E| FF| LUT| Bitwidth P0| Bitwidth P1| +------------------------------+----------+-------+---+----+------------+------------+ |ap_idle | and | 0| 0| 8| 1| 1| |read_pixel13_U0_start_full_n | and | 0| 0| 8| 1| 1| +------------------------------+----------+-------+---+----+------------+------------+ |Total | | 0| 0| 16| 2| 2| +------------------------------+----------+-------+---+----+------------+------------+ * Multiplexer: N/A * Register: N/A ================================================================ == Interface ================================================================ * Summary: +--------------------------+-----+-----+------------+--------------+--------------+ | RTL Ports | Dir | Bits| Protocol | Source Object| C Type | +--------------------------+-----+-----+------------+--------------+--------------+ |s_axi_AXILiteS_AWVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_AWREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_AWADDR | in | 5| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WDATA | in | 32| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WSTRB | in | 4| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARADDR | in | 5| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RVALID | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RREADY | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RDATA | out | 32| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RRESP | out | 2| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BVALID | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BREADY | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BRESP | out | 2| s_axi | AXILiteS | scalar | |ap_clk | in | 1| ap_ctrl_hs | conv_stream | return value | |ap_rst_n | in | 1| ap_ctrl_hs | conv_stream | return value | |interrupt | out | 1| ap_ctrl_hs | conv_stream | return value | |m_axi_in_array_AWVALID | out | 1| m_axi | in_array | pointer | |m_axi_in_array_AWREADY | in | 1| m_axi | in_array | pointer | |m_axi_in_array_AWADDR | out | 32| m_axi | in_array | pointer | |m_axi_in_array_AWID | out | 1| m_axi | in_array | pointer | |m_axi_in_array_AWLEN | out | 8| m_axi | in_array | pointer | |m_axi_in_array_AWSIZE | out | 3| m_axi | in_array | pointer | |m_axi_in_array_AWBURST | out | 2| m_axi | in_array | pointer | |m_axi_in_array_AWLOCK | out | 2| m_axi | in_array | pointer | |m_axi_in_array_AWCACHE | out | 4| m_axi | in_array | pointer | |m_axi_in_array_AWPROT | out | 3| m_axi | in_array | pointer | |m_axi_in_array_AWQOS | out | 4| m_axi | in_array | pointer | |m_axi_in_array_AWREGION | out | 4| m_axi | in_array | pointer | |m_axi_in_array_AWUSER | out | 1| m_axi | in_array | pointer | |m_axi_in_array_WVALID | out | 1| m_axi | in_array | pointer | |m_axi_in_array_WREADY | in | 1| m_axi | in_array | pointer | |m_axi_in_array_WDATA | out | 32| m_axi | in_array | pointer | |m_axi_in_array_WSTRB | out | 4| m_axi | in_array | pointer | |m_axi_in_array_WLAST | out | 1| m_axi | in_array | pointer | |m_axi_in_array_WID | out | 1| m_axi | in_array | pointer | |m_axi_in_array_WUSER | out | 1| m_axi | in_array | pointer | |m_axi_in_array_ARVALID | out | 1| m_axi | in_array | pointer | |m_axi_in_array_ARREADY | in | 1| m_axi | in_array | pointer | |m_axi_in_array_ARADDR | out | 32| m_axi | in_array | pointer | |m_axi_in_array_ARID | out | 1| m_axi | in_array | pointer | |m_axi_in_array_ARLEN | out | 8| m_axi | in_array | pointer | |m_axi_in_array_ARSIZE | out | 3| m_axi | in_array | pointer | |m_axi_in_array_ARBURST | out | 2| m_axi | in_array | pointer | |m_axi_in_array_ARLOCK | out | 2| m_axi | in_array | pointer | |m_axi_in_array_ARCACHE | out | 4| m_axi | in_array | pointer | |m_axi_in_array_ARPROT | out | 3| m_axi | in_array | pointer | |m_axi_in_array_ARQOS | out | 4| m_axi | in_array | pointer | |m_axi_in_array_ARREGION | out | 4| m_axi | in_array | pointer | |m_axi_in_array_ARUSER | out | 1| m_axi | in_array | pointer | |m_axi_in_array_RVALID | in | 1| m_axi | in_array | pointer | |m_axi_in_array_RREADY | out | 1| m_axi | in_array | pointer | |m_axi_in_array_RDATA | in | 32| m_axi | in_array | pointer | |m_axi_in_array_RLAST | in | 1| m_axi | in_array | pointer | |m_axi_in_array_RID | in | 1| m_axi | in_array | pointer | |m_axi_in_array_RUSER | in | 1| m_axi | in_array | pointer | |m_axi_in_array_RRESP | in | 2| m_axi | in_array | pointer | |m_axi_in_array_BVALID | in | 1| m_axi | in_array | pointer | |m_axi_in_array_BREADY | out | 1| m_axi | in_array | pointer | |m_axi_in_array_BRESP | in | 2| m_axi | in_array | pointer | |m_axi_in_array_BID | in | 1| m_axi | in_array | pointer | |m_axi_in_array_BUSER | in | 1| m_axi | in_array | pointer | |m_axi_out_array_AWVALID | out | 1| m_axi | out_array | pointer | |m_axi_out_array_AWREADY | in | 1| m_axi | out_array | pointer | |m_axi_out_array_AWADDR | out | 32| m_axi | out_array | pointer | |m_axi_out_array_AWID | out | 1| m_axi | out_array | pointer | |m_axi_out_array_AWLEN | out | 8| m_axi | out_array | pointer | |m_axi_out_array_AWSIZE | out | 3| m_axi | out_array | pointer | |m_axi_out_array_AWBURST | out | 2| m_axi | out_array | pointer | |m_axi_out_array_AWLOCK | out | 2| m_axi | out_array | pointer | |m_axi_out_array_AWCACHE | out | 4| m_axi | out_array | pointer | |m_axi_out_array_AWPROT | out | 3| m_axi | out_array | pointer | |m_axi_out_array_AWQOS | out | 4| m_axi | out_array | pointer | |m_axi_out_array_AWREGION | out | 4| m_axi | out_array | pointer | |m_axi_out_array_AWUSER | out | 1| m_axi | out_array | pointer | |m_axi_out_array_WVALID | out | 1| m_axi | out_array | pointer | |m_axi_out_array_WREADY | in | 1| m_axi | out_array | pointer | |m_axi_out_array_WDATA | out | 32| m_axi | out_array | pointer | |m_axi_out_array_WSTRB | out | 4| m_axi | out_array | pointer | |m_axi_out_array_WLAST | out | 1| m_axi | out_array | pointer | |m_axi_out_array_WID | out | 1| m_axi | out_array | pointer | |m_axi_out_array_WUSER | out | 1| m_axi | out_array | pointer | |m_axi_out_array_ARVALID | out | 1| m_axi | out_array | pointer | |m_axi_out_array_ARREADY | in | 1| m_axi | out_array | pointer | |m_axi_out_array_ARADDR | out | 32| m_axi | out_array | pointer | |m_axi_out_array_ARID | out | 1| m_axi | out_array | pointer | |m_axi_out_array_ARLEN | out | 8| m_axi | out_array | pointer | |m_axi_out_array_ARSIZE | out | 3| m_axi | out_array | pointer | |m_axi_out_array_ARBURST | out | 2| m_axi | out_array | pointer | |m_axi_out_array_ARLOCK | out | 2| m_axi | out_array | pointer | |m_axi_out_array_ARCACHE | out | 4| m_axi | out_array | pointer | |m_axi_out_array_ARPROT | out | 3| m_axi | out_array | pointer | |m_axi_out_array_ARQOS | out | 4| m_axi | out_array | pointer | |m_axi_out_array_ARREGION | out | 4| m_axi | out_array | pointer | |m_axi_out_array_ARUSER | out | 1| m_axi | out_array | pointer | |m_axi_out_array_RVALID | in | 1| m_axi | out_array | pointer | |m_axi_out_array_RREADY | out | 1| m_axi | out_array | pointer | |m_axi_out_array_RDATA | in | 32| m_axi | out_array | pointer | |m_axi_out_array_RLAST | in | 1| m_axi | out_array | pointer | |m_axi_out_array_RID | in | 1| m_axi | out_array | pointer | |m_axi_out_array_RUSER | in | 1| m_axi | out_array | pointer | |m_axi_out_array_RRESP | in | 2| m_axi | out_array | pointer | |m_axi_out_array_BVALID | in | 1| m_axi | out_array | pointer | |m_axi_out_array_BREADY | out | 1| m_axi | out_array | pointer | |m_axi_out_array_BRESP | in | 2| m_axi | out_array | pointer | |m_axi_out_array_BID | in | 1| m_axi | out_array | pointer | |m_axi_out_array_BUSER | in | 1| m_axi | out_array | pointer | +--------------------------+-----+-----+------------+--------------+--------------+