================================================================ == Vivado HLS Report for 'compute_pixel' ================================================================ * Date: Tue May 29 19:06:49 2018 * Version: 2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017) * Project: edge_detection * Solution: axi_port_only * Product family: zynq * Target device: xc7z020clg484-1 ================================================================ == Performance Estimates ================================================================ + Timing (ns): * Summary: +--------+-------+----------+------------+ | Clock | Target| Estimated| Uncertainty| +--------+-------+----------+------------+ |ap_clk | 10.00| 9.17| 1.25| +--------+-------+----------+------------+ + Latency (clock cycles): * Summary: +-----+-----+-----+-----+----------+ | Latency | Interval | Pipeline | | min | max | min | max | Type | +-----+-----+-----+-----+----------+ | 53| 53| 5| 5| function | +-----+-----+-----+-----+----------+ + Detail: * Instance: N/A * Loop: N/A ================================================================ == Utilization Estimates ================================================================ * Summary: +-----------------+---------+-------+--------+-------+ | Name | BRAM_18K| DSP48E| FF | LUT | +-----------------+---------+-------+--------+-------+ |DSP | -| -| -| -| |Expression | -| -| 0| 24| |FIFO | -| -| -| -| |Instance | -| 7| 553| 1101| |Memory | -| -| -| -| |Multiplexer | -| -| -| 246| |Register | 0| -| 816| 128| +-----------------+---------+-------+--------+-------+ |Total | 0| 7| 1369| 1499| +-----------------+---------+-------+--------+-------+ |Available | 280| 220| 106400| 53200| +-----------------+---------+-------+--------+-------+ |Utilization (%) | 0| 3| 1| 2| +-----------------+---------+-------+--------+-------+ + Detail: * Instance: +-------------------------+----------------------+---------+-------+-----+-----+ | Instance | Module | BRAM_18K| DSP48E| FF | LUT | +-------------------------+----------------------+---------+-------+-----+-----+ |conv_stream_fadd_bkb_U6 |conv_stream_fadd_bkb | 0| 2| 205| 390| |conv_stream_fadd_bkb_U7 |conv_stream_fadd_bkb | 0| 2| 205| 390| |conv_stream_fmul_cud_U8 |conv_stream_fmul_cud | 0| 3| 143| 321| +-------------------------+----------------------+---------+-------+-----+-----+ |Total | | 0| 7| 553| 1101| +-------------------------+----------------------+---------+-------+-----+-----+ * DSP48: N/A * Memory: N/A * FIFO: N/A * Expression: +-----------------------------+----------+-------+---+----+------------+------------+ | Variable Name | Operation| DSP48E| FF| LUT| Bitwidth P0| Bitwidth P1| +-----------------------------+----------+-------+---+----+------------+------------+ |ap_block_pp0_stage0_11001 | and | 0| 0| 8| 1| 1| |ap_block_pp0_stage0_subdone | or | 0| 0| 8| 1| 1| |ap_enable_pp0 | xor | 0| 0| 8| 1| 2| +-----------------------------+----------+-------+---+----+------------+------------+ |Total | | 0| 0| 24| 3| 4| +-----------------------------+----------+-------+---+----+------------+------------+ * Multiplexer: +--------------------------+----+-----------+-----+-----------+ | Name | LUT| Input Size| Bits| Total Bits| +--------------------------+----+-----------+-----+-----------+ |A_address0 | 33| 6| 4| 24| |A_address1 | 27| 5| 4| 20| |ap_NS_fsm | 33| 6| 1| 6| |ap_enable_reg_pp0_iter0 | 9| 2| 1| 2| |ap_enable_reg_pp0_iter10 | 9| 2| 1| 2| |grp_fu_112_p0 | 33| 6| 32| 192| |grp_fu_112_p1 | 33| 6| 32| 192| |grp_fu_117_p0 | 27| 5| 32| 160| |grp_fu_117_p1 | 27| 5| 32| 160| |grp_fu_121_p1 | 15| 3| 32| 96| +--------------------------+----+-----------+-----+-----------+ |Total | 246| 46| 171| 854| +--------------------------+----+-----------+-----+-----------+ * Register: +-----------------------------+----+----+-----+-----------+ | Name | FF | LUT| Bits| Const Bits| +-----------------------------+----+----+-----+-----------+ |A_load_1_reg_193 | 32| 0| 32| 0| |A_load_3_reg_228 | 32| 0| 32| 0| |A_load_5_reg_248 | 32| 0| 32| 0| |A_load_7_reg_268 | 32| 0| 32| 0| |ap_CS_fsm | 5| 0| 5| 0| |ap_enable_reg_pp0_iter0_reg | 1| 0| 1| 0| |ap_enable_reg_pp0_iter1 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter10 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter2 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter3 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter4 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter5 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter6 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter7 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter8 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter9 | 1| 0| 1| 0| |result_2_0_1_reg_218 | 32| 0| 32| 0| |result_2_0_2_reg_233 | 32| 0| 32| 0| |result_2_1_1_reg_253 | 32| 0| 32| 0| |result_2_1_2_reg_258 | 32| 0| 32| 0| |result_2_1_reg_238 | 32| 0| 32| 0| |result_2_2_1_reg_278 | 32| 0| 32| 0| |result_2_2_reg_273 | 32| 0| 32| 0| |result_2_reg_213 | 32| 0| 32| 0| |tmp_10_0_2_reg_183 | 32| 0| 32| 0| |tmp_10_1_1_reg_198 | 32| 0| 32| 0| |tmp_10_2_2_reg_208 | 32| 0| 32| 0| |tmp_10_2_reg_203 | 32| 0| 32| 0| |tmp_s_reg_168 | 32| 0| 32| 0| |tmp_10_0_2_reg_183 | 64| 32| 32| 0| |tmp_10_1_1_reg_198 | 64| 32| 32| 0| |tmp_10_2_2_reg_208 | 64| 32| 32| 0| |tmp_10_2_reg_203 | 64| 32| 32| 0| +-----------------------------+----+----+-----+-----------+ |Total | 816| 128| 688| 0| +-----------------------------+----+----+-----+-----------+ ================================================================ == Interface ================================================================ * Summary: +------------+-----+-----+------------+---------------+--------------+ | RTL Ports | Dir | Bits| Protocol | Source Object | C Type | +------------+-----+-----+------------+---------------+--------------+ |ap_clk | in | 1| ap_ctrl_hs | compute_pixel | return value | |ap_rst | in | 1| ap_ctrl_hs | compute_pixel | return value | |ap_start | in | 1| ap_ctrl_hs | compute_pixel | return value | |ap_done | out | 1| ap_ctrl_hs | compute_pixel | return value | |ap_idle | out | 1| ap_ctrl_hs | compute_pixel | return value | |ap_ready | out | 1| ap_ctrl_hs | compute_pixel | return value | |ap_ce | in | 1| ap_ctrl_hs | compute_pixel | return value | |ap_return | out | 32| ap_ctrl_hs | compute_pixel | return value | |A_address0 | out | 4| ap_memory | A | array | |A_ce0 | out | 1| ap_memory | A | array | |A_q0 | in | 32| ap_memory | A | array | |A_address1 | out | 4| ap_memory | A | array | |A_ce1 | out | 1| ap_memory | A | array | |A_q1 | in | 32| ap_memory | A | array | +------------+-----+-----+------------+---------------+--------------+